Commit Graph

839700 Commits

Author SHA1 Message Date
Andy Shevchenko
a705f9c179 pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux()
By the fact byt_get_gpio_mux() returns a value of mux settings as
it is represented in hardware. Use defined macro instead of magic numbers
to clarify this.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20190703003018.75186-1-andriy.shevchenko@linux.intel.com
Reviewed-By: Enrico Weigelt <info@metux.net>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-04 09:48:49 +02:00
Prasad Sodagudi
57218371d5 pinctrl: qcom: Add SM8150 pinctrl driver
Add initial pinctrl driver to support pin configuration with
pinctrl framework for SM8150

Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
[vkoul: modify to use upstream tile support
	use upstream code style
	order the functions and squash functions]
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20190702105045.27646-4-vkoul@kernel.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-04 09:47:13 +02:00
Prasad Sodagudi
7f1fee22a2 dt-bindings: pinctrl: qcom: Add SM8150 pinctrl binding
Add the binding for the TLMM pinctrl block found in the SM8150 platform.

Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
[vkoul: add missing nodes of gpio range and reserved
	rewrote function names and order them]
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20190702105045.27646-3-vkoul@kernel.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-04 09:45:55 +02:00
Vinod Koul
80327437e3 dt-bindings: pinctrl: qcom: Document missing gpio nodes
The bindings for msm8998-pinctrl was missing gpio-ranges and
gpio-reserved-ranges, so document them as well

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20190702105045.27646-2-vkoul@kernel.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-04 09:44:43 +02:00
Andrew Jeffery
1bbe61d892 pinctrl: aspeed: Add implementation-related documentation
The ASPEED pinctrl driver implementations make heavy use of macros to
minimise tedium of implementation and maximise the chance that the
compiler will catch errors in defining signal and pin configurations.
While the goal of minimising errors is achieved, it is at the cost of
the complexity of the macros.

Document examples of the expanded form of pin declarations to
demonstrate the operation of the macros.

Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-9-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-03 10:38:58 +02:00
Andrew Jeffery
efa5623981 pinctrl: aspeed: Split out pinmux from general pinctrl
ASPEED have completely rearranged the System Control Unit register
layout with the AST2600. The existing code took advantage of the fact
that the AST2400 and AST2500 had layouts that were similar enough to
have little impact on the pinmux infrastructure (though there is a wart
with read-modify-write vs write-1-clear semantics of the hardware
strapping registers between the two).

Given that any similarity has been thrown out with the AST2600, separate
out the function applying an expression state to be driver-specific.
With it, extract out the pinmux macro jungle to its own header and
implementation so the pieces can be composed without dependency cycles.

Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-8-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-03 10:38:03 +02:00
Andrew Jeffery
d0d88b5c9e pinctrl: aspeed: Clarify comment about strapping W1C
Writes of 1 to SCU7C clear set bits in SCU70, the hardware strapping
register. The information was correct if you squinted while reading, but
hopefully switching the order of the registers as listed conveys it
better.

Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-7-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-03 10:35:21 +02:00
Andrew Jeffery
0290eba96b pinctrl: aspeed: Correct comment that is no longer true
We have handled the GFX register case for quite some time now.

Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-6-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-03 10:35:00 +02:00
Andrew Jeffery
053d8b2467 MAINTAINERS: Add entry for ASPEED pinctrl drivers
Add myself as maintainer to avoid burdening others with the madness.

Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-5-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-03 10:34:36 +02:00
Andrew Jeffery
0a617de167 dt-bindings: pinctrl: aspeed: Convert AST2500 bindings to json-schema
Convert ASPEED pinctrl bindings to DT schema format using json-schema.

Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-4-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-03 10:33:47 +02:00
Andrew Jeffery
07457937bb dt-bindings: pinctrl: aspeed: Convert AST2400 bindings to json-schema
Convert ASPEED pinctrl bindings to DT schema format using json-schema

Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-3-andrew@aj.id.au
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-03 10:30:16 +02:00
Andrew Jeffery
34ae69998b dt-bindings: pinctrl: aspeed: Split bindings document in two
Have one for each of the AST2400 and AST2500. The only thing that was
common was the fact that both support ASPEED BMC SoCs.

Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-2-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-03 10:29:21 +02:00
Srinivas Ramana
4b7618fdc7 pinctrl: qcom: Add irq_enable callback for msm gpio
Introduce the irq_enable callback which will be same as irq_unmask
except that it will also clear the status bit before unmask.

This will help in clearing any erroneous interrupts that would
have got latched when the interrupt is not in use.

There may be devices like UART which can use the same gpio line
for data rx as well as a wakeup gpio when in suspend. The data that
was flowing on the line may latch the interrupt and when we enable
the interrupt before going to suspend, this would trigger the
unexpected interrupt. This change helps clearing the interrupt
so that these unexpected interrupts gets cleared.

Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
Link: https://lore.kernel.org/r/1561472086-23360-1-git-send-email-neeraju@codeaurora.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-03 10:25:53 +02:00
Charles Keepax
4cb8df37a7 pinctrl: madera: Fixup SPDX headers
GPL-2.0-only is the preferred way of expressing v2 of the GPL, so switch
to that. Remove some redundant copyright notices and correct some
instances where the wrong comment type has been used in header files.

Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-26 09:51:37 +02:00
Nathan Chancellor
3fe2f17c0e pinctrl: qcom: sdm845: Fix CONFIG preprocessor guard
Clang warns when CONFIG_ACPI is unset:

 drivers/pinctrl/qcom/pinctrl-sdm845.c:1320:5: warning: 'CONFIG_ACPI' is
 not defined, evaluates to 0 [-Wundef]
 #if CONFIG_ACPI
     ^
 1 warning generated.

Use ifdef instead of if to resolve this.

Fixes: a229105d7a ("pinctrl: qcom: sdm845: Provide ACPI support")
Link: https://github.com/ClangBuiltLinux/linux/issues/569
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-25 16:06:23 +02:00
Thierry Reding
cf75b8f2cd pinctrl: tegra: Add bitmask support for parked bits
Some pin groups have park bits for multiple pins in one register.
Support this by turning the parked bit field into a parked bitmask
field. If no parked bits are supported, the bitmask can be 0.

Update the pingroup table on Tegra210, which is the only generation
where this is supported, with the parked bitmask.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-25 15:35:58 +02:00
Thierry Reding
55bd054ce4 pinctrl: tegra: Set specific GPIO compatible string
Rather than reuse the nvidia,tegra30-gpio compatible string
to find the GPIO controller on Tegra30, Tegra114, Tegra124 and
Tegra210, use the most specific compatible string for each
SoC generation for consistency.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-25 15:34:37 +02:00
Chris Packham
eed43e7e17 pinctrl: mvebu: Add support for MV98DX1135
The 98DX1135 is a switch chip with an integrated CPU. This is similar to
the 98DX4122 except the MPP assignments differ.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-25 14:25:31 +02:00
Chris Packham
7b34b0032b dt-bindings: pinctrl: mvebu: Document bindings for 98DX1135
The 98DX1135 is similar to the 98DX4122 except the MPP options differ.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-25 14:24:36 +02:00
Masahiro Yamada
ec6516bfba pinctrl: remove unneeded #ifdef around declarations
What is the point in surrounding the whole of declarations with
ifdef like this?

  #ifdef CONFIG_FOO
  int foo(void);
  #endif

If CONFIG_FOO is not defined, all callers of foo() will fail
with implicit declaration errors since the top Makefile adds
-Werror-implicit-function-declaration to KBUILD_CFLAGS.

This breaks the build earlier when you are doing something wrong.
That's it.

Anyway, it will fail to link since the definition of foo() is not
compiled.

In summary, these ifdef are unneeded.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-25 10:49:18 +02:00
Anson Huang
d9c238c5a6 pinctrl: freescale: Add i.MX8MN pinctrl driver support
Add the pinctrl driver support for i.MX8MN.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-25 10:40:23 +02:00
Anson Huang
124ecd6658 dt-bindings: imx: Add pinctrl binding doc for i.MX8MN
Add binding doc for i.MX8MN pinctrl driver.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-25 10:39:39 +02:00
Linus Walleij
a6c929f69f pinctrl: Minimize SPDX hamming distance
OK so some automatic scripts were fixing the SPDX tags in
the mainline branch while we were patching other stuff,
and yeah it is more correct to have "GPL-2.0-only" rather
than "GPL-2.0" so let's conform to what is already upstream
so we don't end up getting the wrong license on the merged
result later.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-20 10:54:55 +02:00
Masahiro Yamada
4eb293487d pinctrl: make pinconf.h self-contained
This header uses 'bool', but it does not include any header by itself.

So, it could cause unknown type name error, depending on the header
include order, although probably <linux/types.h> has been included by
someone else.

Include <linux/types.h> to make it self-contained.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-18 13:44:41 +02:00
Enrico Weigelt
d664c43958 gpio: Fix build warnings on undefined struct pinctrl_dev
This fixes the warnings:

* include/linux/gpio.h:254:11: warning: 'struct pinctrl_dev' declared
  inside parameter list will not be visible outside of this definition
  or declaration
* include/linux/gpio/driver.h:602:11: warning: 'struct pinctrl_dev'
  declared inside parameter list will not be visible outside of this
  definition or declaration

Fixes: 78b99577b3 ("pinctrl: remove unused pin_is_valid()")
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Enrico Weigelt <info@metux.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-13 02:38:28 +02:00
Icenowy Zheng
2e80e10f2d dt-bindings: pinctrl: add compatible string for Allwinner V3 pinctrl
The Allwinner V3 SoC, despite come with the same die with V3s, has more
GPIO pins than V3s, and a different compatible string for pinctrl is
needed.

Add the compatible string for V3 pinctrl.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-12 14:12:13 +02:00
Icenowy Zheng
1d90dff62e dt-bindings: pinctrl: add missing compatible string for V3s
The pinctrl driver of V3s is already available and used in the kernel,
but the compatible string of it is forgotten to be added.

Add the missing compatible string.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-12 14:11:02 +02:00
Linus Walleij
c204436506 Merge branch 'ib-qcom-acpi' into devel 2019-06-12 09:19:31 +02:00
Lee Jones
a229105d7a pinctrl: qcom: sdm845: Provide ACPI support
This patch provides basic support for booting with ACPI instead
of the currently supported Device Tree.  When doing so there are a
couple of differences which we need to taken into consideration.

Firstly, the SDM850 ACPI tables omit information pertaining to the
4 reserved GPIOs on the platform.  If Linux attempts to touch/
initialise any of these lines, the firmware will restart the
platform.

Secondly, when booting with ACPI, it is expected that the firmware
will set-up things like; Regulators, Clocks, Pin Functions, etc in
their ideal configuration.  Thus, the possible Pin Functions
available to this platform are not advertised when providing the
higher GPIOD/Pinctrl APIs with pin information.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-12 09:14:00 +02:00
Lee Jones
4c0efbfb26 pinctrl: msm: Add ability for drivers to supply a reserved GPIO list
When booting MSM based platforms with Device Tree or some ACPI
implementations, it is possible to provide a list of reserved pins
via the 'gpio-reserved-ranges' and 'gpios' properties respectively.
However some ACPI tables are not populated with this information,
thus it has to come from a knowledgable device driver instead.

Here we provide the MSM common driver with additional support to
parse this informtion and correctly populate the widely used
'valid_mask'.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-12 09:12:49 +02:00
Masahiro Yamada
78b99577b3 pinctrl: remove unused pin_is_valid()
This function was used by pin_request() to pointlessly double-check
the pin validity, and it was the only user ever.

Since commit d2f6a1c6fb ("pinctrl: remove double pin validity
check."), no one has ever used it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-12 09:10:54 +02:00
Masahiro Yamada
6cadafb310 pinctrl: remove unneeded initializer for list_for_each_entry() iterator
The iterator is initialized in list_for_each_entry().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-12 09:09:51 +02:00
Masahiro Yamada
f652e66fcc pinctrl: add include guard to pinctrl-state.h
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-09 16:53:22 +02:00
Geert Uytterhoeven
d6e561df50 dt-bindings: pinctrl: pic32: Spelling s/configuraion/configuration/
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-08 16:11:11 +02:00
Linus Walleij
6bd1eb6c5d pinctrl: sh-pfc: Updates for v5.3
- Add more checks for pinctrl table validation,
   - Add TPU (Timer Pulse Unit / PWM) pin groups on R-Car H3, M3-W, and
     M3-N,
   - Rework description of pins without GPIO functionality,
   - Small fixes and cleanups.
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Merge tag 'sh-pfc-for-v5.3-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v5.3

  - Add more checks for pinctrl table validation,
  - Add TPU (Timer Pulse Unit / PWM) pin groups on R-Car H3, M3-W, and
    M3-N,
  - Rework description of pins without GPIO functionality,
  - Small fixes and cleanups.
2019-06-08 01:32:19 +02:00
Linus Walleij
9d130f91a4 pinctrl: nomadik: Fix SPDX tags
Some files were missing the appropriate SPDX tags so
fixed it up.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-08 01:31:53 +02:00
Gustavo A. R. Silva
d32aa74555 pinctrl: tb10x: Use flexible-array member and struct_size() helper
Update the code to use a flexible array member instead of a pointer in
structure tb10x_pinctrl and use the struct_size() helper:

struct tb10x_pinctrl {
        ...
	struct tb10x_of_pinfunc pinfuncs[];
};

Also, make use of the struct_size() helper instead of an open-coded
version in order to avoid any potential type mistakes.

So, replace the following form:

sizeof(struct tb10x_pinctrl) + of_get_child_count(of_node) * sizeof(struct tb10x_of_pinfunc)

with:

struct_size(state, pinfuncs, of_get_child_count(of_node))

This code was detected with the help of Coccinelle.

Reviewed-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-08 01:29:43 +02:00
Hongwei Zhang
76c4c597b2 pinctrl: aspeed: Add SGPM pinmux
Add SGPM pinmux to ast2500-pinctrl function and group, to prepare for
supporting SGPIO in AST2500 SoC.

Signed-off-by: Hongwei Zhang <hongweiz@ami.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-08 01:29:43 +02:00
Bjorn Andersson
53a5372ce3 pinctrl: qcom: sdm845: Expose ufs_reset as gpio
The ufs_reset pin is expected to be wired to the reset pin of the
primary UFS memory but is pretty much just a general purpose output pinr

Reorder the pins and expose it as gpio 150, so that the UFS driver can
toggle it.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-08 01:29:42 +02:00
Manivannan Sadhasivam
9f1e3c5966 pinctrl: Add drive strength support for BM1880 SoC
Add drive strength support for Bitmain BM1880 SoC.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-08 01:29:42 +02:00
Manivannan Sadhasivam
7ea6a2edbf dt-bindings: pinctrl: Document drive strength settings for BM1880 SoC
Document drive strength settings for Bitmain BM1880 SoC.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-08 01:29:42 +02:00
Young Xiao
f38b506923 pinctrl: ns2: Fix potential NULL dereference
platform_get_resource() may fail and return NULL, so we should
better check it's return value to avoid a NULL pointer dereference
a bit later in the code.

Signed-off-by: Young Xiao <92siuyang@gmail.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-08 01:29:42 +02:00
Anson Huang
3a11cf2217 dt-bindings: imx: Correct pinfunc head file path for i.MX8MM
The i.MX8MM pinfunc head file is located in DT folder, correct it.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-08 01:29:42 +02:00
Linus Walleij
6c99d348fd pinctrl: u300: Fix SPDX tags
Some files were missing the appropriate SPDX tags so
fixed it up.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-08 01:29:42 +02:00
Geert Uytterhoeven
992968d786 pinctrl: sh-pfc: Remove obsolete SH_PFC_PIN_NAMED*() macros
Now all Renesas pin control drivers have been converted to use the new
non-GPIO helper macros, SH_PFC_PIN_NAMED() and SH_PFC_PIN_NAMED_CFG()
are no longer used.  Remove them.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04 11:19:25 +02:00
Geert Uytterhoeven
2549155932 pinctrl: sh-pfc: sh73a0: Use new macros for non-GPIO pins
Update the SH-Mobile AG5 pin control driver to use the new macros for
describing pins without GPIO functionality.  This replaces the use of
physical pin numbers on the SH-Mobile AG5 SoC (in 34x34 BGA package) by
symbolic enum values, referring to signal names.

Note that the user-visible names of these pins are still based on pin
numbers instead of signal names, to preserve DT backwards compatibility.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04 11:19:22 +02:00
Geert Uytterhoeven
7ad549ffcb pinctrl: sh-pfc: r8a77990: Use new macros for non-GPIO pins
Update the R-Car E3 pin control driver to use the new macros for
describing pins without GPIO functionality.  This replaces the use of
physical pin numbers on the R-Car E3 SoC (in 25x25 FCBGA package) by
symbolic enum values, referring to signal names.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04 11:19:20 +02:00
Geert Uytterhoeven
5da89cedce pinctrl: sh-pfc: r8a77965: Use new macros for non-GPIO pins
Update the R-Car M3-N pin control driver to use the new macros for
describing pins without GPIO functionality.  This replaces the use of
physical pin numbers on the R-Car M3-N SiP (in 39x39 BGA package) by
symbolic enum values, referring to signal names.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04 11:19:17 +02:00
Geert Uytterhoeven
168e18fd6c pinctrl: sh-pfc: r8a7796: Use new macros for non-GPIO pins
Update the R-Car M3-W pin control driver to use the new macros for
describing pins without GPIO functionality.  This replaces the use of
physical pin numbers on the R-Car M3-W SiP (in 39x39 BGA package) by
symbolic enum values, referring to signal names.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04 11:19:15 +02:00
Geert Uytterhoeven
42ee6c3395 pinctrl: sh-pfc: r8a7795: Use new macros for non-GPIO pins
Update the R-Car H3 ES2.0 and later pin control driver to use the new
macros for describing pins without GPIO functionality.  This replaces
the use of physical pin numbers on the R-Car H3 ES2.0 SiP (in 39x39
BGA package) by symbolic enum values, referring to signal names.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04 11:19:13 +02:00