- add DDR clock controller
- GPU OPP updates
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAl4XcxQACgkQWTcYmtP7
xmVjBhAAqL8rNKURAhAs7TkdgXxv3DGA1BlcMi0Sb/iuwlNBu5AbptO31FY7Jqb1
ZZ/GFRUljj1BHapjzekdMJUpqwQdPOtDKSrlhc65BkkAcgzXkzTlvvNiS/8/hMEC
RNrmT+O/YgOys/FpSc2wPdzg6WAgql9vhG0pAlI7gth3tPZxQosLTlzNDJ3yW9+K
qhPx5ivF1Q3w6TPnM0Q4eZj4MHnUSeQUDc6aA1b02V1ojt6pqeBkzVFzXyxdxWNs
yp3E8tLmNhQ6p2B3kCPTDt2H4jH1wEei1CrsnZFB4WMu80EoWnNi+VjsoBajmlR2
lufMkX623K47NlZiZ7/XQZ0ki5/09TqDJ4W53mPrpebJ7Cmw8sdSz/tMZ7cOveh0
FRa4VCSTiq4BxfdFks4vXPLDX40ucTXHA26jc1Hrrbb7n6uC93i87I5At7U03SY7
r4Lddd/1Rh6du7hLmxAEM5Ul9M5m82GYFYXgNKngsJHUxz/V1/Ym+rSzBFM/csBj
U2maAFYvvR8B3WBQfpONIYgUo5gJ8YgxglmboivZM226VgalPzsMtEm467xvROKn
xT7knR/pHu9wWL6OxCZGXsEQfjJM3FKn6Z1Fe2VolJpaouULdqBxWfRtnSMUwmgG
E/WqojV/8AOZSSqj6/ixQBr2Soaaim/Q2LmM81lBjcJ+bTCtSlA=
=CTqX
-----END PGP SIGNATURE-----
Merge tag 'amlogic-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt
ARM: dts: Amlogic updates for v5.6
- add DDR clock controller
- GPU OPP updates
* tag 'amlogic-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
ARM: dts: meson8b: use the actual frequency for the GPU's 364MHz OPP
ARM: dts: meson8: use the actual frequency for the GPU's 182.1MHz OPP
ARM: dts: meson8b: fix the clock controller compatible string
ARM: dts: meson8b: add the DDR clock controller
ARM: dts: meson8: add the DDR clock controller
ARM: dts: meson: provide the XTAL clock using a fixed-clock
dt-bindings: clock: meson8b: add the clock inputs
dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding
Link: https://lore.kernel.org/r/7hwo9udi7m.fsf@baylibre.com
Signed-off-by: Olof Johansson <olof@lixom.net>
It's fairly big this time, but the highlights are:
- Enable cpufreq and CPU thermal throttling on the A64
- CLK_CPUX macro usage removed (changed from first pull request)
- CSI0 support on the R40
- CSI1 support on the A10 and A20
- SPI support on the R40
- PMU support on the H3, H5, H6 and R40
- MIPI-DSI support on the A64
- PWM support on the H6
- Thermal sensor on the A64, A83t, H3, H5, H6 and R40
- More DT schemas fixes and conversions
- New boards: LibreComputer ALL-H5-CC H5, LibreComputer ALL-H3-IT H5,
Pine64 H64 Model B, Neutis N5H3
-----BEGIN PGP SIGNATURE-----
iQJCBAABCgAsFiEE2nN1m/hhnkhOWjtHOJpUIZwPJDAFAl4cOHUOHHdlbnNAY3Np
ZS5vcmcACgkQOJpUIZwPJDDMaw/8CYesTIYwsaPQpW6GnAe8lsB8qtOdIj2xhlzp
Qf3INpkH9lBl718lkwsOnVuQP8pJ75gp5J9yFNVuhSXTpWjpEJyKdiTa1e7TiZMj
LS7pKerFy7anZuL2bpgPAFHVyfokvnn8OGEc5tfHX0XJ8hQC+FnkzXpsxz7vYdP2
oxokLZNY/AeuTyPUG5/6KMkH2UJMlK9YRN7p/jPEKFXGlFy4bY9HKaIr3SxMMC7B
NwxYfFPdFVqODnHfWQq9TjXhPVXzHDg1B2bJT6yC1hjpNmDmqDZ6U8mj8v8aZy/u
x8WdUZbFALJeqL3J2ejsWbGsgwG3eMLOZVFIw9JEPgmqWE00pVnndu70P8hI3ZL0
7clq33b+EDjAf5B5oXUJPLdaW6DonWXHrBMbC1PaHwrPVZV+qZtoquAVwTR/WDk6
hnahfOGPB52y/OmxbrognU1dJwpHtVqgjvYjLMhXQoa4WaAS+fN7OBEDiYqC03Ty
Rsxd8iNaVnDVBovWbcnSpE9qG6i7hi9iZlt5LJJGalNxrs9RQ6ncDheyQtHS0TIl
BkwNkPMLy14mbLfiU3CvyDNZVgBIBaltsCVD0N6b5vZraizga4F4rS3FvoMR0JAJ
1bYXR7S53ga53k9t/VyVAEhoJt+5Bzy9WBbjLlL3IgT08K4N7dN/Y0cKKHt8Q7zx
QphJaBs=
=1h4A
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt-for-5.6-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
This is our usual set of DT patches for the Allwinner SoCs.
It's fairly big this time, but the highlights are:
- Enable cpufreq and CPU thermal throttling on the A64
- CLK_CPUX macro usage removed (changed from first pull request)
- CSI0 support on the R40
- CSI1 support on the A10 and A20
- SPI support on the R40
- PMU support on the H3, H5, H6 and R40
- MIPI-DSI support on the A64
- PWM support on the H6
- Thermal sensor on the A64, A83t, H3, H5, H6 and R40
- More DT schemas fixes and conversions
- New boards: LibreComputer ALL-H5-CC H5, LibreComputer ALL-H3-IT H5,
Pine64 H64 Model B, Neutis N5H3
* tag 'sunxi-dt-for-5.6-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (52 commits)
arm64: dts: allwinner: a64: enable DVFS
arm64: dts: allwinner: a64: add dtsi with CPU operating points
arm64: dts: allwinner: a64: add cooling maps and thermal tripping points
arm64: dts: allwinner: a64: add CPU clock to CPU0-3 nodes
arm64: dts: allwinner: sun50i-a64: Use macros for newly exported clocks
ARM: dts: sunxi: Use macros for references to CCU clocks
arm64: dts: allwinner: h5: Add Libre Computer ALL-H5-CC H5 board
ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes
arm64: dts: allwinner: a64: pinebook: Fix lid wakeup
ARM: dts: sun8i: r40: Add device node for CSI0
ARM: dts: sun7i: Add CSI1 controller and pinmux options
ARM: dts: sun4i: Add CSI1 controller and pinmux options
ARM: dts: sunxi: Add missing LVDS resets and clocks
ARM: dts: sun8i: r40: Use tcon top clock index macros
ARM: dts: sun8i: R40: Add PMU node
ARM: dts: sun8i: R40: Upgrade GICC reg size to 8K
arm64: dts: allwinner: h6: Add thermal sensor and thermal zones
ARM: dts: sunxi: Add Libre Computer ALL-H3-IT H5 board
arm64: dts: allwinner: a64: Add MIPI DSI pipeline
arm64: dts: allwinner: a64: Add thermal sensors and thermal zones
...
Link: https://lore.kernel.org/r/20200113095555.GA29848@wens.csie.org
Signed-off-by: Olof Johansson <olof@lixom.net>
- New board support: i.MX6SL based Tolino Shine 3 eBook reader,
i.MX7ULP Embedded Artists COM Board, i.MX6Q/DL based Gateworks
Ventana Boards.
- A couple of series from Andrey Smirnov to enhance i.MX6 RDU2 and
VF610 ZII boards.
- Add revision in board compatible string for imx6sx-sdb-reva and
imx7d-sdb-reva board.
- A fixup on imx6sl-tolino-shine3 board to remove incorrect power
supply assignment.
- Set initial buck regulator modes explicitly for phycore-imx6 board,
so that a wrong initial mode set by bootloader does not interfere.
- Add Add LCD support for imx7d-pico board.
- A couple of patches from Michael Grzeschik to enhance USB Host
support on i.MX25.
- A couple of patches from Michael Trimarchi to remove duplicate
Ethernet PHY reset properties on imx6qdl-icore and switch to
phy-handle.
- A couple of changes to add extirq node support on LS1021A SoC and
make use of it on the LS1021A-TSN board.
- A few random device additions and improvements on various boards.
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAl4b1tgUHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM4HTgf7B8jJJ80bk2Fu61b8o9yTXEdXHYQT
/xyW4IsPl/wJkHgPUyz5iYwebB0trmCfhD+guMCUcjQ9EiydQIq1CPYR5ibRsS+K
zQ8ctDB1ENxZeGgxX1aQ5u04YcuDzHWHQWuN7Bgg2/3h6CdhFb4NnOgwkFyJ445w
c4zcb9e3jfks7nVkKYreK5hOht7z8VLve+yzjQYPesscEuGdC/D7rEW6deuoWCau
k7Rf+VKJgEuh/9/DEfa9YZcPhQX8MVp6auzLBr45oxecUbiBDEe4BL+VPPtas3fL
borVRgA6InJaEaMByXbE1Xs+pIeJTow86yyoEKuQCa3QB1UDYc1BmY5cAQ==
=EI0g
-----END PGP SIGNATURE-----
Merge tag 'imx-dt-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX device tree update for 5.6:
- New board support: i.MX6SL based Tolino Shine 3 eBook reader,
i.MX7ULP Embedded Artists COM Board, i.MX6Q/DL based Gateworks
Ventana Boards.
- A couple of series from Andrey Smirnov to enhance i.MX6 RDU2 and
VF610 ZII boards.
- Add revision in board compatible string for imx6sx-sdb-reva and
imx7d-sdb-reva board.
- A fixup on imx6sl-tolino-shine3 board to remove incorrect power
supply assignment.
- Set initial buck regulator modes explicitly for phycore-imx6 board,
so that a wrong initial mode set by bootloader does not interfere.
- Add Add LCD support for imx7d-pico board.
- A couple of patches from Michael Grzeschik to enhance USB Host
support on i.MX25.
- A couple of patches from Michael Trimarchi to remove duplicate
Ethernet PHY reset properties on imx6qdl-icore and switch to
phy-handle.
- A couple of changes to add extirq node support on LS1021A SoC and
make use of it on the LS1021A-TSN board.
- A few random device additions and improvements on various boards.
* tag 'imx-dt-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (33 commits)
ARM: dts: imx: Add GW5912 board support
ARM: dts: imx: Add GW5913 board support
ARM: dts: imx: Add GW5910 board support
ARM: dts: imx: Add GW5907 board support
ARM: dts: imx6ul-14x14-evk: Pass the "broken-cd" property
ARM: dts: imx6sl-tolino-shine3: Remove incorrect power supply assignment
ARM: dts: imx7d-pico: Add LCD support
ARM: dts: imx6qdl-icore: Add fec phy-handle
ARM: dts: imx6qdl-icore-1.5: Remove duplicate phy reset methods
ARM: dts: imx7: Unify temp-grade and speed-grade nodes
ARM: dts: imx6: phycore-som: add pmic onkey device
ARM: dts: imx51-babbage: Fix the DVI output description
ARM: dts: imx6qdl-apalis: mux HDMI CEC pin
ARM: dts: imx6sll: add PXP module
ARM: dts: colibri-imx6ull: correct wrong pinmuxing and add comments
ARM: dts: vf610-zii-scu4-aib: Add node for switch watchdog
ARM: dts: vf610-zii-scu4-aib: Use generic names for DT nodes
ARM: dts: vf610-zii-dev-rev-b: Drop redundant I2C properties
ARM: dts: phycore-imx6: set buck regulator modes explicitly
ARM: dts: imx6: rdu2: Limit USBH1 to Full Speed
...
Link: https://lore.kernel.org/r/20200113034006.17430-4-shawnguo@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
This adds memory timings for the PAZ100 and does some minor cleanup for
the external memory controller device tree node on Tegra124.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl4ZDK0THHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zod47D/0UOgLf3UoDRORRNjS8X6cRf1cVXLSL
7tMf/U+5uusRWuZAZri4MfEKLA/pKbsEpHkGJvyFHb4lI8PX7sATZlM7dwoxo1VW
SwjsUKLBmtWhxamrVMxHFzwnSO+oiEZcDV4CZCsXyfiQlcfSQDStB4OpV1BXds0R
S+XPUNRJ4ojMvTMPYb0jZgGnfH54M7GAMUAqtKK4XsHn/GGviMNw2xTF1CYuIe+t
pQsKkElO4n7QAGw9DYXTHJiOthI8ZWkGWqG9/Pzim/UWjkm2g41OuMbBoP/rM06L
BnN6MuXrwM2kIn/Blm+d2xohp4Nvd3KZz2UdxPvue+148SpYyFaXJaetKxafDA1J
8fzfwqIsBMW5yrUsQdR0G0sbl96YWxmu1h54FPLTG08tpOXP9ilz+YFa22NiqAoj
KQ3xisbqrmcVrmOyGhs/IjbbDwM2lfhlOJ7O5AbhtxyrKRg1Qq4avvcf/8BNGi4B
w+zjmr3Ri8LMvVZ3FdlVcDZOEUDMWCfVkefQIjCSTsWTWgQnvR9UoE7DOArEXHxB
UXOczs4HrLoN3YAvRFfkjJWWfBhjqsDJrKzElHqyc2kV/SILzrUnrRHI79Q7jI/M
0W/u+ha1CNPzsNZ+eXipoSu4Ta1beUo7zj2z5cGiXKZjrYiwC3vrA5WlabbafEii
sVFGVaAVSLvFgA==
=U9nh
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-5.6-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
ARM: tegra: Device tree changes for v5.6-rc1
This adds memory timings for the PAZ100 and does some minor cleanup for
the external memory controller device tree node on Tegra124.
* tag 'tegra-for-5.6-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: dts: tegra20: paz00: Add memory timings
ARM: tegra: Rename EMC on Tegra124
ARM: tegra: Let the EMC hardware use the EMC clock
Link: https://lore.kernel.org/r/20200111003553.2411874-6-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
The Gateworks GW5907 is an IMX6 SoC based single board computer with:
- IMX6Q or IMX6DL
- 32bit DDR3 DRAM
- FEC GbE Phy
- bi-color front-panel LED
- 256MB NAND boot device
- Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
- Digital IO expander (pca9555)
- Joystick 12bit adc (ads1015)
Signed-off-by: Robert Jones <rjones@gateworks.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Samsung DTS ARM changes for v5.6
1. Couple ARM and wcore bus regulators on Exynos542x so higher
frequencies could be used with dynamic voltage and frequency scaling.
Enable this higher frequencies.
2. Correct the polarity of USB3503 hub GPIOs.
3. Adjust the bus frequencies (scaled with devfreq framework) on
Exynos5422 Odroid boards to match values possible to obtain from root
PLLs.
4. Add display to Tiny4412 board.
5. Cleanups and minor improvements.
* tag 'samsung-dt-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: Enable FIMD node and add proper panel node to Tiny4412
ARM: dts: samsung: Rename Samsung and Exynos to lowercase
ARM: dts: exynos: Adjust bus related OPPs to the values correct for Exynos5422 Odroids
ARM: dts: exynos: Move Exynos5420 bus related OPPs to the Odroid boards DTS
ARM: dts: exynos: Correct USB3503 GPIOs polarity
ARM: dts: exynos: Add missing CPU frequencies for Exynos5422/5800
ARM: dts: exynos: Add initial data for coupled regulators for Exynos5422/5800
ARM: dts: exynos: Remove syscon compatible from chipid node on Exynos5
Link: https://lore.kernel.org/r/20200110172334.4767-3-krzk@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
carrier board, separate versions for the two rockpro64 hardware revisions
which switched a pin between revisions. The rockpro64 also got
bluetooth support now.
The px30 got a lot of attention with dsi, gpu and thermal support.
Similarly the rk3399-roc-pc board also got attention with mtd flash,
sdr104 mode, hdmi sound, gpu and a lot of other smaller improvements.
Other than that there is a new gpu-cooling device for rk3399 a cpu
idle-state for rk3328 and more small improvements across a number
of boards.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAl4Xm7MQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgXPbB/4/iuGhWfydiiB6Mrmeifzlt+Ch7Hm5IJBA
03f8FiHbGkW1Tlh1buw6t9BDKI0XKNqD94MU0pya4yDB7baFaH1GEk8S4/mbEAuE
OZnWM0jzQ40b/1JmwRCw0PL2NTFHwlE+SSHnBJ4EW/OnOsCYUSz8+Aq33fMwdsPA
Dm9gxAeeHsBJTxk26cxLrGePB5vYXltGwazklkKkU5scV75sfJu1xcRKcnVp71sH
4j33aWi19GWo2YkW6RGXzTgiXoFPR+PgzfU337KTqq6A5oSIybH9g2WUnYyAxi8R
tJKxiOBSBeGIrIRxMWtw8g9VxohJwzHfi9y4XO1VwzLpl/SQf3mb
=iCh7
-----END PGP SIGNATURE-----
Merge tag 'v5.6-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
New boards are the Radxa Rock Pi N10 using the VMARC SOM and Dalang
carrier board, separate versions for the two rockpro64 hardware revisions
which switched a pin between revisions. The rockpro64 also got
bluetooth support now.
The px30 got a lot of attention with dsi, gpu and thermal support.
Similarly the rk3399-roc-pc board also got attention with mtd flash,
sdr104 mode, hdmi sound, gpu and a lot of other smaller improvements.
Other than that there is a new gpu-cooling device for rk3399 a cpu
idle-state for rk3328 and more small improvements across a number
of boards.
* tag 'v5.6-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (37 commits)
arm64: dts: rockchip: Enable mp8859 regulator on rk3399-roc-pc
arm64: dts: rockchip: rk3399-hugsun-x99: remove supports-sd and supports-emmc options
arm64: dts: rockchip: rk3399-firefly: remove num-slots from &sdio0 node
arm64: dts: rockchip: Add PX30 LVDS
arm64: dts: rockchip: add dsi controller for px30
arm64: dts: rockchip: Add PX30 DSI DPHY
arm64: dts: rockchip: Add RK3328 idle state
arm64: dts: rockchip: remove identical &uart0 node from rk3368-lion-haikou
arm64: dts: rockchip: Add Radxa Rock Pi N10 initial support
ARM: dts: rockchip: Add Radxa Dalang Carrier board
arm64: dts: rockchip: Add VMARC RK3399Pro SOM initial support
dt-bindings: arm: rockchip: Add Rock Pi N10 binding
arm64: dts: rockchip: hook up bluetooth at uart0 on rockpro64
arm64: dts: rockchip: enable wifi module at sdio0 on rockpro64
arm64: dts: rockchip: split rk3399-rockpro64 for v2 and v2.1 boards
arm64: dts: rockchip: enable the gpu on px30-evb
arm64: dts: rockchip: add the gpu for px30
dt-bindings: gpu: mali-bifrost: Add Rockchip PX30
arm64: dts: rockchip: Add GPU cooling device for RK3399
arm64: dts: rockchip: Add regulators for PCIe for Radxa Rock Pi 4 board
...
Link: https://lore.kernel.org/r/5115625.yBEeHQkg2z@phil
Signed-off-by: Olof Johansson <olof@lixom.net>
additional operating points for rk3288-tinker.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAl4Xk/0QHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgbR8B/9fX3OlIkdu19InRObH9COCjhgZNZQDTkcj
BDR2acJuVJlw409bxNJmWNp7/EvkNVv9y/8F5evqNTDx0qCWT7k05GaveXzwlVoE
FFoIlY1+6uuw/2zqCCI+PXDLSo7NKaNewUgmsdWMFfLPITK/Jh9QQgtq0Jw8xYjk
mpvv/BKWvwczj1Ms7Qx/jh9bKSxE8TyeLrLoEyUEYkqMvW+xf/5D4ahEPxwSWy9y
YumDskVBM+669aTLVSdCVKRZntZY8PdgGgo/l0uBTvIsS/GBvP0bdX8WZrwlvQeZ
02Mt/ef7xrA0QHjovypwkI7zZuBwTRSzUqbpTLnFy2HI4bKDiEh+
=+FbZ
-----END PGP SIGNATURE-----
Merge tag 'v5.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
Pin-name corrections for Veyron-Fievel, bluetooth for a number of veyron boards and
additional operating points for rk3288-tinker.
* tag 'v5.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: Use ABI name for recovery mode pin on veyron fievel/tiger
ARM: dts: rockchip: Use ABI name for write protect pin on veyron fievel/tiger
ARM: dts: rockchip: Add missing cpu operating points for rk3288-tinker
ARM: dts: rockchip: Add brcm bluetooth for rk3288-veyron
Link: https://lore.kernel.org/r/8215452.dU6eVM2tAM@phil
Signed-off-by: Olof Johansson <olof@lixom.net>
Highlights:
----------
MPU part:
-Add PWM support on DK2 board.
-Add counter support to STM32 timers.
-Add support of SDMMC 2&3 instances based on "arm,pl18x". SDMMC2 is
connected to eMMC on ED1 board. SDMMC3 is connected to the GPIO
extension connector on EV1 & DKx boards.
-Add ADC support on ED1 board.
-Update devicetree files split to better fit to STM32MP15 SOC & boards
diversity.
-Fix issues seen during YAML validation.
-Enable Ethernet (MAC) TX clock gating during low-power mode.
-Enable USB OTG HS support on DKx boards.
-Enable USB Host EHCI on DKx boards.
MCU part:
-Fix issues seen during YAML validation.
-----BEGIN PGP SIGNATURE-----
iQJMBAABCgA2FiEEctl9+nxzUSUqdELdf5rJavIecIUFAl4XFegYHGFsZXhhbmRy
ZS50b3JndWVAc3QuY29tAAoJEH+ayWryHnCFlvQP/RtwRkAPRWd5HHJraAzEj4gJ
vx5Hcm8TW4Fsu1oQnOPGHBNUJcoj5QvaCKhyqBP/gaffDnzJz4GZsaAGZ0FyQJd7
7IWqWOp2Ek2d5bklpLwmn4KU/5ZAqWTKOL1hYoEAvkXHdmxzcQi7pZOrvCG75GGs
lsqabxtx0S3NCCmVHy/CsmK2qkAxbASUG2oAn3pMIncUxdUyq2u97qhJB0zjM4TL
wE8nXNDPZk4P2ePi675PNo/nVP1WTbFHReHd+SCtjuKgQGFKIpnp3pNSP4jIrN+e
e2Wcb+5zQ10ZGntDDAwN+Ig+Nv7hOMLdbBB29kmRYoD4szFcYvjt+kdnXms/MWw8
vwBW6h6YLQ56zzhmcvD8vIwo5jI3l8jO7Gxk4OlK2tsyR+4HXpntkYuq2jOuVqoF
UuTrL4hMSoXrUOX+lfaGFC6x0NmblE+NWqbXEWfQ+mqb42z69O1d6Ws2vcl3CgWc
yUpCMOPkzb6ZIzc77+884COneZKqxRtpjNE7vaIUBEzVdxF6IIyaABBhBNbM3SE2
R/ibKOVh1OWpaYIi2qK7jhUMb5WjVt1jTCDVQmB1sYXzfbA2bzzc3iRVAwd1Oioc
W/wn7G3kh4PcwM8QHlbtuJwa5j/BBF4CNAk+pTXuVKX0eBgfgxGOE+PLTUowH1HA
iYXi2dMogCnXHxDvIBtX
=ch11
-----END PGP SIGNATURE-----
Merge tag 'stm32-dt-for-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt
STM32 DT updates for v5.6, round 1
Highlights:
----------
MPU part:
-Add PWM support on DK2 board.
-Add counter support to STM32 timers.
-Add support of SDMMC 2&3 instances based on "arm,pl18x". SDMMC2 is
connected to eMMC on ED1 board. SDMMC3 is connected to the GPIO
extension connector on EV1 & DKx boards.
-Add ADC support on ED1 board.
-Update devicetree files split to better fit to STM32MP15 SOC & boards
diversity.
-Fix issues seen during YAML validation.
-Enable Ethernet (MAC) TX clock gating during low-power mode.
-Enable USB OTG HS support on DKx boards.
-Enable USB Host EHCI on DKx boards.
MCU part:
-Fix issues seen during YAML validation.
* tag 'stm32-dt-for-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (37 commits)
ARM: dts: stm32: Add power-supply for RGB panel on stm32429i-eval
ARM: dts: stm32: Add power-supply for DSI panel on stm32f469-disco
ARM: dts: stm32: change nvmem node name on stm32mp1
ARM: dts: stm32: change nvmem node name on stm32f429
ARM: dts: stm32: update mlahb node according to the bindings on stm32mp15
ARM: dts: stm32: fix dma controller node name on stm32mp157c
ARM: dts: stm32: fix dma controller node name on stm32f743
ARM: dts: stm32: fix dma controller node name on stm32f746
ARM: dts: stm32: add phy-names to usbotg_hs on stm32mp157c-ev1
ARM: dts: stm32: enable USB OTG HS on stm32mp15 DKx boards
ARM: dts: stm32: enable USB Host (USBH) EHCI controller on stm32mp15 DKx
ARM: dts: stm32: enable USBPHYC on stm32mp15 DKx boards
ARM: dts: stm32: remove useless clock-names from RTC node on stm32f746
ARM: dts: stm32: remove useless clock-names from RTC node on stm32f429
ARM: dts: stm32: Enable MAC TX clock gating during TX low-power mode on stm32mp15
ARM: dts: stm32: adjust slew rate for Ethernet on stm32mp15
ARM: dts: stm32: remove syscfg clock on stm32mp15 ethernet
ARM: dts: stm32: remove "@" and "_" from stm32f7 pinmux groups
ARM: dts: stm32: remove "@" and "_" from stm32f4 pinmux groups
ARM: dts: stm32: Adapt STM32MP157C ED1 board to STM32 DT diversity
...
Link: https://lore.kernel.org/r/39df1dee-3c9f-cd35-bc55-a71223e07100@st.com
Signed-off-by: Olof Johansson <olof@lixom.net>
for 5.6, please pull the following:
- Stephan adds support for the HWRNG on 2711 (Raspberry Pi 4) which is
different than the previous Pi chips
- Florian switches the BCM956265HR board to use the hardware I2C
controllers for interfacing with the SFPs
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAl4WKTUACgkQh9CWnEQH
BwQ/8Q//dU5IKccRirODFKEZwgjFd70a7tnf5GelqeBA8WqmN3sqGbPHtlJ8ycca
C0ueafIas6zeTheHvbbraRYyHetLOQys++eOBVzp3m9BtyemQPcb1wgbGe2lnwPe
F3eJSq/EvWavauOul/POzv4wJpvoX3D1mI5fIAfg7n4sIYe2UWtVvVIO2V6XaBFG
LCcIxPSxSLC5tVAVFNdvCoBLUv2QrrUQs5OHybZNTRmOabscPZW+wptsIu3Cyzw7
Z4DaBpPTJzhLZu0b88Y5hca7+el3hZ+aCJ3AzjXxrzJjG7gUgNEQXOg2ygXPWETO
vGjc3IrptriHGtHzby/+JWLW4GlGBPvP0+YBD6R+dR74ZFWZp9kPkJjbIzCd0/Tq
ajootPE+P6JlS2fKEWhBZcMpsBsBurBdlhP56DzwCgKkrzQn4CxW9BDcjHJTVE6x
FG8S5pil+PdMTVEm20ZV+ZjkAtdsQ/YakXeuT9l44C9L3jgWw6bz4lB4kgB4acOP
bi6xJpJ1XNxdjsqotLeg7DD5I56c7ZMvAdxo18zEBPxXmvitoUjEQPCYLomvWPhd
l6PGAeNNZAPKKWLP25qRFLTbihlMfBXujE489JbraNLsrSvgwzzxXGykV6cSNUf2
jqeLRghxtZTXnG+BRXXo+aPAfPUK3hHol8Bs1aRyUHV5fZAjly4=
=EguA
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-5.6/devicetree' of https://github.com/Broadcom/stblinux into arm/dt
This pull request contains Broadcom ARM-based SoCs Device Tree changes
for 5.6, please pull the following:
- Stephan adds support for the HWRNG on 2711 (Raspberry Pi 4) which is
different than the previous Pi chips
- Florian switches the BCM956265HR board to use the hardware I2C
controllers for interfacing with the SFPs
* tag 'arm-soc/for-5.6/devicetree' of https://github.com/Broadcom/stblinux:
ARM: dts: bcm2711: Enable HWRNG support
ARM: dts: bcm2835: Move rng definition to common location
ARM: dts: NSP: Use hardware I2C for BCM958625HR
Link: https://lore.kernel.org/r/20200108191114.15987-1-f.fainelli@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
Currently the maximum rate for peripheral clock is calculated based on a
typical 133MHz MCK. The maximum frequency is defined in the datasheet as a
ratio to MCK. Some sama5d3 platforms are using a 166MHz MCK. Update the
device trees to match the maximum rate based on 166MHz.
Reported-by: Karl Rudbæk Olsen <karl@micro-technic.com>
Fixes: d2e8190b79 ("ARM: at91/dt: define sama5d3 clocks")
Link: https://lore.kernel.org/r/20200110172007.1253659-1-alexandre.belloni@bootlin.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
PAZ00 board has two variants of DDR2 SDRAM devices for External Memory:
one is Hynix HY5PS1G831CLFP-Y5 and the other is Micron MT47H128M8CF-25:H.
The Micron variant doesn't have official timings in the wild, hence only
timings for the Hynix are added. The memory frequency-scaling was tested
using the Tegra20 devfreq driver.
Tested-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The EMC hardware block needs access to the EMC clock in order to scale
the external memory frequency. Add the clocks property so that drivers
for the EMC can acquire a reference to the EMC clock.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add a fixed regulator and use it as power supply for RBG panel.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Add a fixed regulator and use it as power supply for DSI panel.
Fixes: 18c8866266 ("ARM: dts: stm32: Add display support on stm32f469-disco")
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Change non volatile node name from nvmem to efuse to be compliant
with yaml schema.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Change non volatile node name from nvmem to efuse to be compliant
with yaml schema.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Update of the mlahb node according to to DT bindings using json-schema
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Modify dma controller nodes name to fit with the standard naming.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Modify dma controller nodes name to fit with the standard naming.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Modify dma controller nodes name to fit with the standard naming.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
phy-names is required by usbotg_hs driver to get the phy, otherwise, it
considers that there is no phys property.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
This patch enables USB OTG HS on stm32mp15 dkx in Peripheral mode.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
This patch enables USB Host (USBH) EHCI controller on stm32mp15 dk boards.
As a hub is used between USBH and USB connectors, no need to enable
USBH OHCI controller: all low- and full-speed traffic is managed by the
hub.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
This patch enables USBPHYC (USB PHY Controller on stm32mp15 DKx boards.
This enables the two usbphyc usb2 ports, which require 3 supplies:
3v3, 1v1 and 1v8.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
imx6ul-14x14-evk does not have a GPIO dedicated for reading the card
detect pin on the eSDHC2 micro-SD port.
Pass the "broken-cd" property to describe the absence of the card detect
GPIO so that polling must be used.
According to Documentation/devicetree/bindings/mmc/mmc-controller.yaml:
broken-cd:
$ref: /schemas/types.yaml#/definitions/flag
description:
There is no card detection available; polling must be used.
Even though no error is oberved in the kernel, the lack of the
'broken-cd' property caused the micro-SD to not be detected in U-Boot,
so let's improve the device tree description to make it more accurate.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The vdd3p0 LDO's input should be from external USB VBUS directly, NOT
PMIC's power supply, the vdd3p0 LDO's target output voltage can be
controlled by SW, and it requires input voltage to be high enough, with
incorrect power supply assigned, if the power supply's voltage is lower
than the LDO target output voltage, it will return fail and skip the LDO
voltage adjustment, so remove the power supply assignment for vdd3p0 to
avoid such scenario.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add support for the VXT VL050-8048NT-C01 panel connected through
the 24 bit parallel LCDIF interface.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Joris Offouga <offougajoris@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
LAN8720 needs a reset of every clock enable. The reset needs
to be done at device level, due the flag PHY_RST_AFTER_CLK_EN.
So, add phy-handle by creating mdio child node inside fec.
This will eventually move the phy-reset-gpio which is defined
in fec node.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Engicam i.CoreM6 1.5 Quad/Dual MIPI dtsi is reusing fec node
from Engicam i.CoreM6 dtsi but have sampe copy of phy-reset-gpio
and phy-mode properties.
So, drop this phy reset methods from imx6qdl-icore-1.5 dsti file.
Cc: Jacopo Mondi <jacopo@jmondi.org>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The following warning is seen when building with W=1:
arch/arm/boot/dts/imx7s.dtsi:551.39-553.7: Warning (unique_unit_address): /soc/aips-bus@30000000/ocotp-ctrl@30350000/temp-grade@10: duplicate unit-address (also used in node /soc/aips-bus@30000000/ocotp-ctrl@30350000/speed-grade@10)
Since temp-grade and speed-grade point to the same node, replace them by
a single one to avoid the duplicate unit-address warning.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Without the onkey device it isn't possible to power off the system using
the X_PMIC_nONKEY signal which is routed to the SoM pin header.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The recovery mode pin is currently named 'REC_MODE_L', which is
how the signal is called in the schematics. The Chrome OS ABI
requires the pin to be named 'RECOVERY_SW_L', which is also how
it is called on all other veyron devices. Rename the pin to match
the ABI.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200108092908.1.I3afd3535b65460e79f3976e9ebfa392a0dd75e01@changeid
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Enable fimd device node which is a display controller, and add panel
node required by it.
Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
The clock setup on Meson8 cannot achieve a Mali frequency of exactly
182.15MHz. The vendor driver uses "FCLK_DIV7 / 1" for this frequency,
which translates to 2550MHz / 7 / 1 = 364285714Hz.
Update the GPU operating point to that specific frequency to not confuse
myself when comparing the frequency from the .dts with the actual clock
rate on the system.
Fixes: c3ea80b613 ("ARM: dts: meson8b: add the Mali-450 MP2 GPU")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The clock setup on Meson8 cannot achieve a Mali frequency of exactly
182.15MHz. The vendor driver uses "FCLK_DIV7 / 2" for this frequency,
which translates to 2550MHz / 7 / 2 = 182142857Hz.
Update the GPU operating point to that specific frequency to not confuse
myself when comparing the frequency from the .dts with the actual clock
rate on the system.
Fixes: 7d3f6b536e ("ARM: dts: meson8: add the Mali-450 MP6 GPU")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The Meson8b clock controller is an evolution of the Meson8 clock
controller. The clock controller on Meson8b contains two identical mali
clock trees for glitch-free rate switching.
Use the correct compatible string to make use of the glitch free mux.
Fixes: b6db3936f2 ("ARM: dts: meson: switch the clock controller to the HHI register area")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
SolidRun Clearfog Pro rev 2.1 and Clearfog Base rev 1.3 added EEPROM.
Add DT node for EEPROM description in the .dtsi shared by Clearfog Pro
and Base.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Move the i2c0 controller properties to the SOM .dtsi. This is
preparation for adding an i2c device at the SOM level.
Cc: Dennis Gilmore <dennis@ausil.us>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
