Commit Graph

60271 Commits

Author SHA1 Message Date
Chris Wilson
953d57eba5 drm/i915/gem: Limit the blitter sizes to ensure low preemption latency
Currently we insert a arbitration point every 128MiB during a blitter
copy. At 8GiB/s, this is around 30ms. This is a little on the large side
if we need to inject a high priority work, so reduced it down to 8MiB or
roughly 1ms.

v2: Don't forget both fill/copy.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191028203012.14566-1-chris@chris-wilson.co.uk
2019-10-28 20:40:50 +00:00
Michal Wajdeczko
19c17b763f drm/i915/execlists: Use vfunc to check engine submission mode
While processing CSB there is no need to look at GuC submission
settings, just check if engine is configured for execlists mode.

While today GuC submission is disabled it's settings are still
based on modparam values that might not correctly reflect actual
submission status in case of any fallback. Until that is fully
fixed, use alternate method to confirm that engine really runs in
execlists mode by comparing set_default_submission vfunc.

v2: add other immediate use of new helper

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
Reviewed-by: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191028164520.31772-1-michal.wajdeczko@intel.com
2019-10-28 20:40:07 +00:00
Chris Wilson
f9d9fece29 drm/i915/display: Mark conn as initialised by iterator
smatch complains about
drivers/gpu/drm/i915//display/intel_display.c:14403 intel_set_dp_tp_ctl_normal() error: uninitialized symbol 'conn'.
because it has no way to determine that the loop must have an entry.
Tell the static analysers to ignore the local, it will always be set.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191028142652.1987-2-chris@chris-wilson.co.uk
2019-10-28 16:09:44 +00:00
Chris Wilson
e7f536000c drm/i915/selftests: Initialise ret
Keep smatch quiet,

drivers/gpu/drm/i915//gem/selftests/i915_gem_context.c:1268 __igt_ctx_sseu() error: uninitialized symbol 'ret'.
drivers/gpu/drm/i915//gem/selftests/i915_gem_context.c:1280 __igt_ctx_sseu() error: uninitialized symbol 'ret'.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191028142652.1987-1-chris@chris-wilson.co.uk
2019-10-28 16:09:44 +00:00
Chris Wilson
370831fcb1 drm/i915/selftests: Initialise err in case there are no engines!
drivers/gpu/drm/i915//gt/selftest_engine_heartbeat.c:255 live_heartbeat_fast() error: uninitialized symbol 'err'.
drivers/gpu/drm/i915//gt/selftest_engine_heartbeat.c:320 live_heartbeat_off() error: uninitialized symbol 'err'.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191025135943.12524-2-chris@chris-wilson.co.uk
2019-10-28 16:09:44 +00:00
Chris Wilson
a7f328fc78 drm/i915/execlists: Simply walk back along request timeline on reset
The request's timeline will only contain requests from this context, in
order of execution. Therefore, we can simply look back along this
timeline to find the currently executing request.

If we do find that the current context has completed its last request,
that does not imply that all requests are completed in the context, so
only advance the ring->head up to the end of the known completions!

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191028124125.25176-1-chris@chris-wilson.co.uk
2019-10-28 16:09:44 +00:00
Chris Wilson
13670f4ce9 drm/i915/selftests: Check a few more fixed locations within the context image
As we use hard coded offsets for a few locations within the context
image, include those in the selftests to assert that they are valid.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191028121803.29408-1-chris@chris-wilson.co.uk
2019-10-28 16:09:43 +00:00
Christian König
a39414716c drm/amdgpu: add independent DMA-buf import v9
Instead of relying on the DRM functions just implement our own import
functions. This prepares support for taking care of unpinned DMA-buf.

v2: enable for all exporters, not just amdgpu, fix invalidation
    handling, lock reservation object while setting callback
v3: change to new dma_buf attach interface
v4: split out from unpinned DMA-buf work
v5: rebased and cleanup on new DMA-buf interface
v6: squash with invalidation callback change,
    stop using _(map|unmap)_locked
v7: drop invalidations when the BO is already in system domain
v8: rebase on new DMA-buf patch and drop move notification
v9: cleanup comments

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/337948/
2019-10-28 16:59:43 +01:00
Christian König
6e6db2722c drm/amdgpu: add independent DMA-buf export v8
Add an DMA-buf export implementation independent of the DRM helpers.

This not only avoids the caching of DMA-buf mappings, but also
allows us to use the new dynamic locking approach.

This is also a prerequisite of unpinned DMA-buf handling.

v2: fix unintended recursion, remove debugging leftovers
v3: split out from unpinned DMA-buf work
v4: rebase on top of new no_sgt_cache flag
v5: fix some warnings by including amdgpu_dma_buf.h
v6: fix locking for non amdgpu exports
v7: rebased on new DMA-buf locking patch
v8: drop extra include

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/337949/
2019-10-28 16:59:35 +01:00
Matt Roper
e5df52dcf8 drm/i915/tgl: Handle AUX interrupts for TC ports
We're currently only processing AUX interrupts on the combo ports; make
sure we handle the TC ports as well.

v2: Drop stale comment

Fixes: f663769a5e ("drm/i915/tgl: initialize TC and TBT ports")
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191024173023.22113-1-matthew.d.roper@intel.com
2019-10-28 08:27:04 -07:00
Kyle Mahlkuch
d02f5aab06 drm/radeon: Fix EEH during kexec
During kexec some adapters hit an EEH since they are not properly
shut down in the radeon_pci_shutdown() function. Adding
radeon_suspend_kms() fixes this issue.
Enabled only on PPC because this patch causes issues on some other
boards.

Signed-off-by: Kyle Mahlkuch <kmahlkuc@linux.vnet.ibm.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-28 11:19:17 -04:00
YueHaibing
b64919a236 drm/amd/powerplay: Make two functions static
Fix sparse warnings:

drivers/gpu/drm/amd/amdgpu/../powerplay/arcturus_ppt.c:2050:5:
 warning: symbol 'arcturus_i2c_eeprom_control_init' was not declared. Should it be static?
drivers/gpu/drm/amd/amdgpu/../powerplay/arcturus_ppt.c:2068:6:
 warning: symbol 'arcturus_i2c_eeprom_control_fini' was not declared. Should it be static?

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-28 11:19:17 -04:00
Wambui Karuga
f440ff44b1 drm/amd: correct "_LENTH" mispelling in constant
Correct the "_LENTH" mispelling in the AMDGPU_MAX_TIMEOUT_PARAM_LENGTH
constant.

Signed-off-by: Wambui Karuga <wambui.karugax@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-28 11:19:17 -04:00
Wambui Karuga
7e0ff20c7a drm/amd: declare amdgpu_exp_hw_support in amdgpu.h
Declare `amdgpu_exp_hw_support` as extern in amdgpu.h to address the
following sparse warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c:118:5: warning: symbol 'amdgpu_exp_hw_support' was not declared. Should it be static?

Signed-off-by: Wambui Karuga <wambui.karugax@gmail.com>
Suggested-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-28 11:19:17 -04:00
YueHaibing
4ef0b9d0a1 drm/amd/display: Make calculate_integer_scaling static
Fix sparse warning:

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_resource.c:963:6:
 warning: symbol 'calculate_integer_scaling' was not declared. Should it be static?

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-28 11:19:17 -04:00
Pelle van Gils
11436b0177 drm/amdgpu/powerplay/vega10: allow undervolting in p7
The vega10_odn_update_soc_table() function does not allow the SCLK
dependent voltage to be set for power-state 7 to a value below the default
in pptable. Change the for-loop condition to allow undervolting in the
highest state.

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205277
Signed-off-by: Pelle van Gils <pelle@vangils.xyz>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-28 11:19:17 -04:00
chen gong
f509be1840 drm/amd/powerplay: Disable gfx CGPG when suspend smu
if no disable gfx CGPG when suspend smu, enabling gfx CGPG will fail when resume smu.

Platform: Renoir
dmesg log information:

[  151.844110 ] amdgpu: [powerplay] SMU is resuming...
[  151.844116 ] amdgpu: [powerplay] dpm has been disabled
[  151.844604 ] amdgpu: [powerplay] Failed to send message 0x2f,response 0xfffffffb param 0x1
[  151.844605 ] amdgpu: [powerplay] SMU is resumed successfully!

Signed-off-by: chen gong <curry.gong@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-28 11:19:01 -04:00
Wambui Karuga
847a75fb9e drm/radeon: remove assignment for return value
Remove unnecessary assignment for return value and have the
function return the required value directly.
Issue found by coccinelle:
@@
local idexpression ret;
expression e;
@@

-ret =
+return
     e;
-return ret;

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Wambui Karuga <wambui@karuga.xyz>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-28 11:19:00 -04:00
zhongshiqi
039ffeaae3 dc.c:use kzalloc without test
dc.c:583:null check is needed after using kzalloc function

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: zhongshiqi <zhong.shiqi@zte.com.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-28 11:19:00 -04:00
Chenwandun
b69cd5dd01 drm/amd/display: remove gcc warning Wunused-but-set-variable
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c: In function dce_aux_configure_timeout:
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c: warning: variable timeout set but not used [-Wunused-but-set-variable]

Signed-off-by: Chenwandun <chenwandun@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-28 11:19:00 -04:00
Krzysztof Wilczynski
5a884be547
drm/exynos: Move static keyword to the front of declaration
Move the static keyword to the front of declaration of modes,
and resolve the following compiler warning that can be seen
when building with warnings enabled (W=1):

drivers/gpu/drm/exynos/exynos_mixer.c:1074:2: warning:
  ‘static’ is not at beginning of declaration [-Wold-style-declaration]

Signed-off-by: Krzysztof Wilczynski <kw@linux.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2019-10-28 21:12:27 +09:00
Chris Wilson
746078b334 drm/i915/selftests: Exercise adjusting rpcs over all render-class engines
Iterate over all user-accessible render engines when checking whether
they can be adjusted for sseu.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191027225808.19437-2-chris@chris-wilson.co.uk
2019-10-28 12:08:29 +00:00
Chris Wilson
6804da20bb drm/i915/selftests: Select a random engine for testing memory regions
Use any blitter engine at random for prefilling the memory region.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191027225808.19437-5-chris@chris-wilson.co.uk
2019-10-28 11:57:17 +00:00
Chris Wilson
5a3e2b82af drm/i915/gt: Tidy up rps irq handler to use intel_gt
Since the rps is tied to its intel_gt, use that backpointer to find the
right engine rather than delving into i915.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Andi Shyti <andi.shyti@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191027175505.25470-1-chris@chris-wilson.co.uk
2019-10-28 11:42:59 +00:00
Chris Wilson
c8c197d426 drm/i915/selftests: Use a random engine for GEM coherency tests
Select a random user accessible engine for checking coherency results.
While we should check all engines, we use a random selection so that
over repeated runs we cover all.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191027225808.19437-4-chris@chris-wilson.co.uk
2019-10-28 11:42:59 +00:00
Jani Nikula
96815f3d8b drm/i915/bios: add compression parameter block definition
Add definition for block 56, the compression parameters.

v2: add missing slice_height (Vandita)

Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191024075608.11511-1-jani.nikula@intel.com
2019-10-28 13:34:30 +02:00
Chris Wilson
52aac377e7 drm/i915/selftests: Check all blitter engines for client blt
Check all user accessible engines that can blit work with our blitter
client.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191027225808.19437-3-chris@chris-wilson.co.uk
2019-10-28 11:24:50 +00:00
Chris Wilson
1f9f6353e8 drm/i915/selftests: Drop global engine lookup for gt selftests
As we are inside the gt, we have a local gt->engine[] lookup we should
be using in preference over the i915->engine[] copy.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191027225808.19437-1-chris@chris-wilson.co.uk
2019-10-28 11:23:35 +00:00
Chris Wilson
39f9547a33 drm/i915/selftests: Measure basic throughput of blit routines
We need to verify that our blitter routines perform as expected, so
measure it.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191028112207.5464-1-chris@chris-wilson.co.uk
2019-10-28 11:22:58 +00:00
Ville Syrjälä
1d581dc3f5 drm/i915: Add CHICKEN_TRANS_D
Add CHICKEN_TRANS definition for transcoder D.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191024122138.25065-2-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2019-10-28 12:51:17 +02:00
Ville Syrjälä
12c4d4c18c drm/i915: Use _PICK() for CHICKEN_TRANS()
Make CHICKEN_TRANS() a bit less special looking by using _PICK().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191024122138.25065-1-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2019-10-28 12:47:55 +02:00
Thierry Reding
85d0c4b54f drm/tegra: sor: Introduce audio enable/disable callbacks
In order to support different modes (DP in addition to HDMI), split out
the audio setup/teardown into callbacks.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:57 +01:00
Thierry Reding
a9087cf2e1 drm/tegra: sor: Extract common audio enabling code
The code to enable audio support is split into two parts, one being
generic for the SOR and another part that is specific whether the SOR is
in HDMI mode or in DP mode. Split out the common part in preparation for
reusing the code in DP mode.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:57 +01:00
Thierry Reding
68a2ebb54d drm/tegra: sor: Avoid timeouts on unplug events
When the SOR is disabled in DP mode as part of an unplug event, do not
attempt to power the DP link down. Powering down the link requires the
DPAUX to transmit AUX messages which only works if there's a connected
sink.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:56 +01:00
Thierry Reding
d278e4a971 drm/tegra: sor: Unify eDP and DP support
The SOR0 on Tegra210 does, contrary to what was previously assumed, in
fact support DisplayPort. The difference between SOR0 and SOR1 is that
the latter supports audio and HDCP over DP, whereas the former doesn't.

The code for eDP and DP is now almost identical and the differences can
easily be parameterized based on the presence of a panel. There is no
need any longer to duplicate the code.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:56 +01:00
Thierry Reding
d23691f647 drm/tegra: sor: Use correct I/O pad for DP
The correct I/O pad needs to be powered up before DP can be used. Make
sure the correct default is set for Tegra generations where the I/O pad
cannot be derived from the SOR instance.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:56 +01:00
Thierry Reding
61417aaa11 drm/tegra: sor: Unify clock setup for eDP, HDMI and DP
With the clocks modelled consistently across SoC generations, the clock
setup for eDP, HDMI and DP can now be unified.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:56 +01:00
Thierry Reding
bae88815ad drm/tegra: sor: Support DisplayPort on Tegra194
Reuse parameters from earlier generations to support DisplayPort on
Tegra194.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:55 +01:00
Thierry Reding
1c3cc0df82 drm/tegra: sor: Deduplicate connector type detection code
The connector type detection code is duplicated in two places. Keeping
both places in sync is an extra maintenance burden that can be avoided
by comparing the connector type operations that are set upon the first
detection.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:55 +01:00
Thierry Reding
4bdf4710e0 drm/tegra: sor: Implement pad clock for all SOR instances
So far the pad clock was only needed on the second SOR instance. The
clock does exist for all SOR instances, though, so make sure it is
always implemented. This prepares for further unification of the code
in subsequent patches.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:55 +01:00
Thierry Reding
24e64f86da drm/tegra: sor: Use correct SOR index on Tegra210
The device tree bindings for the Tegra210 SOR don't require the
controller instance to be defined, since the instance can be derived
from the compatible string. The index is never used on Tegra210, so we
got away with it not getting set. However, subsequent patches will
change that, so make sure the proper index is used.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:54 +01:00
Thierry Reding
b9b9e19762 drm/tegra: sor: Remove tegra186-sor1 support
It turns out that SOR1 is just another instance of the same block as the
SOR0, so there is no need to distinguish them.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:54 +01:00
Thierry Reding
0472c21b83 drm/tegra: sor: Add DisplayPort support
Add support for regular DisplayPort on Tegra210 and Tegra186.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:54 +01:00
Thierry Reding
c9533131fe drm/tegra: sor: Filter eDP rates
The SOR found on Tegra SoCs does not support all the rates potentially
advertised by eDP 1.4. Make sure that the rates that are not supported
are filtered out.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:54 +01:00
Thierry Reding
38b445bc13 drm/tegra: sor: Stabilize eDP
Rework eDP code to correspond more closely to what's documented. This
also improves the reliability of modesets.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:53 +01:00
Thierry Reding
6f684de537 drm/tegra: sor: Hook up I2C-over-AUX to output
This is necessary for the output abstraction to retrieve a list of valid
modes from the EDID of a connected panel/monitor. This will be useful in
conjunction with DisplayPort support that will be added in a subsequent
patch, so that the driver can read EDID via the AUX channel.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:53 +01:00
Thierry Reding
c176393728 drm/tegra: sor: Use DP link training helpers
Make use of the DP link training helpers to implement full and fast link
training. While at it, refactor some of the code and remove various code
sequences that are not necessary.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:53 +01:00
Thierry Reding
078c445733 drm/tegra: dp: Add DisplayPort link training helper
Add a helper that will perform link training as described in the
DisplayPort specification.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:53 +01:00
Thierry Reding
6a127160c4 drm/tegra: dp: Add support for eDP link rates
Parses additional link rates from DPCD if the sink supports eDP 1.4.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:53 +01:00
Thierry Reding
01f09f242e drm/tegra: dp: Add drm_dp_link_choose() helper
This helper chooses an appropriate configuration, according to the
bitrate requirements of the video mode and the capabilities of the
DisplayPort sink.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:52 +01:00
Thierry Reding
c4a2728852 drm/tegra: dp: Enable alternate scrambler reset when supported
If the sink is eDP and supports the alternate scrambler reset, enable
it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:52 +01:00
Thierry Reding
553769ff8d drm/tegra: dp: Set channel coding on link configuration
Make use of ANSI 8B/10B channel coding if the DisplayPort sink supports
it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:52 +01:00
Thierry Reding
ad7f2dda38 drm/tegra: dp: Read AUX read interval from DPCD
Store the AUX read interval from DPCD, so that it can be used to wait
for the durations given in the specification during link training.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:52 +01:00
Thierry Reding
7aa3cc540d drm/tegra: dp: Read eDP version from DPCD
If the sink supports eDP, read the eDP revision from it's DPCD.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:45 +01:00
Thierry Reding
4ff9ba5674 drm/tegra: dp: Read alternate scrambler reset capability from sink
Parse from the sink capabilities whether or not the eDP alternate
scrambler reset value of 0xfffe is supported.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:45 +01:00
Thierry Reding
6c651b13e4 drm/tegra: dp: Read channel coding capability from sink
Parse from the sink capabilities whether or not it supports ANSI 8B/10B
channel coding as specified in ANSI X3.230-1994, clause 11.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:45 +01:00
Thierry Reding
db199502fa drm/tegra: dp: Read TPS3 capability from sink
The TPS3 capability can be exposed by DP 1.2 and later sinks if they
support the alternative training pattern for channel equalization.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:45 +01:00
Thierry Reding
cb072eebfa drm/tegra: dp: Read fast training capability from link
While probing the DisplayPort link, query the fast training capability.
If supported, drivers can use the fast link training sequence instead of
the more involved full link training sequence.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:44 +01:00
Thierry Reding
480770440a drm/tegra: dp: Probe link using existing parsing helpers
Use existing parsing helpers to probe a DisplayPort link.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:44 +01:00
Thierry Reding
27ba465ce3 drm/tegra: dp: Turn link capabilities into booleans
Rather than storing capabilities as flags in an integer, use a separate
boolean per capability. This simplifies the code that checks for these
capabilities.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:44 +01:00
Thierry Reding
c728e2d4a6 drm/tegra: dp: Track link capabilities alongside settings
Store capabilities in max_* fields and add separate fields for the
currently selected settings.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:44 +01:00
Thierry Reding
1abd6b3304 drm/tegra: dp: Add drm_dp_link_reset() implementation
Subsequent patches will add non-volatile fields to struct drm_dp_link,
so introduce a function to zero out only the volatile fields.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:44 +01:00
Thierry Reding
0fa5c1bdd2 drm/tegra: Add missing kerneldoc for struct drm_dp_link
The drm_dp_link structure tracks capabilities on the DP link. Add some
kerneldoc to explain what each of its fields means.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:44 +01:00
Thierry Reding
fc4ebe5287 drm/tegra: dpaux: Parameterize CMH, DRVZ and DRVI
The CMH, DRVZ and DRVI values vary depending on the SoC generation. Move
them into SoC specific structures so that DT compatible string matching
can be used to select the right parameters and write them to hardware at
the right time.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:43 +01:00
Thierry Reding
6c79f09fce drm/tegra: dpaux: Fix crash if VDD supply is absent
In order to properly make the VDD supply optional, all accesses to the
regulator need to be ignored, because the regulator core doesn't treat
NULL special.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:43 +01:00
Thierry Reding
245ce70cd4 drm/tegra: dpaux: Retry on transfer size mismatch
When a transfer didn't complete transmission of the requested number of
bytes, signal that the transaction should be retried.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:43 +01:00
Thierry Reding
5e881f6b29 drm/tegra: dpaux: Support monitor hotplugging
The dpaux driver has a quirk built-in that will delay initialization of
the display driver for a short while, trying to detect an eDP panel. The
reason for this quirk is that the panel may not report as connected
until after the display driver has initialized, at which point the fbdev
emulation will have fallen back to 1024x768 as default resolution, which
will likely not be the eDP panel's native resolution.

With upcoming DisplayPort support, the code needs to be able to cope
with hotpluggable monitors as well. Waiting for a panel to show up is no
longer going to work because the monitor may not be attached on boot. If
the output runs in DisplayPort mode, skip waiting for the panel to show
up.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:43 +01:00
Thierry Reding
acf6b77c4c drm/tegra: gem: Use sg_alloc_table_from_pages()
Instead of manually creating the SG table for a discontiguous buffer,
use the existing sg_alloc_table_from_pages(). Note that this is not safe
to be used with the ARM DMA/IOMMU integration code because that will not
ensure that the whole buffer is mapped contiguously. Depending on the
size of the individual entries the mapping may end up containing holes
to ensure alignment.

However, we only ever use these buffers with explicit IOMMU API usage
and know how to avoid these holes.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:42 +01:00
Thierry Reding
8b5a3c17a2 drm/tegra: gem: Always map SG tables for DMA-BUFs
When an importer wants to map a DMA-BUF, make sure to always actually
map it, irrespective of whether the buffer is contiguous or not.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:40 +01:00
Thierry Reding
d81f3431e6 drm/tegra: gem: Use dma_get_sgtable()
Rather than manually creating an SG table in an incorrect way, let the
standard dma_get_sgtable() function do it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:39 +01:00
Thierry Reding
7e3c53a096 drm/tegra: gem: Rename paddr -> iova
The address can refer to either physical memory or IO virtual memory.
If referring to IO virtual memory, there will always be an associated
physical memory address. Rename this variable to "iova" to clarify in
all cases that this is the IO virtual memory, which in the absence of
an IOMMU is identical to the physical address.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:38 +01:00
Thierry Reding
aacdf19849 drm/tegra: Move IOMMU group into host1x client
Handling of the IOMMU group attachment is common to all clients, so move
the group into the client to simplify code.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:37 +01:00
Thierry Reding
7baa943e0b drm/tegra: vic: Use common IOMMU attach/detach code
Reuse common code to attach to or detach from an IOMMU domain.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:36 +01:00
Thierry Reding
d5ad0e3dfe drm/tegra: vic: Inherit DMA mask from host1x
VIC, just like all other host1x clients, has the same addressing range
as its parent host1x device. Inherit the DMA mask to reflect that.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:35 +01:00
Thierry Reding
dd631e8ac9 drm/tegra: vic: Skip stream ID programming without IOMMU
If VIC is not behind an IOMMU, don't touch any of the registers related
to stream ID programming.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:35 +01:00
Thierry Reding
0301196b57 drm/tegra: Use DRM_DEBUG_DRIVER for driver messages
The driver-specific messages should use the DRM_UT_DRIVER category so
that they can be properly filtered.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:35 +01:00
Thierry Reding
47b15779b0 drm/tegra: Inherit device DMA parameters from host1x
The display controllers and VIC don't have any limitations on the
DMA segment size. Inherit the DMA parameters from the parent device,
which also doesn't have any such limitations.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:34 +01:00
Ben Dooks (Codethink)
33904487f1 gpu: host1x: Make host1x_cdma_wait_pushbuffer_space() static
The host1x_cdma_wait_pushbuffer_space() function is not declared or
directly called from outside the file it is in, so make it static.

Fixes the following sparse warning:

    drivers/gpu/host1x/cdma.c:235:5: warning: symbol 'host1x_cdma_wait_pushbuffer_space' was not declared. Should it be static?

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:34 +01:00
Thierry Reding
caccddcfc4 gpu: host1x: Request channels for clients, not devices
A struct device doesn't carry much information that a channel might be
interested in, but the client very much does. Request channels for the
clients rather than their parent devices and store a pointer to them
in order to have that information available when needed.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:33 +01:00
Thierry Reding
8f45f5071a gpu: host1x: Explicitly initialize host1x_info structures
It's technically not required to explicitly initialize the fields that
will be zero by default, but it's easier to read these structures if
they are all initialized uniformly.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:33 +01:00
Thierry Reding
b9cd7b954a gpu: host1x: Remove gratuitous blank line
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:33 +01:00
Thierry Reding
d98914ebc2 gpu: host1x: Do not limit DMA segment size
host1x nor any its clients have any limitations on the DMA segment size,
so don't pretend that they do.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:08 +01:00
Thomas Zimmermann
8e86dee022 drm/fb-helper: Remove drm_fb_helper_defio_init() and update docs
There are no users of drm_fb_helper_defio_init(), so we can remove
it. The documentation around defio support is a bit misleading and
should mention compatibility issues with SHMEM helpers. Clarify this.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Noralf Trønnes <noralf@tronnes.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20191025092759.13069-2-tzimmermann@suse.de
2019-10-28 10:07:54 +01:00
Chris Wilson
dd095afc88 drm/i915/rps: Flip interpretation of ips fmin/fmax to max rps
ips uses clock delays as opposed to rps frequency bins. To fit the
delays into the same rps calculations, we need to invert the ips delays.

Fixes: 3e7abf8141 ("drm/i915: Extract GT render power state management")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Andi Shyti <andi.shyti@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191026200917.1780-1-chris@chris-wilson.co.uk
2019-10-27 20:44:48 +00:00
Chris Wilson
d9d54a530a drm/i915: Put future HW and their uAPIs under STAGING & BROKEN
We would like some freedom to break the user API/ABI for future HW but
yet still expose the driver for upstream development on that HW.
Currently, we have the i915.force_probe module parameter to avoid binding
to HW while the driver is under development, but that is still a little
too soft with respect to the stringent no-regression rules if we also
plan to be redesigning the uAPI to go along with the new HW.

To allow the uAPI to be changed during development, only expose that API
and in development HW under STAGING (and BROKEN). Hopefully, making it
explicit that such interfaces to that HW are under development and not
to be blindly enabled by distributions.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dave Airlie <airlied@redhat.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191027154314.11139-1-chris@chris-wilson.co.uk
2019-10-27 15:47:10 +00:00
Chris Wilson
3fc794f27f drm/i915: Split memory_region initialisation into its own file
Pull the memory region bookkeeping into its file. Let's start clean and
see how long it lasts!

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191026202032.4371-1-chris@chris-wilson.co.uk
2019-10-26 22:25:34 +01:00
Andi Shyti
9fb94522dd drm/i915: Extract the GuC interrupt handlers
Pull the GuC interrupt handlers out of i915_irq.c. They now use the GT
interrupt facilities rather than the central dispatch.

Based on a patch by Chris Wilson.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191024211642.7688-2-chris@chris-wilson.co.uk
2019-10-26 19:28:59 +01:00
Andi Shyti
3e7abf8141 drm/i915: Extract GT render power state management
i915_irq.c is large. One reason for this is that has a large chunk of
the GT render power management stashed away in it. Extract that logic
out of i915_irq.c and intel_pm.c and put it under one roof.

Based on a patch by Chris Wilson.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191024211642.7688-1-chris@chris-wilson.co.uk
2019-10-26 19:28:59 +01:00
Chris Wilson
35865aef05 drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image
The location of RING_MI_MODE (used to stop the ring across resets) moved
for Tigerlake. Fixup the new location and include a selftest to verify
the location in the default context image.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191026082220.32632-1-chris@chris-wilson.co.uk
2019-10-26 09:48:34 +01:00
Chris Wilson
babaab2f47 drm/i915: Encapsulate kconfig constant values inside boolean predicates
Avoid angering clang and smatch by using a constant value in a '&&' test,
by forcing that constant value into a boolean.

E.g.,
drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:159:13: warning: use of logical '&&' with constant operand [-Wconstant-logical-operand]
	if (!delay && CONFIG_DRM_I915_PREEMPT_TIMEOUT) {
                      ^  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Nathan Chancellor <natechancellor@gmail.com>
Cc: Nick Desaulniers <ndesaulniers@google.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Nathan Chancellor <natechancellor@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191025135943.12524-1-chris@chris-wilson.co.uk
2019-10-26 09:25:25 +01:00
José Roberto de Souza
2d69c42e37 drm/i915/tc: Clear DKL_TX_PMD_LANE_SUS before program voltage swing
This sequence was recently added to fix internal HW sequences to
reset TC ports.

HSDES: 1507287614
HSDES: 14010071447
BSpec: 49292
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191021223408.87344-1-jose.souza@intel.com
2019-10-25 15:58:07 -07:00
Chris Wilson
c442292a66 drm/i915/pmu: Initialise the spinlock before registering
As the GT may be running in parallel with the module initialisation
code, we may enter i915_pmu_gt_parked() as we are executing
i915_pmu_register(). We have to init the spinlock before we mark
pmu.event_init so that it is available for use by i915_pmu_gt_parked()
(which may run as soon as event_init is set).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112127
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191025165442.23356-1-chris@chris-wilson.co.uk
2019-10-25 22:56:14 +01:00
Matthew Auld
0e99f939f0 drm/i915/selftests/blt: add some kthreads into the mix
We can be more aggressive in our testing by launching a number of
kthreads, where each is submitting its own copy or fill batches on a set
of random sized objects. Also since the underlying fill and copy batches
can be pre-empted mid-batch(for particularly large objects), throw in a
random mixture of ctx priorities per thread to make pre-emption a
possibility.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191025172511.25742-1-matthew.auld@intel.com
2019-10-25 22:56:12 +01:00
Matthew Auld
dd158d71a0 drm/i915/selftests: add sanity selftest for huge-GTT-pages
Now that for all the relevant backends we do randomised testing, we need
to make sure we still sanity check the obvious cases that might blow up,
such that introducing a temporary regression is less likely.  Also
rather than do this for every backend, just limit to our two memory
types: system and local.

Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191025153728.23689-7-chris@chris-wilson.co.uk
2019-10-25 22:56:05 +01:00
Matthew Auld
11d723ceb2 drm/i915/selftests: prefer random sizes for the huge-GTT-page smoke tests
Ditch the dubious static list of sizes to enumerate, in favour of
choosing a random size within the limits of each backing store. With
repeated CI runs this should give us a wider range of object sizes, and
in turn more page-size combinations, while using less machine time.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191025153728.23689-6-chris@chris-wilson.co.uk
2019-10-25 22:56:00 +01:00
Matthew Auld
23741bc81d drm/i915/selftests: extend coverage to include LMEM huge-pages
Add LMEM objects to list of backends we test for huge-GTT-pages.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191025153728.23689-5-chris@chris-wilson.co.uk
2019-10-25 22:55:55 +01:00
Matthew Auld
340be48f2c drm/i915/selftests: add write-dword test for LMEM
Simple test writing to dwords across an object, using various engines in
a randomized order, checking that our writes land from the cpu.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191025153728.23689-4-chris@chris-wilson.co.uk
2019-10-25 22:55:49 +01:00
Abdiel Janulgue
01377a0d7e drm/i915/lmem: support kernel mapping
We can create LMEM objects, but we also need to support mapping them
into kernel space for internal use.

Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Steve Hampson <steven.t.hampson@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191025153728.23689-3-chris@chris-wilson.co.uk
2019-10-25 22:55:43 +01:00
Abdiel Janulgue
cb6d2467ac drm/i915: setup io-mapping for LMEM
Create an io-mapping to describe the CPU aperture for lmem.

Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191025153728.23689-2-chris@chris-wilson.co.uk
2019-10-25 22:55:37 +01:00
Matthew Auld
b908be543e drm/i915: support creating LMEM objects
We currently define LMEM, or local memory, as just another memory
region, like system memory or stolen, which we can expose to userspace
and can be mapped to the CPU via some BAR.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191025153728.23689-1-chris@chris-wilson.co.uk
2019-10-25 22:55:31 +01:00
Lucas De Marchi
7be8782a50 drm/i915: split gen11_irq_handler to make it shareable
Split gen11_irq_handler() to receive as parameter the function
pointers. This allows to share the interrupt handler even if the enable/disable
functions are different.

Make sure it's always inlined to avoid the extra indirect call on the
hot path. Checking with gcc 9 this produce the exact same code as of
now:

$ size drivers/gpu/drm/i915/i915_irq*.o
   text	   data	    bss	    dec	    hex	filename
  47511	    560	      0	  48071	   bbc7	drivers/gpu/drm/i915/i915_irq.o
  47511	    560	      0	  48071	   bbc7	drivers/gpu/drm/i915/i915_irq_new.o

$ gdb -batch -ex 'file drivers/gpu/drm/i915/i915_irq.o' -ex 'disassemble gen11_irq_handler' > /tmp/old.s
$ gdb -batch -ex 'file drivers/gpu/drm/i915/i915_irq_new.o' -ex 'disassemble gen11_irq_handler' > /tmp/new.s
$ git diff --no-index /tmp/{old,new}.s
$

So, no change in behavior, just a simple refactor.

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191024195122.22877-4-lucas.demarchi@intel.com
2019-10-25 13:55:49 -07:00
Lucas De Marchi
e6e2ac0711 drm/i915: do not set MOCS control values on dgfx
On dgfx there's no LLC and eDRAM control table. Since now this
also means the device has global MOCS, just return early on the
initialization function.

L3 settings still apply and still need to be tweaked.

Bspec: 45101

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191024195122.22877-3-lucas.demarchi@intel.com
2019-10-25 13:55:49 -07:00
Stuart Summers
d8203d398c drm/i915: add new gen12 dgfx platform macro
Add a new macro for GEN12 platforms to be grouped under dgfx feature
set.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191024195122.22877-2-lucas.demarchi@intel.com
2019-10-25 13:54:00 -07:00
José Roberto de Souza
dc90fe3fd2 drm/i915: Add is_dgfx to device info
This will be helpful to diferentiate a set of GPUs
with the same GEN version.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191024195122.22877-1-lucas.demarchi@intel.com
2019-10-25 13:53:51 -07:00
Andrey Grodzovsky
db5e65fcb3 drm/amdgpu: If amdgpu_ib_schedule fails return back the error.
Use ERR_PTR to return back the error happened during amdgpu_ib_schedule.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:11 -04:00
Andrey Grodzovsky
e91e5f080e drm/sched: Set error to s_fence if HW job submission failed.
Problem:
When run_job fails and HW fence returned is NULL we still signal
the s_fence to avoid hangs but the user has no way of knowing if
the actual HW job was ran and finished.

Fix:
Allow .run_job implementations to return ERR_PTR in the fence pointer
returned and then set this error for s_fence->finished fence so whoever
wait on this fence can inspect the signaled fence for an error.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:11 -04:00
chen gong
42ce4b666d drm/amdgpu/powerplay: modify the parameters of SMU_MSG_PowerUpVcn to 0
The parameters what SMU_MSG_PowerUpVcn need is 0, not 1

Signed-off-by: chen gong <curry.gong@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:11 -04:00
Tianci.Yin
dcc0fcff14 drm/amdgpu/gfx10: update gfx golden settings for navi12
update registers: mmCGTT_SPI_CLK_CTRL

Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:11 -04:00
Tianci.Yin
21c943f35a drm/amdgpu/gfx10: update gfx golden settings for navi14
update registers: mmCGTT_SPI_CLK_CTRL

Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:11 -04:00
Tianci.Yin
d753dc6ab2 drm/amdgpu/gfx10: update gfx golden settings
update registers: mmCGTT_SPI_CLK_CTRL

Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:11 -04:00
Evan Quan
59e038d067 drm/amd/powerplay: correct current clock level label for Arcturus
For dpm disabled case, it's assumed the only one support clock
level is always current clock level.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:11 -04:00
Evan Quan
0525f29713 drm/amd/powerplay: skip unsupported clock limit settings on Arcturus V2
For Arcturus, clock limit settings on uclk/socclk/fclk domains
are not supported.

V2: simplify the code to support both SGPU and MGPU cases

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:10 -04:00
Marek Olšák
664fe85a2d drm/amdgpu: Allow reading more status registers on si/cik
Allow userspace to read the same status registers for every family.
Based on commit c7890fea, added any of these registers if defined in
the include files of each architecture.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:10 -04:00
Andrey Grodzovsky
121a2bc6ae drm/amdgpu: Move amdgpu_ras_recovery_init to after SMU ready.
For Arcturus the I2C traffic is done through SMU tables and so
we must postpone RAS recovery init to after they are ready
which is in amdgpu_device_ip_hw_init_phase2.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:10 -04:00
Andrey Grodzovsky
cf52ecc8b6 drm/amdgpu: Use ARCTURUS in RAS EEPROM.
Add Arcturus EEPROM/I2C support in generic EEPROM code.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:10 -04:00
Andrey Grodzovsky
d1a84427ad drm/amd/powerplay: Add EEPROM I2C read/write support to Arcturus.
The communication is done through SMU table and hence the code
is in powerplay.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:10 -04:00
Andrey Grodzovsky
7388ccf968 drm/amd/powerplay: Add interface for I2C transactions to SMU.
Will be used by Arcturus support for RAS page retirement.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:10 -04:00
Leo Li
eaf56410cc drm/amdgpu: Add DC feature mask to disable fractional pwm
[Why]

Some LED panel drivers might not like fractional PWM. In such cases,
backlight flickering may be observed.

[How]

Add a DC feature mask to disable fractional PWM, and associate it with
the preexisting dc_config flag.

The flag is only plumbed through the dmcu firmware, so plumb it through
the driver path as well.

To disable, add the following to the linux cmdline:
amdgpu.dcfeaturemask=0x4

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204957
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Anthony Koo <anthony.koo@amd.com>
Tested-by: Lukáš Krejčí <lskrejci@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:10 -04:00
Nirmoy Das
9f0256da6b drm/amdgpu: remove unused parameter in amdgpu_gfx_kiq_free_ring
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:10 -04:00
James Zhu
8047266443 drm/amdgpu/vcn: Enable VCN2.5 encoding
After VCN2.5 firmware (Version ENC: 1.1  Revision: 11),
VCN2.5 encoding can work properly.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:10 -04:00
Pelloux-prayer, Pierre-eric
3f378758b8 drm/amdgpu/sdma5: do not execute 0-sized IBs (v2)
This seems to help with https://bugs.freedesktop.org/show_bug.cgi?id=111481.

v2: insert a NOP instead of skipping all 0-sized IBs to avoid breaking older hw

Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:10 -04:00
chen gong
5aed95bbdd drm/amdgpu: Fix SDMA hang when performing VKexample test
VKexample test hang during Occlusion/SDMA/Varia runs.
Clear XNACK_WATERMK in reg SDMA0_UTCL1_WATERMK to fix this issue.

Signed-off-by: chen gong <curry.gong@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:10 -04:00
Guchun Chen
52dd95f2b6 drm/amdgpu: define macros for retire page reservation
Easy for maintainance.

Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:10 -04:00
Guchun Chen
c688a06bc6 drm/amdgpu: refine reboot debugfs operation in ras case (v3)
Ras reboot debugfs node allows user one easy control to avoid
gpu recovery hang problem and directly reboot system per card
basis, after ras uncorrectable error happens. However, it is
one common entry, which should get rid of ras_ctrl node and
remove ip dependence when inputting by user. So add one new
auto_reboot node in ras debugfs dir to achieve this.

v2: in commit mssage, add justification why ras reboot debugfs
node is needed.
v3: use debugfs_create_bool to create debugfs file for boolean value

Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:10 -04:00
Philip Yang
2c99a547bc drm/amdkfd: don't use dqm lock during device reset/suspend/resume
If device reset/suspend/resume failed for some reason, dqm lock is
hold forever and this causes deadlock. Below is a kernel backtrace when
application open kfd after suspend/resume failed.

Instead of holding dqm lock in pre_reset and releasing dqm lock in
post_reset, add dqm->sched_running flag which is modified in
dqm->ops.start and dqm->ops.stop. The flag doesn't need lock protection
because write/read are all inside dqm lock.

For HWS case, map_queues_cpsch and unmap_queues_cpsch checks
sched_running flag before sending the updated runlist.

v2: For no-HWS case, when device is stopped, don't call
load/destroy_mqd for eviction, restore and create queue, and avoid
debugfs dump hdqs.

Backtrace of dqm lock deadlock:

[Thu Oct 17 16:43:37 2019] INFO: task rocminfo:3024 blocked for more
than 120 seconds.
[Thu Oct 17 16:43:37 2019]       Not tainted
5.0.0-rc1-kfd-compute-rocm-dkms-no-npi-1131 #1
[Thu Oct 17 16:43:37 2019] "echo 0 >
/proc/sys/kernel/hung_task_timeout_secs" disables this message.
[Thu Oct 17 16:43:37 2019] rocminfo        D    0  3024   2947
0x80000000
[Thu Oct 17 16:43:37 2019] Call Trace:
[Thu Oct 17 16:43:37 2019]  ? __schedule+0x3d9/0x8a0
[Thu Oct 17 16:43:37 2019]  schedule+0x32/0x70
[Thu Oct 17 16:43:37 2019]  schedule_preempt_disabled+0xa/0x10
[Thu Oct 17 16:43:37 2019]  __mutex_lock.isra.9+0x1e3/0x4e0
[Thu Oct 17 16:43:37 2019]  ? __call_srcu+0x264/0x3b0
[Thu Oct 17 16:43:37 2019]  ? process_termination_cpsch+0x24/0x2f0
[amdgpu]
[Thu Oct 17 16:43:37 2019]  process_termination_cpsch+0x24/0x2f0
[amdgpu]
[Thu Oct 17 16:43:37 2019]
kfd_process_dequeue_from_all_devices+0x42/0x60 [amdgpu]
[Thu Oct 17 16:43:37 2019]  kfd_process_notifier_release+0x1be/0x220
[amdgpu]
[Thu Oct 17 16:43:37 2019]  __mmu_notifier_release+0x3e/0xc0
[Thu Oct 17 16:43:37 2019]  exit_mmap+0x160/0x1a0
[Thu Oct 17 16:43:37 2019]  ? __handle_mm_fault+0xba3/0x1200
[Thu Oct 17 16:43:37 2019]  ? exit_robust_list+0x5a/0x110
[Thu Oct 17 16:43:37 2019]  mmput+0x4a/0x120
[Thu Oct 17 16:43:37 2019]  do_exit+0x284/0xb20
[Thu Oct 17 16:43:37 2019]  ? handle_mm_fault+0xfa/0x200
[Thu Oct 17 16:43:37 2019]  do_group_exit+0x3a/0xa0
[Thu Oct 17 16:43:37 2019]  __x64_sys_exit_group+0x14/0x20
[Thu Oct 17 16:43:37 2019]  do_syscall_64+0x4f/0x100
[Thu Oct 17 16:43:37 2019]  entry_SYSCALL_64_after_hwframe+0x44/0xa9

Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:10 -04:00
Zhan liu
80df905da7 drm/amd/display: Change Navi14's DWB flag to 1
[Why]
DWB (Display Writeback) flag needs to be enabled as 1, or system
will throw out a few warnings when creating dcn20 resource pool.
Also, Navi14's dwb setting needs to match Navi10's,
which has already been set to 1.

[How]
Change value of num_dwb from 0 to 1.

Signed-off-by: Zhan Liu <zhan.liu@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:10 -04:00
Roman Li
397a9bc588 drm/amdgpu/display: add dc feature mask for psr enablement
[Why]
Adding psr mask to dc features allows selectively disable/enable psr.
Current psr implementation may not work with non-pageflipping application.
Until resolved it should be disabled by default.

[How]
Add dcfeaturemask for psr enablement. Disable by default.
To enable set amdgpu.dcfeaturemask=0x8 in grub kernel command line.

Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:10 -04:00
Evan Quan
6c45e480fe drm/amd/powerplay: clear the swSMU code layer
With this cleanup, the APIs from amdgpu_smu.c will map to
ASIC specific ones directly. Those can be shared around
all SMU V11/V12 ASICs will be put in smu_v11_0.c and
smu_v12_0.c respectively.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:10 -04:00
Evan Quan
18c1d3cee4 drm/amd/powerplay: split out those internal used swSMU APIs V2
Those swSMU APIs used internally are moved to smu_internal.h while
others are kept in amdgpu_smu.h.

V2: give a better name smu_internal.h for the place to hold
    those internal APIs

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:09 -04:00
Evan Quan
3697b339c6 drm/amd/powerplay: add lock protection for swSMU APIs V2
This is a quick and low risk fix. Those APIs which
are exposed to other IPs or to support sysfs/hwmon
interfaces or DAL will have lock protection. Meanwhile
no lock protection is enforced for swSMU internal used
APIs. Future optimization is needed.

V2: strip the lock protection for all swSMU internal APIs

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Feifei Xu <Feifei.Xu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:09 -04:00
Jane Jian
6aec5bb489 drm/amdgpu: add VCN0 and VCN1 needed headers
Add mmsch part registers

Signed-off-by: Jane Jian <jane.jian@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:09 -04:00
Joshua Aberback
6fcca317cb drm/amd/display: Apply vactive dram clock change workaround to dcn2 DMLv2
[Why]
This workaround was put in dcn2 DMLv1, and now we need it in DMLv2.

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:09 -04:00
Eric Yang
b617b26559 drm/amd/display: fix hubbub deadline programing
[Why]
Fix the programming of DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A.
Was not filled in.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:09 -04:00
Dmytro Laktyushkin
b745ecdb5e drm/amd/display: fix avoid_split for dcn2+ validation
We are currently incorrectly processing avoid split at highest
voltage level.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:09 -04:00
Sung Lee
e72f8f62d2 drm/amd/display: Do not call update bounding box on dc create
[Why]
In Hybrid Graphics, dcn2_1_soc struct stays alive through PnP.
This causes an issue on dc init where dcn2_1_soc which has been
updated by update_bw_bounding_box gets put into dml->soc.
As update_bw_bounding_box is currently incorrect for dcn2.1,
this makes dml calculations fail due to incorrect parameters,
leading to a crash on PnP.

[How]
Comment out update_bw_bounding_box call for now.

Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:09 -04:00
Reza Amini
3b733278ca drm/amd/display: Add center mode for integer scaling in DC
[why]
We want to use maximum space on display to show source

[how]
For Centered Mode: Replicate source as many times as possible to use
maximum of display active space add borders.

Signed-off-by: Reza Amini <Reza.Amini@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:09 -04:00
Lewis Huang
d4c2a96fdb drm/amd/display: take signal type from link
[Why]
Signal is update to EDP when driver disable first encoder. The
following encoder using SIGNAL_TYPE_EDP to handle other
device. When encoder signal is HDMI, driver will detect it is dp
and release phy. It cause hw hang.

[How]
Take signal type from link->connector_signal.

Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:09 -04:00
Aric Cyr
b837d783b6 drm/amd/display: 3.2.56
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:09 -04:00
Noah Abradjian
1ea8751bd2 drm/amd/display: Make clk mgr the only dto update point
[Why]

* Clk Mgr DTO update point did not cover all needed updates, as it included a
  check for plane_state which does not exist yet when the updater is called on
  driver startup
* This resulted in another update path in the pipe programming sequence, based
  on a dppclk update flag
* However, this alternate path allowed for stray DTO updates, some of which would
  occur in the wrong order during dppclk lowering and cause underflow

[How]

* Remove plane_state check and use of plane_res.dpp->inst, getting rid
  of sequence dependencies (this results in extra dto programming for unused
  pipes but that doesn't cause issues and is a small cost)
* Allow DTOs to be updated even if global clock is equal, to account for
  edge case exposed by diags tests
* Remove update_dpp_dto call in pipe programming sequence (leave update to
  dppclk_control there, as that update is necessary and shouldn't occur in clk
  mgr)
* Remove call to optimize_bandwidth when committing state, as it is not needed
  and resulted in sporadic underflows even with other fixes in place

Signed-off-by: Noah Abradjian <noah.abradjian@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:09 -04:00
Krunoslav Kovac
50575eb5b3 drm/amd/display: Only use EETF when maxCL > max display
[Why&How]
BT.2390 EETF is used for tone mapping/range reduction.
Say display is 0.1 - 500 nits.
The problematic case is when content is 0-400. We apply EETF because
0<0.1 so we need to reduce the range by 0.1.

In the commit, we ignore the bottom range. Most displays map 0 to min and
then have a ramp to 0.1, so sending 0.1 is actually >0.1.
Furthermode, HW that uses 3D LUT also assumes min=0.

Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:09 -04:00
Eric Yang
622a88c825 drm/amd/display: move wm ranges reporting to end of init hw
[Why]
SMU does not keep the wm table across S3, S4, need to re-send
the table. Also defer sending the cable to after DCN bave initialized

[How]
Send table at end of init hw

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:09 -04:00
Jun Lei
0460f9abf2 drm/amd/display: do not synchronize "drr" displays
[why]
A display that supports DRR can never really be considered
"synchronized" with any other display because we can dynamically
enable DRR (i.e. without modeset).  this will cause their
relative CRTC positions to drift and lose sync.  this will disrupt
features such as MCLK switching that assume and depend on
their permanent alignment (that can only change with modeset)

[how]
check for ignore_msa in stream when considered synchronizability
this ignore_msa is basically actually implemented as "supports drr"

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:09 -04:00
Anthony Koo
e9c93e5af3 drm/amd/display: Proper return of result when aux engine acquire fails
[Why]
When aux engine acquire fails, we missed populating the operation_result
that describes the failure reason.

[How]
Set operation_result to new type:
AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE
in the case aux engine acquire has failed.

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:09 -04:00
Michael Strauss
4d25a0d510 drm/amd/display: Disable force_single_disp_pipe_split on DCN2+
[WHY]
force_single_disp_pipe_split is a debug flag for use on DCN1
but isn't necessary otherwise as DCN2+ splits by default

Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:09 -04:00
Michael Strauss
71fb7b2801 drm/amd/display: Passive DP->HDMI dongle detection fix
[WHY]
i2c_read is called to differentiate passive DP->HDMI and DP->DVI-D dongles
The call is expected to fail in DVI-D case but pass in HDMI case
Some HDMI dongles have a chance to fail as well, causing misdetection as DVI-D

[HOW]
Retry i2c_read to ensure failed result is valid

Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:09 -04:00
Yogesh Mohan Marimuthu
bf7f5ac316 drm/amd/display: map TRANSMITTER_UNIPHY_x to LINK_REGS_x
[Why]
The enum value for TRANSMITTER_UNIPHY_G is 9. In resource dc_xx_resource
file structure link_enc_regs[], the TRANSMITTER_UNIPHY_G registers are
initialized at index 6. Due to this mismatch, if monitor is attached to
port using TRANSMITTER_UNIPHY_G then the monitor blanks out.

[How]
add function map_transmitter_id_to_phy_instance() and use the function
to map enum transmitter to link regs.

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:09 -04:00
Jun Lei
22631bb8ca drm/amd/display: add flag to allow diag to force enumerate edp
[why]
SLT tests require that diag can drive eDP even if nothing is connected, this is not
typical production use case, so we need to add flag

[how]
add flag, and this flag supercedes "should destroy" logic

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:08 -04:00
Dmytro Laktyushkin
d5ac4ff211 drm/amd/display: add embedded flag to dml
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:08 -04:00
Dmytro Laktyushkin
5cb4ca07c2 drm/amd/display: fix number of dcn21 dpm clock levels
These are specific to dcn21 and should not be increased for
reuse on other asics.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:08 -04:00
Yongqiang Sun
8c35730993 drm/amd/display: enable vm by default for rn.
[Why & How]
vm should be enabled by default for rn to get
right dml.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25 16:50:08 -04:00