Commit Graph

93 Commits

Author SHA1 Message Date
Harry Wentland
20e9b0718b drm/amd: Add missing SURFACE_TMZ register shift/mask
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26 18:15:20 -04:00
Harry Wentland
ee87a45e95 drm/amd/include: Add DCHUBBUB_TEST_DEBUG register defines
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26 18:15:19 -04:00
Harry Wentland
d8bad05a62 drm/amd/include: Add DC_PINSTRAPS.AUDIO defines
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26 18:15:18 -04:00
Rex Zhu
9f4b35411c drm/amd/powerplay: add CI asics support to smumgr (v3)
This ports support for CI asics (Bonaire, Hawaii)
to the powerplay smumgr

v2: warning fix (Alex)
v3: squash in fix for thermal (Tom)

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26 13:06:57 -04:00
Alex Deucher
702f9292ad drm/amdgpu: add register headers for VCN 1.0
Add registers for Video Controller Next 1.0

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-24 17:40:48 -04:00
Alex Deucher
bfd86c1ab3 drm/amdgpu: add register headers for THM 10.0
Add registers for THerMal control 10.0

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-24 17:40:47 -04:00
Alex Deucher
ce869c637e drm/amdgpu: add register headers for SDMA 4.1
Add registers for SDMA 4.1

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-24 17:40:46 -04:00
Alex Deucher
c4dc7b1a54 drm/amdgpu: add register headers for NBIO 7.0
Add registers for NBIO 7.0

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-24 17:40:45 -04:00
Alex Deucher
cfeb9192fe drm/amdgpu: add register headers for MP 10.0
Add registers for MP 10.0

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-24 17:40:44 -04:00
Alex Deucher
96ded7747c drm/amdgpu: add register headers for MMHUB 9.1
Add registers for the MultiMedia Hub 9.1

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-24 17:40:44 -04:00
Alex Deucher
7582d7e649 drm/amdgpu: add register headers for GC 9.1
Registers for Graphics Controller 9.1

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-24 17:40:43 -04:00
Alex Deucher
752ca077d5 drm/amdgpu: add register headers for DCN 1.0
Registers for Display Controller Next 1.0

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-24 17:40:42 -04:00
Xiaojie Yuan
4caca70668 drm/amdgpu: add DP audio support for si dce6 (v3)
v2: refine dce_v6_0_audio_endpt_wreg() and unify inconsistent method names
v3: fix num_pins for tahiti, pitcairn, verde and oland

Signed-off-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Junwei Zhang <Jerry.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-24 17:39:58 -04:00
Alex Deucher
f6c3947893 drm/amdgpu: add the VCE 4.0 register headers
These are the Video Compression Engine registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:28 -04:00
Alex Deucher
7008d577d6 drm/amdgpu: add the UVD 7.0 register headers
These are the Unifed Video Decoder registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:28 -04:00
Alex Deucher
893f25540e drm/amdgpu: add THM 9.0 register headers
These are the THerMal control registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:27 -04:00
Alex Deucher
63d311d9b4 drm/amdgpu: add SMUIO 9.0 register headers
These are the System Managment Unit IO registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:26 -04:00
Alex Deucher
456f97704f drm/amdgpu: add SDMA 4.0 register headers
These are the System DMA register headers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:26 -04:00
Alex Deucher
5a8288c0f9 drm/amdgpu: add OSSSYS 4.0 register headers
These are the OS Services register headers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:25 -04:00
Alex Deucher
198b746016 drm/amdgpu: add NBIO 6.1 register headers
These are the Bus IO registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:24 -04:00
Alex Deucher
61e04478b2 drm/amdgpu: add NBIF 6.1 register headers
These are the Bus InterFace registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:23 -04:00
Alex Deucher
3ec127a075 drm/amdgpu: add MP 9.0 register headers
MP is the system management controller on vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:23 -04:00
Alex Deucher
68c7d13052 drm/amdgpu: add the MMHUB 1.0 register headers
Add the MultiMedia Hub registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:22 -04:00
Alex Deucher
bcfb47cdd7 drm/amdgpu: add the HDP 4.0 register headers
These are the Host Data Path registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:21 -04:00
Alex Deucher
5585476e44 drm/amdgpu: add the GC 9.0 register headers
Add the Graphics Core register headers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:21 -04:00
Alex Deucher
4adc5ab813 drm/amdgpu: Add the DCE 12.0 register headers
These are the register headers for the Display
and Composition Engine on vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:20 -04:00
Alex Deucher
7fee1fd93b drm/amdgpu: Add ATHUB 1.0 register headers
ATHUB is part of the memory controller on soc15 asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:19 -04:00
Alex Deucher
733acf561e drm/amdgpu: add vega10_enum.h
This adds the register bitfield enums for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:19 -04:00
Alex Deucher
1fd1cc5640 drm/amdgpu: add soc15ip.h
This header defines the IP layout for soc15 based SoCs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:18 -04:00
Rex Zhu
1c622002b1 drm/amd/powerplay: add a new register define for APU in VI.
the ixcurrent_pg_status addr is different between APU and DGPU.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:06 -04:00
Christian König
f7c35abe93 drm/amdgpu: implement PRT for GFX6 v2
Enable/disable the handling globally for now and
print a warning when we enable it for the first time.

v2: write to the correct register, adjust bits to that hw generation
v3: fix compilation, add the missing register bit definitions

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:52:57 -04:00
Rex Zhu
254cd2e08d drm/amdgpu: read hw register to check pg status.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-02-13 12:43:04 -05:00
Rex Zhu
cbd9262f80 drm/amdgpu: add current_pg_status register define for smu7.1
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-02-08 17:20:22 -05:00
Alex Deucher
689957b12b drm/amdgpu: move misc si headers into amdgpu
Move these to the amdgpu directory to match what we
do for other asics.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 12:20:41 -05:00
Alex Deucher
d848c0ba66 drm/amdgpu: remove unused header si_reg.h
All of these are available elsewhere.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 12:20:40 -05:00
Harry Wentland
33503e9e5a drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines
This is required for DP HBR2 test pattern

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:44 -05:00
Harry Wentland
8c27f5c1fd drm/amd/amdgpu: Add HDMI_DATA_SCRAMBLE register definition
This is required by HDMI 2.0

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27 11:12:43 -05:00
Linus Torvalds
9439b3710d Main pull request for drm for 4.10 kernel
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Merge tag 'drm-for-v4.10' of git://people.freedesktop.org/~airlied/linux

Pull drm updates from Dave Airlie:
 "This is the main pull request for drm for 4.10 kernel.

  New drivers:
   - ZTE VOU display driver (zxdrm)
   - Amlogic Meson Graphic Controller GXBB/GXL/GXM SoCs (meson)
   - MXSFB support (mxsfb)

  Core:
   - Format handling has been reworked
   - Better atomic state debugging
   - drm_mm leak debugging
   - Atomic explicit fencing support
   - fbdev helper ops
   - Documentation updates
   - MST fbcon fixes

  Bridge:
   - Silicon Image SiI8620 driver

  Panel:
   - Add support for new simple panels

  i915:
   - GVT Device model
   - Better HDMI2.0 support on skylake
   - More watermark fixes
   - GPU idling rework for suspend/resume
   - DP Audio workarounds
   - Scheduler prep-work
   - Opregion CADL handling
   - GPU scheduler and priority boosting

  amdgfx/radeon:
   - Support for virtual devices
   - New VM manager for non-contig VRAM buffers
   - UVD powergating
   - SI register header cleanup
   - Cursor fixes
   - Powermanagement fixes

  nouveau:
   - Powermangement reworks for better voltage/clock changes
   - Atomic modesetting support
   - Displayport Multistream (MST) support.
   - GP102/104 hang and cursor fixes
   - GP106 support

  hisilicon:
   - hibmc support (BMC chip for aarch64 servers)

  armada:
   - add tracing support for overlay change
   - refactor plane support
   - de-midlayer the driver

  omapdrm:
   - Timing code cleanups

  rcar-du:
   - R8A7792/R8A7796 support
   - Misc fixes.

  sunxi:
   - A31 SoC display engine support

  imx-drm:
   - YUV format support
   - Cleanup plane atomic update

  mali-dp:
   - Misc fixes

  dw-hdmi:
   - Add support for HDMI i2c master controller

  tegra:
   - IOMMU support fixes
   - Error handling fixes

  tda998x:
   - Fix connector registration
   - Improved robustness
   - Fix infoframe/audio compliance

  virtio:
   - fix busid issues
   - allocate more vbufs

  qxl:
   - misc fixes and cleanups.

  vc4:
   - Fragment shader threading
   - ETC1 support
   - VEC (tv-out) support

  msm:
   - A5XX GPU support
   - Lots of atomic changes

  tilcdc:
   - Misc fixes and cleanups.

  etnaviv:
   - Fix dma-buf export path
   - DRAW_INSTANCED support
   - fix driver on i.MX6SX

  exynos:
   - HDMI refactoring

  fsl-dcu:
   - fbdev changes"

* tag 'drm-for-v4.10' of git://people.freedesktop.org/~airlied/linux: (1343 commits)
  drm/nouveau/kms/nv50: fix atomic regression on original G80
  drm/nouveau/bl: Do not register interface if Apple GMUX detected
  drm/nouveau/bl: Assign different names to interfaces
  drm/nouveau/bios/dp: fix handling of LevelEntryTableIndex on DP table 4.2
  drm/nouveau/ltc: protect clearing of comptags with mutex
  drm/nouveau/gr/gf100-: handle GPC/TPC/MPC trap
  drm/nouveau/core: recognise GP106 chipset
  drm/nouveau/ttm: wait for bo fence to signal before unmapping vmas
  drm/nouveau/gr/gf100-: FECS intr handling is not relevant on proprietary ucode
  drm/nouveau/gr/gf100-: properly ack all FECS error interrupts
  drm/nouveau/fifo/gf100-: recover from host mmu faults
  drm: Add fake controlD* symlinks for backwards compat
  drm/vc4: Don't use drm_put_dev
  drm/vc4: Document VEC DT binding
  drm/vc4: Add support for the VEC (Video Encoder) IP
  drm: Add TV connector states to drm_connector_state
  drm: Turn DRM_MODE_SUBCONNECTOR_xx definitions into an enum
  drm/vc4: Fix ->clock_select setting for the VEC encoder
  drm/amdgpu/dce6: Set MASTER_UPDATE_MODE to 0 in resume_mc_access as well
  drm/amdgpu: use pin rather than pin_restricted in a few cases
  ...
2016-12-13 09:35:09 -08:00
Joe Perches
fe6bce8d30 treewide: Make remaining source files non-executable
.c and .h source files should not be executable, change
the permissions to 0644.

[ This would normally go through Andrew Morton, but his ancient
  patch-based toolchain doesn't do permission changes ]

Signed-off-by: Joe Perches <joe@perches.com>
Acked-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-12-12 20:41:52 -08:00
Tom St Denis
b00861b98b drm/amd/amdgpu: port of DCE v6 to new headers (v3)
Port of SI DCE v6 over to new AMDGPU headers.  Tested on a
Tahiti with GNOME through various hot plugs/rotations/sizes/fullscreen/windowed and
staging drm/xf86-video-amdgpu.

(v2) Re-factored to remove formatting changes to si_enums.h
     as well rename various defines.
(v3) Rebase on upstream

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-23 15:08:42 -05:00
Tom St Denis
5e2e211995 drm/amd/amdgpu: add SI defines/registers
Add missing gca MMIO registers and defines necessary for the
next patch which re-works a lot of gfx v6 to use the new SI
headers.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-11 10:21:08 -05:00
Tom St Denis
de2bdb3dcf drm/amd/amdgpu: Introduction of SI registers (v2)
This introduces the SI registers in the amdgpu
driver style.

v2: squash duplicates fix

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-11 10:21:07 -05:00
Monk Liu
4bc10d168a drm/amdgpu:use smc_index_11 for VI
for VI smc, index_0 to index_8 are all not safe,
they may used by BIOS/FW, and index_11 is reserved
only for driver.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25 14:38:20 -04:00
Huang Rui
865ab832ba drm/amdgpu: implement raster configuration for gfx v6
This patch is to implement the raster configuration and harvested
configuration of gfx v6.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-09-19 14:38:24 -04:00
Ken Wang
62a3755341 drm/amdgpu: add si implementation v10
v5: rebase fixes
v6: add mgcg arrays
v7: rebase fixes
v8: rebase fixes
v9: add get_disabled_bios(), make get_xclk static
v10: fix oland and hainan asic specific handle at si_program_aspm

Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-08-31 12:11:19 -04:00
Ken Wang
30d1574fa4 drm/amdgpu: add DMA implementation for si v8
v4: rebase fixes
v5: use the generic nop fill
v6: rebase fixes
v7: rebase fixes
    copy count fixes from Jonathan
    general cleanup
    add fill buffer implementation
v8: adapt write_pte and copy_pte to latest changes

Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-08-31 12:10:51 -04:00
Ken Wang
e2cdf640cb drm/amdgpu: add display controller implementation for si v10
v4: rebase fixups
v5: more fixes based on dce8 code
v6: squash in dmif offset fix
v7: rebase fixups
v8: rebase fixups, drop some debugging remnants
v9: fix BE build
v10: include Marek's tiling fixes, add support for
     page_flip_target, set MASTER_UDPATE_MODE=0,
     fix cursor

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-08-31 12:10:19 -04:00
Ken Wang
0f27e46258 drm/amdgpu: add si header files v4
v4: drop unused DCE6 macro

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-08-31 12:09:08 -04:00
Alex Deucher
c8b4f288f4 drm/amdgpu: switch UVD code to use UVD_NO_OP for padding
Replace packet2's with packet0 writes to UVD_NO_OP.  The
value written to UVD_NO_OP does not matter.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-08-24 16:25:05 -04:00
Alex Deucher
8dd31d74ac drm/amdgpu: add support for UVD_NO_OP register
Writes to this register are the preferred way to do NOPs.

Bump the driver version as well.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-08-24 16:25:04 -04:00