Commit Graph

810464 Commits

Author SHA1 Message Date
Evan Quan
7ca881a865 drm/amd/powerplay: support enabled ppfeatures retrieving and setting V3
User can use "ppfeatures" sysfs interface to retrieve and set enabled
powerplay features.

V2: expose this feature for Vega10 and later dGPUs
V3: squash in removal of unused variable (Alex)

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25 16:15:34 -05:00
Chunming Zhou
b61857b5e3 drm/amdgpu: set bulk_moveable to false when lru changed v2
if lru is changed, we cannot do bulk moving.
v2:
root bo isn't in bulk moving, skip its change.

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25 16:15:34 -05:00
Chunming Zhou
ae6d343541 drm/ttm: add lru notify to bo driver v2
allow driver do somethings when lru changed.
v2:
address Michel's comments.

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25 16:15:34 -05:00
Aaron Liu
466bcb75b0 drm/amdgpu/psp: ignore psp response status
In some cases, psp response status is not 0 even there is no
problem while the command is submitted. Some version of PSP FW
doesn't write 0 to that field.
So here we would like to only print a warning instead of an error
during psp initialization to avoid breaking hw_init and it doesn't
return -EINVAL.

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Xiangliang Yu<Xiangliang.Yu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Paul Menzel <pmenzel+amd-gfx@molgen.mpg.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25 16:15:34 -05:00
Oak Zeng
7c94bc828e drm/amdgpu: Setting doorbell range registers earlier
HW doorbell writing routing policy: writing to doorbell
not in SDMA/IH/MM/ACV doorbell range will be routed to CP.
So CP doorbell routing depends on doorbell range setting
of above blocks. Setting doorbell range of above blocks
earlier (soc15_common_hw_init) to make sure CP doorbell
writing be routed to CP block.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25 16:15:34 -05:00
Oak Zeng
8987e2e256 drm/amdgpu: Fix sdma doorbell range setting
Different ASIC has different SDMA queue number so
different SDMA doorbell range. Introduce an extra
parameter to sdma_doorbell_range function and set
sdma doorbell range correctly.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25 16:15:34 -05:00
Oak Zeng
fd4855409f drm/amdgpu: Add per device sdma_doorbell_range field
Different ASIC has different sdma doorbell range. Add
a per device sdma_doorbell_range field and initialize
it.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25 16:15:34 -05:00
Alex Deucher
1f46df61a1 drm/amdgpu/soc15: return proper error codes in baco reset
Rather than just -1.

Reviewed-by: JimQu <Jim.Qu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25 16:15:34 -05:00
Rafał Miłecki
0982a8fc2a drm/amd/display: Include names of all PP clock types
This fixes printing clock names in cases like:
[    5.352311] [drm] DM_PPLIB: values for Invalid clock
[    5.352313] [drm] DM_PPLIB:   400000 in kHz
[    5.352313] [drm] DM_PPLIB:   933000 in kHz
[    5.352314] [drm] DM_PPLIB:   1067000 in kHz
[    5.352315] [drm] DM_PPLIB:   1200000 in kHz
[    5.352317] [drm] DM_PPLIB: values for Invalid clock
[    5.352318] [drm] DM_PPLIB:   300000 in kHz
[    5.352318] [drm] DM_PPLIB:   600000 in kHz
[    5.352319] [drm] DM_PPLIB:   626000 in kHz
[    5.352320] [drm] DM_PPLIB:   654000 in kHz
(source: HP EliteBook 745 G5 w. RAVEN 0x1002:0x15DD 0x103C:0x83D5 0xD1)

On my system above "Invalid" names got replaced by "F" and "DCF".

The same problem was occurring on Huawei Matebook D with just 667000 kHz
instead of 400000 kHz.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25 16:15:34 -05:00
Matteo Croce
229f7b1d63 drm/amd: fix typo
Fix spelling mistake: "lenght" -> "length"

Signed-off-by: Matteo Croce <mcroce@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25 16:15:34 -05:00
Jerry (Fangzhi) Zuo
02d35a67f4 drm/amd/display: Skip create new stream if crtc state doesn't change
Need to check if crtc state is changed so that mode set is
required before trying to create new stream.

It deals with the MST hotplug use case when plug back to the
same connector where the failure to create new stream for the
inactive crtc on the old connector.

Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25 16:15:34 -05:00
Jim Qu
2172b89e7c drm/amdgpu: use BACO reset on vega20 if platform support
Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25 16:15:34 -05:00
Jim Qu
e2b6d053b1 drm/amdgpu: use BACO reset if platform support (v2)
It will fall back to use mode1 reset if platform does not support BACO
feature.

v2: squash in warning fix (Alex)

Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25 16:15:33 -05:00
Jim Qu
3177b3c52f drm/amdgpu/powerper: add vega20 BACO functions
Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25 16:15:33 -05:00
Jim Qu
6a789aa8d5 drm/amdgpu: update THM IP register header to support BACO
Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25 16:15:33 -05:00
Jim Qu
d1882ab2c2 drm/amdgpu: also include NBIO v7.4 register mask header
Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25 16:15:33 -05:00
Jim Qu
f5d9e9b9c1 drm/amdgpu: update NBIO v7.4 to support BACO
Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25 16:15:33 -05:00
Jim Qu
425db2553e drm/amdgpu: expose BACO interfaces to upper level from PP
Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25 16:15:33 -05:00
Jim Qu
2affc6234f drm/amdgpu: add BACO interfaces for vega10
V2: delay 20ms before BACO out.
V3: rename function to vega10_baco_xxx

Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25 16:15:33 -05:00
Jim Qu
36eac4dd1f drm/amdpgu: add common functions for BACO feature in PP (v2)
V2: squash in crash fix for non-register commands (Alex)

Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25 16:15:33 -05:00
Jim Qu
7451ca88d5 drm/amdgpu: add BACO interfaces in pm and hwmgr function table
Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:43:01 -05:00
Jim Qu
58a50420aa drm/amdgpu: update nbio v6.1 register/master to support BACO
Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:42:51 -05:00
Leo Li
9c7c0ae754 drm/amd/display: Fully remove i2caux folder
This is a follow up to:
e28e1490794d ("drm/amd/display: Remove i2caux folder")

Some files were still left, so delete all of them.

CC: David Francis <David.Francis@amd.com>
CC: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:42:43 -05:00
Steven Chiu
45a31b01b5 drm/amd/display: 3.2.14
Signed-off-by: Steven Chiu <steven.chiu@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:42:37 -05:00
Krunoslav Kovac
ccab121723 drm/amd/display: Check for NULL when creating gamma struct
[Wjy&How] Some stress test is causing unexpected memory allocation
failure. This prevents null dereference but there will likely be problems
later, hard to gracefully handle memalloc fail for critical objects.

Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Reza Amini <Reza.Amini@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:42:30 -05:00
Eric Bernstein
5dc3fc5a78 drm/amd/display: Check if registers are available before accessing
Check if VERT_FILTER_INIT_BOT and BLACK_OFFSET registers
exists in the DCN SCL IP block before trying to access.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:42:22 -05:00
Bayan Zabihiyan
ca35899c4e drm/amd/display: Add new infopacket definition
Modify freesync module to build VTEM infopackets when in HdmiVRR mode

Signed-off-by: Bayan Zabihiyan <Bayan.Zabihiyan@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:42:12 -05:00
Dmytro Laktyushkin
2ee7c03cf1 drm/amd/display: Rename configure_encoder to enc1_configure_encoder
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:42:04 -05:00
Eric Yang
0f0c192433 drm/amd/display: add workaround for 4k video underflow
[Why]
On DCN1, there is an issue where on high BW config on single channel
systems, underflow will be observed if DCC is disabled. This issue
can be observed on several use cases. For this particular case,
it is observed when playing 4k video on 4k desktop with video downscaled
to a certain size.

[How]
Block MPO for this particular case, this will prevent extra BW consumed
from downscaling, working around the underflow.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:41:47 -05:00
Charlene Liu
9983b80053 drm/amd/display: dp interlace MSA timing programming for Interlace mode.
[Why]
DP compliance box shows wrong MSA data.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:41:39 -05:00
Roman Li
570744b98c drm/amd/display: fix warning on raven hotplug
[Why]
Hotplug on raven results in REG_WAIT_TIMEOUT warning
due to failing attempt to lock disabled otg for the hubp
interdependent pipes programming.

[How]
Don't setup pipe interdependencies for disabled otg.
Also removed the unnecessary duplicate logic checks.

Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:41:09 -05:00
hersen wu
588715bdcf drm/amd/display: dal-pplib interface refactor dal part
[WHY] clarify dal input parameters to pplib interface, remove
un-used parameters. dal knows exactly which parameters needed
and their effects at pplib and smu sides.

current dal sequence for dcn1_update_clock to pplib:

1.smu10_display_clock_voltage_request for dcefclk
2.smu10_display_clock_voltage_request for fclk
3.phm_store_dal_configuration_data {
   set_min_deep_sleep_dcfclk
   set_active_display_count
   store_cc6_data --- this data never be referenced

new sequence will be:

1. set_display_count  --- need add new pplib interface
2. set_min_deep_sleep_dcfclk -- new pplib interface
3. set_hard_min_dcfclk_by_freq
4. set_hard_min_fclk_by_freq

after this code refactor, smu10_display_clock_voltage_request,
phm_store_dal_configuration_data will not be needed for rv.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:41:01 -05:00
David Francis
077d0b6ba2 drm/amd/display: Remove i2caux folder
[Why]
It is huge, unmaintainable, needlessly layered, and obsolete

[How]
Remove it.  All of it.  Also remove the i2caux struct in
dc_context and the code that created and destructed it

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:40:54 -05:00
David Francis
1877ccf6ee drm/amd/display: Change from aux_engine to dce_aux
[Why]
The aux_engine struct is needlessly complex and
is defined multiple times.  It contains function pointers
that each have only one version and are called only from
inside dce_aux.

[How]
Replace aux_engine with a new struct called dce_aux.
Remove all function pointers and call functions directly.
Remove unused functions

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:40:48 -05:00
David Francis
eae5ffa9bd drm/amd/display: Switch ddc to new aux interface
[Why]
The old aux interface goes through i2caux and the aux_engine
and engine function pointers.  The multiple layers of indirection
make it hard to tell waht is happening.  The aux algorithm
does not need to be this complicated: attempt to submit the
request.  If you get an ack (reply = 0), stop.  Otherwise,
retry, up to 7 times.

[How]
Add a new helper function in dce_aux that performs aux retries

Move the plumbing of the aux calling code into dce_aux

Add functions in ddc that redirect directly to dce_aux

Make all aux calls use these functions

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:40:40 -05:00
David Francis
ad6756b4d7 drm/amd/display: Shift dc link aux to aux_payload
[Why]
aux_payload should be the struct used inside dc to start
aux transactions.  This will allow the old aux interface
to be seamlessly replaced.

[How]
Add three fields to aux_payload: reply, mot, defer_delay
This will mean that aux_payload has all data required
to submit a request.  Shift dc_link to use this struct

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:40:33 -05:00
Steven Chiu
bbba983103 drm/amd/display: 3.2.13
Signed-off-by: Steven Chiu <steven.chiu@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:40:27 -05:00
Nicholas Kazlauskas
55a806d37f drm/amd/display: Fix disabled cursor on top screen edge
[Why]
The cursor vanishes when touching the top of edge of the screen for
Raven on Linux.

This occurs because the cursor height is not taken into account when
deciding to disable the cursor.

[How]
Factor in the cursor height into the cursor calculations - and mimic
the existing x position calculations.

Fixes: 94a4ffd1d4 ("drm/amd/display: fix PIP bugs on Dal3")

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:40:18 -05:00
Derek Lai
b03a599b3e drm/amd/display: Set link rate set if eDP ver >= 1.4.
[Why]
If eDP ver >= 1.4,
the Source device must use LINK_RATE_SET.

[How]
Get LINK_RATE_SET by reading DPCD 10h-1fh,
then write DPCD 00115h before link training.

Signed-off-by: Derek Lai <Derek.Lai@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:40:08 -05:00
Joshua Aberback
7eb9097541 drm/amd/display: Fix for NULL ramp pointer crashing driver
[Why]
In certain scenarios the ramp parameter come in as NULL, which crashes
because this function doesn't guard properly in the early return.

[How]
- parameter mapUserRamp should be the guard (false means no ramp)
- remove checking ramp in early return

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Sivapiriyan Kumarasamy <Sivapiriyan.Kumarasamy@amd.com>
Acked-by: Eryk Brol <Eryk.Brol@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:40:00 -05:00
Martin Tsai
ffb6c1c6c5 drm/amd/display: Redefine DMCU_SCRATCH to identify DMCU state
[why]
To resume system before entering S0i3 completely will cause PSP not
reload DMCU FW since there is not HW power state change.
In this case, driver cannot get correct DMCU version from IRAM
since driver override it and DMCU didn't reload to update it.
It makes driver return false in dcn10_dmcu_init().

[how]
1.To redefine DMCU_SCRATCH to identify different DMCU state.
2.To reserve IRAM 0xF0~0xFF write by DMCU only.
3.To remove dcn10_get_dmcu_state

Signed-off-by: Martin Tsai <martin.tsai@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:39:22 -05:00
Charlene Liu
070fe7246f drm/amd/display: fix PME notification not working in RV desktop
[Why]
PPLIB not receive the PME when unplug.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:38:47 -05:00
Tony Cheng
44788bbc30 drm/amd/display: refactor reg_update
[why]
separate register access from logic to allow us abstract register sequences

[how]
consolidate mask and value first then apply to register.

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:38:40 -05:00
Leo Li
29c8f23425 Revert "drm/amd/display: Signal hw_done() after waiting for flip_done()"
This reverts commit 717276b925.

The reverted patch was a workaround that addressed an issue fixed by:
4364bcb2cd ("drm: Get ref on CRTC commit object when waiting for
flip_done")

Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:38:31 -05:00
abdoulaye berthe
a6729a5a40 drm/amd/display: fix CTS 4.2.2.8
[Why]
1-Test equipment does not reset test automation flag after completing
current test causing the next test to fail.
2.When test request is empty, we shouldn't ack the test.

[How]
1-Driver should always clear test equipment automation test request
when request is completed.
2-Driver should clear test equipement test automation if driver does
not complete the request.

Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:38:24 -05:00
Josip Pavic
c591d8429d drm/amd/display: Pack DMCU iRAM alignment
[Why]
When the DMCU's iRAM definition was moved to the newly created
power_helpers, a #pragma pack was lost, causing the iRAM to be misaligned

[How]
Restore the #pragma pack

Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:38:16 -05:00
Joshua Aberback
4bd0dc68fd drm/amd/display: Fix missing hwss function for dce
[Why]
The driver will crash on dce hardware due to a null function pointer.

[How]
- bring back "program_csc_matrix" functionality as "program_output_csc" for
dce110
- dce110 doesn't use the "opp_id" parameter, so use 0 when there's no hubp

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:38:08 -05:00
Steven Chiu
887c549dc0 drm/amd/display: 3.2.12
Signed-off-by: Steven Chiu <steven.chiu@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:38:01 -05:00
Nicholas Kazlauskas
a93587b31e drm/amd/display: Only get the connector state for VRR when toggled
[Why]
This fixes a stuttering issue that occurs when moving a hardware cursor
when VRR is enabled.

Previously when VRR is enabled atomic check will grab the connector
state for every atomic update. This has to lock the connector in order
to do so. The locking is bad enough by itself for performance, but
it gets worse with what we do just below that - add all the planes
for the CRTC to the commit.

This prevents the cursor fast path from working - there's more than one
plane now. With state->allow_modeset = true on top of this, it also
adds and removes all the planes from the DC context triggering a full
(very slow) update in DC.

[How]
We need the connector state to get the VRR min/max capbilities, but we
only need them when there's a CRTC mode change or when VRR is toggled.

The condition has been updated accordingly.

Fixes: 3cc22f281318 ("drm/amdgpu: Set FreeSync state using drm VRR properties")

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:37:51 -05:00
Kenneth Feng
b721056b34 drm/amd/powerplay: run acg btc for Vega12
acg btc was added to Vega12

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:37:43 -05:00