Commit Graph

4668 Commits

Author SHA1 Message Date
Pankaj Dubey
51a2de5517 arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7
Usage of DTS macros instead of hard-coded numbers makes code easier to
read.  One does not have to remember which value means pull-up/down or
specific driver strength.

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-02-02 19:08:37 +02:00
Linus Torvalds
e387dc122f Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
Pull crypto fixes from Herbert Xu:
 "This fixes a bug in CBC/CTR on ARM64 that breaks chaining as well as a
  bug in the core API that causes registration failures when a driver
  unloads and then reloads an algorithm"

* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6:
  crypto: arm64/aes-blk - honour iv_out requirement in CBC and CTR modes
  crypto: api - Clear CRYPTO_ALG_DEAD bit before registering an alg
2017-02-01 09:24:00 -08:00
Christopher Covington
d9ff80f83e arm64: Work around Falkor erratum 1009
During a TLB invalidate sequence targeting the inner shareable domain,
Falkor may prematurely complete the DSB before all loads and stores using
the old translation are observed. Instruction fetches are not subject to
the conditions of this erratum. If the original code sequence includes
multiple TLB invalidate instructions followed by a single DSB, onle one of
the TLB instructions needs to be repeated to work around this erratum.
While the erratum only applies to cases in which the TLBI specifies the
inner-shareable domain (*IS form of TLBI) and the DSB is ISH form or
stronger (OSH, SYS), this changes applies the workaround overabundantly--
to local TLBI, DSB NSH sequences as well--for simplicity.

Based on work by Shanker Donthineni <shankerd@codeaurora.org>

Signed-off-by: Christopher Covington <cov@codeaurora.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-02-01 15:41:50 +00:00
Frederic Weisbecker
b672592f02 sched/cputime: Remove generic asm headers
cputime_t is now only used by two architectures:

	* powerpc (when CONFIG_VIRT_CPU_ACCOUNTING_NATIVE=y)
	* s390

And since the core doesn't use it anymore, we don't need any arch support
from the others. So we can remove their stub implementations.

A final cleanup would be to provide an efficient pure arch
implementation of cputime_to_nsec() for s390 and powerpc and finally
remove include/linux/cputime.h .

Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rik van Riel <riel@redhat.com>
Cc: Stanislaw Gruszka <sgruszka@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Wanpeng Li <wanpeng.li@hotmail.com>
Link: http://lkml.kernel.org/r/1485832191-26889-36-git-send-email-fweisbec@gmail.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-02-01 09:14:07 +01:00
Ivan T. Ivanov
7c10da3736 arm64: dts: qcom: Add msm8916 CoreSight components
Add initial set of CoreSight components found on Qualcomm msm8916 and
apq8016 based platforms, including the DragonBoard 410c board.

Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-01-31 17:23:17 -06:00
Marek Szyprowski
d1160ebff1 arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e
Add initial clock configuration for display subsystem for Exynos5433
based TM2/TM2e boards in device tree in order to avoid dependency on the
configuration left by the bootloader. This initial configuration is also
needed to ensure that display subsystem is operational if display power
domain gets turned off before clock controller is probed and the inital
clock configuration left by the bootloader saved.

TM2 and TM2e uses different rate for DISP PLL clock, but for better
maintainability all 'assigned-clocks-*' properties for DISP CMU are
defines in each board dts instead of redefining the rates property.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-01-31 21:37:51 +02:00
Catalin Marinas
ec663d967b arm64: Improve detection of user/non-user mappings in set_pte(_at)
Commit cab15ce604 ("arm64: Introduce execute-only page access
permissions") allowed a valid user PTE to have the PTE_USER bit clear.
As a consequence, the pte_valid_not_user() macro in set_pte() was
replaced with pte_valid_global() under the assumption that only user
pages have the nG bit set. EFI mappings, however, also have the nG bit
set and set_pte() wrongly ignores issuing the DSB+ISB.

This patch reinstates the pte_valid_not_user() macro and adds the
PTE_UXN bit check since all kernel mappings have this bit set. For
clarity, pte_exec() is renamed to pte_user_exec() as it only checks for
the absence of PTE_UXN. Consequently, the user executable check in
set_pte_at() drops the pte_ng() test since pte_user_exec() is
sufficient.

Fixes: cab15ce604 ("arm64: Introduce execute-only page access permissions")
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-31 16:44:07 +00:00
Thomas Petazzoni
d0979c07ff arm64: dts: marvell: adjust name of sd-mmc-gop clock in syscon
This commit adjusts the names of gatable clock #18 of the Marvell Armada
CP110 system controller. This clock not only controls SD/MMC, but also
the GOP (Group Of Ports) used for networking. So the clock is renamed to
{cpm,cps}-sd-mmc-gop instead of {cpm,cps}-sd-mmc.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-01-31 11:51:45 +01:00
Olof Johansson
ca6f848694 Samsung DeviceTree ARM64 update for v4.11, second round:
1. Use proper drive strengths on Exynos7.
 2. Fix significant current leak on Exynos5433-based TM2/TM2E due
    to disabled regulator.
 3. Add touchkey to TM2, set display clocks for Ultra HD modes.
 4. Cleanups and minor fixes for Exynos5433, TM2 and TM2E.
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJYj31/AAoJEME3ZuaGi4PXXjEQAI3QSvZNYagIX1ph+mRvyw+W
 GVBE7NGdkW8Cd3/2lIrLQ/+boqvM27u+4deJFG0Vx3+u2hHBbvoojjFTgQatO26I
 Hrf8sAtQ8K7ta9mMQ+CnQl/CyWP7od9aG5XeTy02YQR6+nunWikPfN0xJ+X1+ufN
 zvyGILuYlBZMS4aiQK5G4Ue5qqNU7DU0KGH0zDA/BiEJUESEaLvStOa+3YdXC8Qa
 WVWCEJQugNswipMf4Y7fi8MiOBsnNgs/dbTFA+XLdHBn8+uxikeFi1CjKlgv4nzE
 LegegLss7VZmRZY7IpPqme1ruqF1/YD7JDIuXnVMzQQxlNTkFACsd3ZlIQRQG4zp
 QiuNkV1Ymu/FfrYtjjLYOYOrOwKuAFmhXr8m34tgxCXNTvac/hO5+/w65yC/3Uu4
 qlYZvEmqZIsJwPFv1PU3LN4gcXiLXle8iWY8Tjad6y7MhIb46iT2MPrR4q/oSN5x
 LP7N21VFCdobjxk+zFqvE2jb1BOQuUhrPnHx2zUpH7IrJU8jKVCa9gFx/U5w/tnU
 40TYoO7aCk55xDsAWWQhKs6lxbdK/+OH+6vua5Q6dEZH5U9NsD2RgoQD8wPjNwmM
 8Kpgmu9oCbyxfCfbBgXm787X5ZcEjU4IrKfp2iMcmwR+QQf+TwQSmEvEFKfKmbc7
 rP8YPV0IhPRZRMP9+Nw+
 =rfRv
 -----END PGP SIGNATURE-----

Merge tag 'samsung-dt64-4.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64

Samsung DeviceTree ARM64 update for v4.11, second round:
1. Use proper drive strengths on Exynos7.
2. Fix significant current leak on Exynos5433-based TM2/TM2E due
   to disabled regulator.
3. Add touchkey to TM2, set display clocks for Ultra HD modes.
4. Cleanups and minor fixes for Exynos5433, TM2 and TM2E.

* tag 'samsung-dt64-4.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: dts: exynos: Add clocks to Exynos5433 LPASS module
  arm64: dts: exynos: set LDO7 regulator as always on
  arm64: dts: exynos: configure TV path clocks for Ultra HD modes
  arm64: dts: exynos: Fix drive strength of sd0_xxx pin definitions
  arm64: dts: exynos: Disable pull down for audio pins in Exynos5433 SoCs
  arm64: dts: exynos: Add TM2 touchkey node
  arm64: dts: exynos: Remove unneeded unit names in Exynos5433 nodes

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-30 21:07:34 -08:00
Neil Armstrong
6b6a186766 ARM64: dts: meson-gxbb-p200: add ADC laddered keys
Add the 5 buttons connected to a resistor laddered matrix and sampled
by the SAR ADC channel 0.

Only the p200 board has these buttons, the P201 doesn't.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-30 10:47:59 -08:00
Martin Blumenstingl
bd80ef5ed4 ARM64: dts: meson: meson-gx: add the SAR ADC
Add the SAR ADC to meson-gxbb.dtsi and meson-gxl.dtsi. GXBB provides a
10-bit ADC while GXL and GXM provide a 12-bit ADC.
Some boards use resistor ladder buttons connected through one of the ADC
channels. On newer devices (GXL and GXM) some boards use pull-ups/downs
to change the resistance (and thus the ADC value) on one of the ADC
channels to indicate the board revision.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-30 10:44:04 -08:00
Joerg Roedel
ce273db0ff Merge branch 'iommu/iommu-priv' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into arm/core 2017-01-30 16:05:18 +01:00
Marc Zyngier
13b7756cec arm/arm64: KVM: Stop propagating cacheability status of a faulted page
Now that we unconditionally flush newly mapped pages to the PoC,
there is no need to care about the "uncached" status of individual
pages - they must all be visible all the way down.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-01-30 13:47:38 +00:00
Marc Zyngier
8f36ebaf21 arm/arm64: KVM: Enforce unconditional flush to PoC when mapping to stage-2
When we fault in a page, we flush it to the PoC (Point of Coherency)
if the faulting vcpu has its own caches off, so that it can observe
the page we just brought it.

But if the vcpu has its caches on, we skip that step. Bad things
happen when *another* vcpu tries to access that page with its own
caches disabled. At that point, there is no garantee that the
data has made it to the PoC, and we access stale data.

The obvious fix is to always flush to PoC when a page is faulted
in, no matter what the state of the vcpu is.

Cc: stable@vger.kernel.org
Fixes: 2d58b733c8 ("arm64: KVM: force cache clean on page fault when caches are off")
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-01-30 13:47:37 +00:00
Vijaya Kumar K
e96a006cb0 KVM: arm/arm64: vgic: Implement KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO ioctl
Userspace requires to store and restore of line_level for
level triggered interrupts using ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO.

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-01-30 13:47:29 +00:00
Vijaya Kumar K
d017d7b0bd KVM: arm/arm64: vgic: Implement VGICv3 CPU interface access
VGICv3 CPU interface registers are accessed using
KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
as 64-bit. The cpu MPIDR value is passed along with register id.
It is used to identify the cpu for registers access.

The VM that supports SEIs expect it on destination machine to handle
guest aborts and hence checked for ICC_CTLR_EL1.SEIS compatibility.
Similarly, VM that supports Affinity Level 3 that is required for AArch64
mode, is required to be supported on destination machine. Hence checked
for ICC_CTLR_EL1.A3V compatibility.

The arch/arm64/kvm/vgic-sys-reg-v3.c handles read and write of VGIC
CPU registers for AArch64.

For AArch32 mode, arch/arm/kvm/vgic-v3-coproc.c file is created but
APIs are not implemented.

Updated arch/arm/include/uapi/asm/kvm.h with new definitions
required to compile for AArch32.

The version of VGIC v3 specification is defined here
Documentation/virtual/kvm/devices/arm-vgic-v3.txt

Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-01-30 13:47:25 +00:00
Vijaya Kumar K
4b927b94d5 KVM: arm/arm64: vgic: Introduce find_reg_by_id()
In order to implement vGICv3 CPU interface access, we will need to perform
table lookup of system registers. We would need both index_to_params() and
find_reg() exported for that purpose, but instead we export a single
function which combines them both.

Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-01-30 13:47:16 +00:00
Vijaya Kumar K
94574c9488 KVM: arm/arm64: vgic: Add distributor and redistributor access
VGICv3 Distributor and Redistributor registers are accessed using
KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_REDIST_REGS
with KVM_SET_DEVICE_ATTR and KVM_GET_DEVICE_ATTR ioctls.
These registers are accessed as 32-bit and cpu mpidr
value passed along with register offset is used to identify the
cpu for redistributor registers access.

The version of VGIC v3 specification is defined here
Documentation/virtual/kvm/devices/arm-vgic-v3.txt

Also update arch/arm/include/uapi/asm/kvm.h to compile for
AArch32 mode.

Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-01-30 13:47:07 +00:00
Andre Przywara
b8bcf0e1b2 arm64: allwinner: add BananaPi-M64 support
The Banana Pi M64 board is a typical single board computer based on the
Allwinner A64 SoC. Aside from the usual peripherals it features eMMC
storage, which is connected to the 8-bit capable SDHC2 controller.
Also it has a soldered WiFi/Bluetooth chip, so we enable UART1 and SDHC1
as those two interfaces are connected to it.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
2017-01-30 11:37:42 +01:00
Andre Przywara
e7ba733d32 arm64: allwinner: a64: add UART1 pin nodes
On many boards UART1 connects to a Bluetooth chip, so add the pinctrl
nodes for the only pins providing access to that UART. That includes
those pins for hardware flow control (RTS/CTS).

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
2017-01-30 11:37:40 +01:00
Andre Przywara
ebe3ae29c6 arm64: allwinner: pine64: add MMC support
All Pine64 boards connect an micro-SD card slot to the first MMC
controller.
Enable the respective DT node and specify the (always-on) regulator
and card-detect pin.
As a micro-SD slot does not feature a write-protect switch, we disable
this feature.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
2017-01-30 11:37:38 +01:00
Maxime Ripard
22be992fae arm64: allwinner: a64: Increase the MMC max frequency
The eMMC controller seem to have a maximum frequency of 200MHz, while the
regular MMC controllers are capped at 150MHz.

Since older SoCs cannot go that high, we cannot change the default maximum
frequency, but fortunately for us we have a property for that in the DT.

This also has the side effect of allowing to use the MMC HS200 and SD
SDR104 modes for the boards that support it (with either 1.2v or 1.8v IOs).

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Acked-by: Chen-Yu Tsai <wens@csie.org>
2017-01-30 11:37:36 +01:00
Maxime Ripard
a3e8f49262 arm64: allwinner: a64: Add MMC pinctrl nodes
The A64 only has a single set of pins for each MMC controller. Since we
already have boards that require all of them, let's add them to the DTSI.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Acked-by: Chen-Yu Tsai <wens@csie.org>
2017-01-30 11:37:34 +01:00
Andre Przywara
f3dff3478a arm64: allwinner: a64: Add MMC nodes
The A64 has 3 MMC controllers, one of them being especially targeted to
eMMC. Among other things, it has a data strobe signal and a 8 bits data
width.

The two other are more usual controllers that will have a 4 bits width at
most and no data strobe signal, which limits it to more usual SD or MMC
peripherals.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Acked-by: Chen-Yu Tsai <wens@csie.org>
2017-01-30 11:37:31 +01:00
Masahiro Yamada
fa11b3dd54 arm64: defconfig: enable CONFIG_MTD_NAND and CONFIG_MTD_NAND_DENALI_DT
Enable the NAND framework and the Denali NAND controller driver.
This NAND controller is used on UniPhier SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-29 21:18:00 -08:00
Masahiro Yamada
ddf4d59b34 arm64: defconfig: enable CONFIG_MTD_BLOCK
Enable the block layer support for MTD devices.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-29 21:17:58 -08:00
Olof Johansson
84b4e9f5a8 ZTE arm64 device tree update for 4.11:
- Enable cpufreq support for zx296718 by using new operating-points-v2
    bindings, so that it works with the generic cpufreq-dt driver.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJYjW1hAAoJEFBXWFqHsHzOkYUH/RNoyrOb3+KWfy0pczLBj98F
 SmF966hsGNPPKNZ+NFhqWdd1/iT9UzdIax09858HQzvyWSL7LSZNwbkHJU/2McKy
 zFo71IAnMNiNti6USiKVNX0HGx9ndnCChzJBUAcum46fJ7Kt0g8zjfBZfGjRq1cQ
 b3b1sJXt5P9+ebjUhrGXAykkS4zwpTHCdRAwmtKQEhU8Q5ri2+pqMtwvrt8XDfxl
 vFbckTpA0byd60TGvl/HecmafpYhXvOU7QGQaknzOnlH2o5dmwf0/i7Cw0sqyQn7
 JeBopKi7N2S2hN7ZlUYcEQ87FRGdf2u5WbQtcTRiYrZwvUf508hNMxGclMKUHNg=
 =EYrK
 -----END PGP SIGNATURE-----

Merge tag 'zte-dt64-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64

ZTE arm64 device tree update for 4.11:
 - Enable cpufreq support for zx296718 by using new operating-points-v2
   bindings, so that it works with the generic cpufreq-dt driver.

* tag 'zte-dt64-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: zx: support cpu-freq for zx296718

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-29 21:15:52 -08:00
Olof Johansson
ac43d9e0e5 Freescale arm64 device tree updates for 4.11:
- Add support for LS1012A SoC which is an ARMv8 SoC with single
    Cortex-A53 core, and the corresponding board support: FRDM, QDS
    and RDB.
  - Enable TMU (Thermal Monitoring Unit) support for LS1046A SoC.
  - Enable PCA9547 device for ls2080a-rdb board by removing 'disabled'
    status setting.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJYjWZxAAoJEFBXWFqHsHzOvGQIAJpdglbg/r997PFL43gODNaU
 RfF/userRtzsm3PZ9Uyf2EMg2Q66O92g9lqlr6+QNDSBuLl6iyyIomiCE3P9D/8A
 IggNiTKYuEFqWQUCQL6VSoOK5Ha9sa4D23rrGoRGbfKeiiM8M/gn7gNjOAmbbZx6
 VwVAAmkLObGmrkxq9IN++u7rIpTWLyOX+6wzQUYFfTD8OqGBrkpFpKOGTZXgzmeE
 Q8EebPh/ti2lFjGw1lWECjI4kEXIz7TMnKFsS/fYf7o6s778JQ/uocUl2UtTon1E
 aIIU72OMq6Mp/EoaMq3l9t1pgoEZMPVzyGiYPVypfEzkKTh26wb9POc6KiDO0JE=
 =g8mg
 -----END PGP SIGNATURE-----

Merge tag 'imx-dt64-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64

Freescale arm64 device tree updates for 4.11:
 - Add support for LS1012A SoC which is an ARMv8 SoC with single
   Cortex-A53 core, and the corresponding board support: FRDM, QDS
   and RDB.
 - Enable TMU (Thermal Monitoring Unit) support for LS1046A SoC.
 - Enable PCA9547 device for ls2080a-rdb board by removing 'disabled'
   status setting.

* tag 'imx-dt64-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  dt-bindings: clockgen: Add compatible string for LS1012A
  Documentation: DT: add LS1012A compatible for SCFG and DCFG
  Documentation: DT: Add entry for FSL LS1012A RDB, FRDM, QDS boards
  arm64: dts: ls1046a: Add TMU device tree support
  arm64: dts: Add support for FSL's LS1012A SoC
  arm64: dts: ls2080a-rdb: remove disable status of pca9547

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-29 21:09:19 -08:00
Olof Johansson
bb414fc190 mvebu dt64 for 4.11 (part 2)
- Add a new Armada 8K based board: MACCHIATOBin
 - Enable AHCI on the Armada 7K/8K SoCs
 -----BEGIN PGP SIGNATURE-----
 
 iIEEABECAEEWIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWIt9MyMcZ3JlZ29yeS5j
 bGVtZW50QGZyZWUtZWxlY3Ryb25zLmNvbQAKCRALBhiOFHI71Zw/AJ9NEi6v2zy2
 F16VJxKCgnhcJd++zwCfXA4/Z8eBtxXwsIPNLPMCTc9FtC0=
 =JDKj
 -----END PGP SIGNATURE-----

Merge tag 'mvebu-dt64-4.11-2' of git://git.infradead.org/linux-mvebu into next/dt64

mvebu dt64 for 4.11 (part 2)

- Add a new Armada 8K based board: MACCHIATOBin
- Enable AHCI on the Armada 7K/8K SoCs

* tag 'mvebu-dt64-4.11-2' of git://git.infradead.org/linux-mvebu:
  arm64: dts: marvell: add generic-ahci compatibles for CP110 ahci
  arm64: dts: marvell: Add DT for MACCHIATOBin board

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-29 21:03:12 -08:00
Olof Johansson
4c8cb9c40a arm64: tegra: Device tree changes for v4.11-rc1
This contains three patches that reintroduce symbolic identifiers for
 clocks, resets and mailboxes. These had been converted to literals in
 the v4.10 release to avoid complicated dependencies between branches.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAliLECQTHHRyZWRpbmdA
 bnZpZGlhLmNvbQAKCRDdI6zXfz6zoTa2EACD9/bu6s6tJopSAPBxKCI1voclTsXQ
 du1TCe2PO6Vz4CFkmpCo8mAsAexr+pQ6b8yX/SVOr/8A5N1J7TtQTUfK7Mzggeh+
 hI07xNDcE6LskOsEiLSApBpTwbCbpju7efIQWlnYByznfElnfLzuVUaXwezZTdG4
 rdXl2tCJOAuHwaA0dhlgj3YerVnDADSqZGMAa8tfpp0tN3P1/H9k7Q8Ze8Xcm2ag
 DZAo5XxL5XqcvEz1Rt8pTBHdtkGKeIO+3P6az2sCHMzqvB1Ejpa6sx6WIEQvJqxX
 VuTX27fFepWhEHfQMktLobxYl9zfsP/XMzlAve4EDrtJMmNjZ3glPNOuoEzicgsQ
 QpnYiF1HR/Q7BeZpGHDpSd3skTgtLvQZq9+CSQrOkXmhTnoHea5e1vHw6mR5Xi9V
 jvitE7bLSW2cWxHZ51QNDygobF4Gqmk9DFuKBDv22QYqh2d67J5TqpSJ2xURDH58
 GK5g32LAyoX8xehA1I+insyObKxe6QWOAg1Ukt1S0BgUHQhwBx/qh0ZVv0ktwcyF
 fYcnJmvvAHiaYJvePoy0aBRN01JCnYwzbKlM+KjfT6juuSiPqaJNVErurTYc2Gfz
 7/lT2EmhNbFnveflZGODpWTuygJZkmoGxADfyzP1D4U+6P35yaWVRTiGha4FWMEn
 spltHyMXJ4tBpQ==
 =eeee
 -----END PGP SIGNATURE-----

Merge tag 'tegra-for-4.11-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64

arm64: tegra: Device tree changes for v4.11-rc1

This contains three patches that reintroduce symbolic identifiers for
clocks, resets and mailboxes. These had been converted to literals in
the v4.10 release to avoid complicated dependencies between branches.

* tag 'tegra-for-4.11-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  arm64: tegra: Use symbolic reset identifiers
  arm64: tegra: Use symbolic clock identifiers
  arm64: tegra: Use symbolic HSP identifiers

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-29 20:59:55 -08:00
Olof Johansson
9cbcb077bf Second Round of Renesas ARM64 Based SoC DT Updates for v4.11
r8a779[56] SoCs:
 * Mark EthernetAVB device node disabled in DT for r8a779[56] SoCs
   - They are enabled as appropriate in board DT files
 * Link ARM GIC to clock and clock domain on r8a779[56] SoCs
 * Add thermal support
 
 r8a7795 SoC:
 * Tidyup audma definition order on r8a7795 SoC
 * Add missing power-domains property for SATA
 
 r8a7795/h3ulcb board:
 * Add MIX/CTU support as per support present in DT for r8a7796
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJYiw5mAAoJENfPZGlqN0++SqEP/3vqRuXgL0dxMPWzgTO0OW1h
 G0POAg9AN0gNSS0dgA8yaUOJvphYcM8HGEbyCh8iE4sQ29fel55H4MW2Be2XB1RI
 v08wcx2dr4N/FgbZdyw2VtVF7mmskpU+NEuQenpm3Pa2hYY9RuGdM84Fnk8o+Ks8
 npyoijNMxLdfuhtWnkPl+CDAs3Ney5CRUlBM3nxz89w0s/nTigVUToVQv1m43VDk
 KWK2+zrFQZNikodw1d3AwrFj9NtL7DakBY41vHHGh8UjEmgItd1ae//JHAlT9Y1J
 KmY/2kBBiI0xqYZXVfXl1g04Fxy4Hx8p07sThS1+MzIeBsPX4+2U3zffWns3Y3DK
 8ijF/lHbxo70ElYuwKX4HxNOeGgjh+ZF8nTzguqywgpVKIxot8FzLNi00wYji5in
 /gxE8+OORGiegy40/J8423l2IleN/DiBe6IIA3JB8zgZf4N61DsYDNcnlXb71WTA
 klPrNXTScE3IVbhK41HgkX38rJE3agF1jG3YIhWCUin8lvNw2UCX2ScsV8J6nksB
 OUSlA1Ls2ABdgEoDGh6Q1coyowHnOX8o5LtP+fZNH7V+LuDL01oyeCLoEeppPE+K
 Y3yygtZ8QeGEiBKWqb0/y2LvsPl/78BIImxIBDyokXFDQpb3fjBXT7dpH78dsSjU
 UiI9ZpMJ/nna0LOF43Pu
 =KG8o
 -----END PGP SIGNATURE-----

Merge tag 'renesas-arm64-dt2-for-v4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64

Second Round of Renesas ARM64 Based SoC DT Updates for v4.11

r8a779[56] SoCs:
* Mark EthernetAVB device node disabled in DT for r8a779[56] SoCs
  - They are enabled as appropriate in board DT files
* Link ARM GIC to clock and clock domain on r8a779[56] SoCs
* Add thermal support

r8a7795 SoC:
* Tidyup audma definition order on r8a7795 SoC
* Add missing power-domains property for SATA

r8a7795/h3ulcb board:
* Add MIX/CTU support as per support present in DT for r8a7796

* tag 'renesas-arm64-dt2-for-v4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: dts: r8a7796: Mark EthernetAVB device node disabled
  arm64: dts: r8a7795: Mark EthernetAVB device node disabled
  arm64: dts: r8a7795: tidyup audma definition order
  arm64: dts: r8a7796: Link ARM GIC to clock and clock domain
  arm64: dts: r8a7795: Link ARM GIC to clock and clock domain
  arm64: dts: r8a7796: Add R-Car Gen3 thermal support
  arm64: dts: r8a7795: Add R-Car Gen3 thermal support
  arm64: dts: r8a7795: Add missing power-domains property for sata
  arm64: dts: h3ulcb: follow sound CTU/MIX supports

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-29 20:57:26 -08:00
Masahiro Yamada
a3e3fa0bfa arm64: defconfig: enable CONFIG_MMC_SDHCI_CADENCE
Enable the Cadence SD/SDIO/eMMC controller.  This is used on
Socionext UniPhier SoC family.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-29 17:34:32 -08:00
Olof Johansson
656b532ffc ARM64: DT: Hisilicon SoC DT updates for 4.11
- Add binding for Hi3660 SoC and HiKey960 Board
 - Add binding for ARM Cortex-A73
 - Add dts files for HiKey960 development board
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJYiNBNAAoJEAvIV27ZiWZcR4oQAJKZUqtZsOjKumrBU4wji/AS
 le3PE8Ygy3O2lKsCtRhfeKkM9s1FVasvCbou3QsmbmKIKHCN3eS1PV1pJYEaINUD
 MymbxkpG3jNnZkUXui/mzpDDsNSODXR7UkieKXfkVHtxkHJzFrBcRSqobQc71+/u
 ACmiorYSqxZtABN0vGj00F4Jv9I7HneTNjBs591PF8dPQvzCIuL/duYyBAGQNWnR
 hUseVgDa+DYm7nPWI30M+hjF4sL6oVvxODkubrB4Gfo+xzoXCoa2rT/qMrsDCuQJ
 OHmSfaIMgvs76w7iCMBouwgemATv9/kHL470B3mEXaqUs7hxJrtNdDHR3ghks09b
 1YKaO03DZJmRXe8Ym6Or/PWVPea9ZBMhptd4Coya8nEapR25XNXR90EQ2Sihh1O+
 xTVZnLF7wVcEV61U+eEKaoUmQpf4bviO4EiaoSZvr9Qzdtsv4B3wPWKPDZIQg89D
 49hSxtbP5RPWwX9K7Kn0ougV8USSPDkSpXgvUP50ynLab5dT4/uRbXZL65HThF2M
 cJgd5nnlt/wZ5B4SA/P0sJp5T5QeZ0GsuENK5fmVAgpQMsGnbwGERPqBsj2Ds+8/
 qVhoyp3PD3uqpN+bN0TsoU+VV3PUD5kV3v2cTV7OPQdaPvEiOVMV3b8aTv89jxvV
 h09M1EtcPwk3Mo5NiGmF
 =zJLi
 -----END PGP SIGNATURE-----

Merge tag 'hisi-arm64-dt-for-4.11' of git://github.com/hisilicon/linux-hisi into next/dt64

ARM64: DT: Hisilicon SoC DT updates for 4.11

- Add binding for Hi3660 SoC and HiKey960 Board
- Add binding for ARM Cortex-A73
- Add dts files for HiKey960 development board

* tag 'hisi-arm64-dt-for-4.11' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: Add dts files for Hisilicon Hi3660 SoC
  dt-bindings: Add a support cpu type for cortex-a73
  document: dt: add binding for Hi3660 SoC

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-29 17:28:40 -08:00
Olof Johansson
5ee3dd850c For mt8173:
- set mm_sel clock to 400 MHz to support 4K HDMI
 - adjust power efficiency between the little and big cores
 - add a node for thermal calibration via e-fuse data
 -----BEGIN PGP SIGNATURE-----
 
 iQJLBAABCAA1FiEEiUuSfQSYnG8EMsBltDliWyzx00MFAliIjQgXHG1hdHRoaWFz
 LmJnZ0BnbWFpbC5jb20ACgkQtDliWyzx00PWjg//WVJsbVGXUcHGHmSOTNGjdAYR
 FB5ybdXDMyPhXLrUoY6xN0aCidXPTgv9gbLW37EWBlpGy+LAQN5ssMZMuEZeYJyb
 xR8yKrU+bcgQlwQrn3F35nJx7Eoh8T47dW2+C0ftzQxl0ZQirkmm9QnMg3/7xQ89
 LpA+Opqq3GkHG2Q2HTgpRqPaI3LZ/aZuWBtqhjxl0lYi+E2liA1cbvzIIeA3Uz+9
 rR+vlfQEG4CW9GnHDaLtg4Ad68YNlTQ7kU1070uwlpELwPAOV0SgxL1q0IBwj1WB
 FaTnfx5wFya8FZIPrnI+Dk1X1fDdkLZ16Cq+b3hBixiwLOs0XuLTAj/zMOoDLFcE
 vcyfRgFVbYo3ju+iQAZ49vt+OwDLjrCEGxO8XONT2bUN+3MW6EB0rKQC/uhO4vp7
 kEdJowUElvmDfnFqaAaWg8mrXzL+h/8y6SW1JT4pxTJpfXem3RnAiNywwrExdN5a
 9bj7WhJtA9t39wXkmdIAVQbIkGLwrks1TXaGoDPuuj21+Jzm+3uGZL4EyQU6TUA1
 jC04/5eBRVaA7JmU+/iegGdgaoyNs9PMhrjCUct6U3F2qvkRggAPnF9Eyj8stei6
 +kzRjhAup8exKHYUXTxROutngW7K93RpbMtsIDiiib4mKm3HueVMJEY5cJPW/yap
 4MttR/dH/W5PjTjkEVo=
 =hboI
 -----END PGP SIGNATURE-----

Merge tag 'v4.10-next-dts' of https://github.com/mbgg/linux-mediatek into next/dt64

For mt8173:
- set mm_sel clock to 400 MHz to support 4K HDMI
- adjust power efficiency between the little and big cores
- add a node for thermal calibration via e-fuse data

* tag 'v4.10-next-dts' of https://github.com/mbgg/linux-mediatek:
  arm64: dts: mt8173: add node for thermal calibration
  arm64: dts: mt8173: Fix cpu_thermal cooling-maps contributions
  arm64: dts: mt8173: add mmsel clocks for 4K support

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-29 17:21:10 -08:00
Olof Johansson
62f838c998 Qualcomm ARM64 Updates for v4.11
* Add Vol+ support for DB820C and APQ8016
 * Add HDMI audio support for APQ8016
 * Fix DB820C GPIO pinctrl name
 * Enable WCNSS on MSM8916
 * Add SCM node for MSM8996
 * Use fixed XO clock on MSM8916
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJYhvUBAAoJEFKiBbHx2RXVqnQQAK4xkBNoswr+afRkqOrEWZlc
 Ed1lotQ3gA202Q8iddMtmRgb2BjBRe9bH01mPA5MlB+/1TpmdT9dm6oNXN31DJbn
 L//om+669nzgPg2NhQAGfxfE97VzUTIksuVw1piCXK3eLlQCbccwifxITONbo+5Q
 7818h2sb306sMet0LI+UkjLzJeU1dL1F6EKusErZatWBWuKMz3bFs/Ch0KUC1GRR
 e7AU8i9f+jy2BSQFSOZbYkeInWvhee5IIp6dZMW0nINnaoVXafchvQzfkbi6t+Os
 qv2nQUMco4ZlU9KbTWcNZQ0SlyVWLE9h2Khc8QF3uy9G6RxU8nSy25Mwi57enz3B
 O+ousFAd79yUYyLZXA7OijAB+joSinl1OX6iFnq1H5Dx+XDRBXxmt97l5O0GanZn
 CZQmGcdKMbbgV1nboM4NjUn2Nwn07EpaAbPPgsTJJBR519UV/TG82RE7TDbrxeUx
 ABaylDX6rtgA+TdOP/wqqhEmEZ0xYko2TJBk6VqNfPAj/QVDS0lFbAzIjfqIM8q0
 XyLIM+snIldu7qFgFwikUumFI7xVVghlmVJ0zPZEwKkLRZs0MJyt7TFPwDYmktXG
 SDqq/E58YXFn4sbThFwGV3Ayaun4MjDHMTT1Xn95r+7O1WvLt3hu0LqW6b3AvqRO
 /vNnTwmv0bwxV4fN6qs/
 =UglA
 -----END PGP SIGNATURE-----

Merge tag 'qcom-arm64-for-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt64

Qualcomm ARM64 Updates for v4.11

* Add Vol+ support for DB820C and APQ8016
* Add HDMI audio support for APQ8016
* Fix DB820C GPIO pinctrl name
* Enable WCNSS on MSM8916
* Add SCM node for MSM8996
* Use fixed XO clock on MSM8916

* tag 'qcom-arm64-for-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
  arm64: dts: db820c: add support to volume up key
  arm64: dts: apq8016-sbc: Limit MPP4 high state to 1.8V
  arm64: dts: apq8016-sbc: Add Volume Up key device node
  arm64: dts: apq8016-sbc: add support to hdmi audio via adv7533
  arm64: dts: db820c: fix gpio pinctrl name correctly
  ARM: dts: msm8916: Add and enable wcnss node
  arm64: dts: msm8996: Add SCM DT node
  arm64: dts: qcom: msm8916: Use fixed factor xo clock

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-29 15:08:11 -08:00
Olof Johansson
f41afa53ad UniPhier ARM64 SoC DT updates for v4.11
- Add an SD reset controller node for LD11 SoC
 - Add an eMMC controller node for LD11/LD20 SoC
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJYhLQbAAoJED2LAQed4NsGrI0P/0gx+XKmhFsQkvfIl1cd4dHm
 ttc7pvYK5UaF/tO7b+9HXO2CS7SeEfizkAc0S1djGouqp+N6vWCAnimoPTDBwQOG
 dANWWEfhluzxf8F9tgVmHGRx9VaGgnJq7oK2X59k0otNsWA1bEdL8iUX460rlOdi
 U4mqOuZthehg8e1hPmgj5P4fQM0o/uCydyU7V1PX8mc9Bv09r+34qbRXhWjP0t6d
 pdlTqLIwTMDY4/B7fMU7DnQFVjeN21DtVcepKr93Fnrv1TADpl6BydN8+No/JBRb
 ILH9RxkRSwqzb5K53C5X4P9c1dVom7coxKKrnCsFaUswu7J5rF4a1HtfeTDpfJDp
 4aNgBXzT1vg+GAehAqUeBktw0IH6qGktt4+S7xLDt6E3KmY/9HyP0ZoBqJbN5/pb
 Cn8MQ1Gc03L8miP3YeC4znTl7gX04HAQ7WbQzXQmvY960JMfvZd9tGVSB7f/BsR7
 F1fNh3Lv8V51trf+cBs9y/DyhMEy/zQbU9ZpL5Pz6u/IQit+D8VeNxQ06vy1rkJL
 YalMIpeLYl4mdL3mpG6ov5BUPDJpQuWC5QmxMLMMVQRa0oI/UKUO72K26dFnsEAb
 ms8E2PKA0uy4Tw5IkwJv6Rmw1dmRjK2LIadqE+VOBiNeqYL3ENU4Xyu4OislY4jI
 kBb0Wm5Olik+qStJiR8A
 =DP8G
 -----END PGP SIGNATURE-----

Merge tag 'uniphier-dt64-v4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt64

UniPhier ARM64 SoC DT updates for v4.11

- Add an SD reset controller node for LD11 SoC
- Add an eMMC controller node for LD11/LD20 SoC

* tag 'uniphier-dt64-v4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier:
  arm64: dts: uniphier: add eMMC controller node for LD11/LD20
  arm64: dts: uniphier: add SD-ctrl node for LD11 SoC

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-29 14:49:04 -08:00
Olof Johansson
dc6328feeb 64bit dts changes with some adjustments to the pcie controller,
usb clocks, grf phandles for the rk3399 CRUs, epd pinctrl settings,
 a phandle to the rk3399 tsadc and converting boards to use the
 recently introduced pin constants.
 -----BEGIN PGP SIGNATURE-----
 
 iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAliBUMUQHGhlaWtvQHNu
 dGVjaC5kZQAKCRDzpnnJnNEdgeszCAC0VNLtUhe6ksHGJzvgP1diZLPghPsKticu
 tmpxFVJrZTYFmxacvO3w2rXNvwtWsay812m+wmpbCYe2rpE1WwRYEhDIVbQ0hIuD
 I7fiG6wKaGVEu+5XmVi+6tGouGKSZA0zBlcOja4kFeBPsyDDL0SISu1iopfD/o0z
 u/2EfcBRQFLUotLKLY8t//I+RJ4IsDMQ4zh1AJ1NDfUVCqthE7sJzoa8eJuHaKjj
 YPKdfJlUIZAXJiXuDrjrkkbUQT0GuYha0CtWE2nUn4clfrIWivvgJCXFfEnKtM9+
 OguqMChemOXL7SanHGKqM4RHL6Qq0F3Y162UODDX2AC3QYxxv8XK
 =i0J0
 -----END PGP SIGNATURE-----

Merge tag 'v4.11-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64

64bit dts changes with some adjustments to the pcie controller,
usb clocks, grf phandles for the rk3399 CRUs, epd pinctrl settings,
a phandle to the rk3399 tsadc and converting boards to use the
recently introduced pin constants.

* tag 'v4.11-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: add rockchip,grf property for RK3399 PMUCRU/CRU
  arm64: dts: rockchip: add aspm-no-l0s for rk3399
  arm64: dts: rockchip: add max-link-speed for rk3399
  arm64: dts: rockchip: use pin constants to describe gpios
  arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399
  arm64: dts: rockchip: add rk3399 eDP HPD pinctrl
  arm64: dts: rockchip: add rk3399 thermal_zones phandle

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-29 14:42:21 -08:00
Martin Blumenstingl
249a2243e9 ARM64: dts: meson-gxl: add the pwm_ao_b pin
This adds the pwm_ao_b pin to allow boards which have an LED connected
to GPIOAO_9 to use the leds-pwm driver (by activating the pwm_AO_ab node
and passing the pwm_ao_b_pin pinctrl-reference).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-27 11:00:41 -08:00
Martin Blumenstingl
e48512244f ARM64: dts: meson-gx: add the missing pwm_AO_ab node
All Meson GX SoCs (GXBB, GXL and GXM) have a PWM controller within the
AO domain. When one of the board's LEDs is connected to one of the AO
PWM pins then this can be used to dim that LED (when the leds-pwm driver
is used).
Add the pwm_AO_ab to allow such devices to use the leds-pwm driver.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-27 11:00:40 -08:00
Mark Rutland
49f6cba617 arm64: handle sys and undef traps consistently
If an EL0 instruction in the SYS class triggers an exception, do_sysintr
looks for a sys64_hook matching the instruction, and if none is found,
injects a SIGILL. This mirrors what we do for undefined instruction
encodings in do_undefinstr, where we look for an undef_hook matching the
instruction, and if none is found, inject a SIGILL.

Over time, new SYS instruction encodings may be allocated. Prior to
allocation, exceptions resulting from these would be handled by
do_undefinstr, whereas after allocation these may be handled by
do_sysintr.

To ensure that we have consistent behaviour if and when this happens, it
would be beneficial to have do_sysinstr fall back to do_undefinstr.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Suzuki Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-27 17:13:14 +00:00
Neil Armstrong
bba8e3f427 ARM64: dts: meson-gx: Add firmware reserved memory zones
The Amlogic Meson GXBB/GXL/GXM secure monitor uses part of the memory space,
this patch adds these reserved zones.

Without such reserved memory zones, running the following stress command :
$ stress-ng --vm 16 --vm-bytes 128M --timeout 10s
multiple times:

Could lead to the following kernel crashes :
[   46.937975] Bad mode in Error handler detected on CPU1, code 0xbf000000 -- SError
...
[   47.058536] Internal error: Attempting to execute userspace memory: 8600000f [#3] PREEMPT SMP
...
Instead of the OOM killer.

Fixes: 4f24eda840 ("ARM64: dts: Prepare configs for Amlogic Meson GXBaby")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
[khilman: added Fixes tag, added _reserved and unit addresses]
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-01-27 16:46:43 +01:00
Jerome Brunet
feb3cbea09 ARM64: dts: meson-gxbb-odroidc2: fix GbE tx link breakage
OdroidC2 GbE link breaks under heavy tx transfer. This happens even if the
MAC does not enable Energy Efficient Ethernet (No Low Power state Idle on
the Tx path). The problem seems to come from the phy Rx path, entering the
LPI state.

Disabling EEE advertisement on the phy prevent this feature to be
negociated with the link partner and solve the issue.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-01-27 16:46:42 +01:00
Christopher Covington
fa715319c1 arm64: Use __tlbi() macros in KVM code
Refactor the KVM code to use the __tlbi macros, which will allow an errata
workaround that repeats tlbi dsb sequences to only change one location.
This is not intended to change the generated assembly and comparing before
and after vmlinux objdump shows no functional changes.

Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Christopher Covington <cov@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-27 13:52:34 +00:00
Shanker Donthineni
ea5f9d1a69 arm64: Define Falkor v1 CPU
Define the MIDR implementer and part number field values for the Qualcomm
Datacenter Technologies Falkor processor version 1 in the usual manner.

Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Christopher Covington <cov@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-27 13:52:10 +00:00
Prashanth Prakash
606f42265d arm64: skip register_cpufreq_notifier on ACPI-based systems
On ACPI based systems where the topology is setup using the API
store_cpu_topology, at the moment we do not have necessary code
to parse cpu capacity and handle cpufreq notifier, thus
resulting in a kernel panic.

Stack:
        init_cpu_capacity_callback+0xb4/0x1c8
        notifier_call_chain+0x5c/0xa0
        __blocking_notifier_call_chain+0x58/0xa0
        blocking_notifier_call_chain+0x3c/0x50
        cpufreq_set_policy+0xe4/0x328
        cpufreq_init_policy+0x80/0x100
        cpufreq_online+0x418/0x710
        cpufreq_add_dev+0x118/0x180
        subsys_interface_register+0xa4/0xf8
        cpufreq_register_driver+0x1c0/0x298
        cppc_cpufreq_init+0xdc/0x1000 [cppc_cpufreq]
        do_one_initcall+0x5c/0x168
        do_init_module+0x64/0x1e4
        load_module+0x130c/0x14d0
        SyS_finit_module+0x108/0x120
        el0_svc_naked+0x24/0x28

Fixes: 7202bde8b7 ("arm64: parse cpu capacity-dmips-mhz from DT")
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Prashanth Prakash <pprakash@codeaurora.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-01-27 11:30:36 +00:00
Russell King
7292ff67b9 arm64: dts: marvell: add generic-ahci compatibles for CP110 ahci
Testing with an Armada 8040 board shows that adding the generic-ahci
compatible to the CP110 AHCI nodes gets us working AHCI on the board.
A previous patch series posted by Thomas Petazzoni was retracted when
it was realised that the IP was supposed to be, and is, compatible
with the standard register layout.

Add this compatible.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-01-27 11:13:01 +01:00
Thierry Reding
7bcf266462 arm64: tegra: Use symbolic reset identifiers
Now that the corresponding device tree binding include has been merged,
convert the DTS files to use symbolic names instead of numeric ones.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-27 10:13:24 +01:00
Geert Uytterhoeven
7e1c23b94e arm64: dts: r8a7796: Mark EthernetAVB device node disabled
Device nodes representing I/O devices should be marked disabled in the
SoC-specific DTS, and overridden by board-specific DTSes where needed.

Fixes: 8e8b9eaef8 ("arm64: dts: renesas: r8a7796: Add EthernetAVB instance")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-01-27 10:09:02 +01:00
Geert Uytterhoeven
0d1390ff28 arm64: dts: r8a7795: Mark EthernetAVB device node disabled
Device nodes representing I/O devices should be marked disabled in the
SoC-specific DTS, and overridden by board-specific DTSes where needed.

Fixes: a92843c8a6 ("arm64: dts: r8a7795: add EthernetAVB device node")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-01-27 10:09:01 +01:00
Kuninori Morimoto
769fa8369b arm64: dts: r8a7795: tidyup audma definition order
Current r8a7795.dtsi defines audma -> ipmmu -> dma order.
Because of this order, dma can connect to ipmmu, but
audma can't connect to it.
This patch moves audma order as ipmmu -> dma -> audma.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-01-27 10:08:46 +01:00
Geert Uytterhoeven
0bacdbc76b arm64: dts: r8a7796: Link ARM GIC to clock and clock domain
Link the ARM GIC to the INTC-AP module clock, and add it to the SYSC
"always-on" PM Domain, so it can be power managed using that clock.

Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-01-27 09:25:08 +01:00
Geert Uytterhoeven
b6e56e4c1f arm64: dts: r8a7795: Link ARM GIC to clock and clock domain
Link the ARM GIC to the INTC-AP module clock, and add it to the SYSC
"always-on" PM Domain, so it can be power managed using that clock.

Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-01-27 09:25:07 +01:00
Wolfram Sang
af25d1c2a9 arm64: dts: r8a7796: Add R-Car Gen3 thermal support
Signed-off-by: Hien Dang <hien.dang.eb@renesas.com>
Signed-off-by: Thao Nguyen <thao.nguyen.yb@rvc.renesas.com>
Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-01-27 09:25:06 +01:00
Wolfram Sang
b443cd1740 arm64: dts: r8a7795: Add R-Car Gen3 thermal support
Signed-off-by: Hien Dang <hien.dang.eb@renesas.com>
Signed-off-by: Thao Nguyen <thao.nguyen.yb@rvc.renesas.com>
Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-01-27 09:25:06 +01:00
Geert Uytterhoeven
2cab226c34 arm64: dts: r8a7795: Add missing power-domains property for sata
This went unnoticed as the sata_rcar driver doesn't support Runtime PM
yet, but manages module clocks manually.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-01-27 09:25:05 +01:00
Marek Szyprowski
7547162ac3 arm64: dts: exynos: Add clocks to Exynos5433 LPASS module
Exynos5433 LPASS module requires some clocks for proper operation with
power domain.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-01-26 22:04:20 +02:00
Robin Murphy
adbe7e26f4 arm64: dma-mapping: Fix dma_mapping_error() when bypassing SWIOTLB
When bypassing SWIOTLB on small-memory systems, we need to avoid calling
into swiotlb_dma_mapping_error() in exactly the same way as we avoid
swiotlb_dma_supported(), because the former also relies on SWIOTLB state
being initialised.

Under the assumptions for which we skip SWIOTLB, dma_map_{single,page}()
will only ever return the DMA-offset-adjusted physical address of the
page passed in, thus we can report success unconditionally.

Fixes: b67a8b29df ("arm64: mm: only initialize swiotlb when necessary")
CC: stable@vger.kernel.org
CC: Jisheng Zhang <jszhang@marvell.com>
Reported-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-26 12:25:14 +00:00
Kefeng Wang
2e449048a2 arm64: Kconfig: select COMPAT_BINFMT_ELF only when BINFMT_ELF is set
Fix warning:
"(COMPAT) selects COMPAT_BINFMT_ELF which has unmet direct dependencies
(COMPAT && BINFMT_ELF)"

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-26 12:19:49 +00:00
Ard Biesheuvel
79ba11d24b arm64: kernel: do not mark reserved memory regions as IORESOURCE_BUSY
Memory regions marked as NOMAP should not be used for general allocation
by the kernel, and should not even be covered by the linear mapping
(hence the name). However, drivers or other subsystems (such as ACPI)
that access the firmware directly may legally access them, which means
it is also reasonable for such drivers to claim them by invoking
request_resource(). Currently, this is prevented by the fact that arm64's
request_standard_resources() marks reserved regions as IORESOURCE_BUSY.

So drop the IORESOURCE_BUSY flag from these requests.

Reported-by: Hanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-26 12:15:13 +00:00
Geert Uytterhoeven
cbb999dd0b arm64: Use __pa_symbol for empty_zero_page
If CONFIG_DEBUG_VIRTUAL=y and CONFIG_ARM64_SW_TTBR0_PAN=y:

    virt_to_phys used for non-linear address: ffffff8008cc0000 (empty_zero_page+0x0/0x1000)
    WARNING: CPU: 0 PID: 0 at arch/arm64/mm/physaddr.c:14 __virt_to_phys+0x28/0x60
    ...
    [<ffffff800809abb4>] __virt_to_phys+0x28/0x60
    [<ffffff8008a02600>] setup_arch+0x46c/0x4d4

Fixes: 2077be6783 ("arm64: Use __pa_symbol for kernel symbols")
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Laura Abbott <labbott@redhat.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-26 12:14:50 +00:00
Chen-Yu Tsai
4f9758302c arm64: dts: allwinner: Remove no longer used pinctrl/sun4i-a10.h header
All dts files for the sunxi platform have been switched to the generic
pinconf bindings. As a result, the sunxi specific pinctrl macros are
no longer used.

Remove the #include entry with the following command:

    sed -i -e '/pinctrl\/sun4i-a10.h/D' \
	arch/arm64/boot/dts/allwinner/*.dts?

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-26 11:15:04 +01:00
Chen Feng
35ca816813 arm64: dts: Add dts files for Hisilicon Hi3660 SoC
Add initial dtsi file to support Hisilicon Hi3660 SoC with
support of Octal core CPUs in two clusters(4 * A53 & 4 * A73).

Also add dts file to support HiKey960 development board which
based on Hi3660 SoC.
The output console is earlycon "earlycon=pl011,0xfdf05000".
And the con_init uart5 with a fixed clock, which already
configured at bootloader.

When clock is available, the uart5 will be modified.

Tested on HiKey960 Board.

Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-01-25 16:08:29 +00:00
Christoffer Dall
10f92c4c53 KVM: arm/arm64: vgic: Add debugfs vgic-state file
Add a file to debugfs to read the in-kernel state of the vgic.  We don't
do any locking of the entire VGIC state while traversing all the IRQs,
so if the VM is running the user/developer may not see a quiesced state,
but should take care to pause the VM using facilities in user space for
that purpose.

We also don't support LPIs yet, but they can be added easily if needed.

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
2017-01-25 13:50:03 +01:00
Thierry Reding
c58f5f8848 arm64: tegra: Use symbolic clock identifiers
Now that the corresponding device tree binding include has been merged,
convert the DTS files to use symbolic names instead of numeric ones.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25 09:23:56 +01:00
Thierry Reding
5edcebb96b arm64: tegra: Use symbolic HSP identifiers
Now that the corresponding device tree binding include has been merged,
convert the DTS files to use symbolic names instead of numeric ones.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25 09:23:55 +01:00
Andrzej Hajda
6c992d35b8 arm64: dts: exynos: set LDO7 regulator as always on
LDO7 regulator beside DSI and HDMI provides power for core blocks in Exynos
5433 SoC. Disabling it causes serious current leak - about 200mA.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-01-24 19:50:57 +02:00
Bart Van Assche
815dd18788 treewide: Consolidate get_dma_ops() implementations
Introduce a new architecture-specific get_arch_dma_ops() function
that takes a struct bus_type * argument. Add get_dma_ops() in
<linux/dma-mapping.h>.

Signed-off-by: Bart Van Assche <bart.vanassche@sandisk.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Juergen Gross <jgross@suse.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: linux-arch@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Russell King <linux@armlinux.org.uk>
Cc: x86@kernel.org
Signed-off-by: Doug Ledford <dledford@redhat.com>
2017-01-24 12:23:35 -05:00
Bart Van Assche
5657933dbb treewide: Move dma_ops from struct dev_archdata into struct device
Some but not all architectures provide set_dma_ops(). Move dma_ops
from struct dev_archdata into struct device such that it becomes
possible on all architectures to configure dma_ops per device.

Signed-off-by: Bart Van Assche <bart.vanassche@sandisk.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Juergen Gross <jgross@suse.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: linux-arch@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Russell King <linux@armlinux.org.uk>
Cc: x86@kernel.org
Signed-off-by: Doug Ledford <dledford@redhat.com>
2017-01-24 12:23:35 -05:00
Bart Van Assche
5299709d0a treewide: Constify most dma_map_ops structures
Most dma_map_ops structures are never modified. Constify these
structures such that these can be write-protected. This patch
has been generated as follows:

git grep -l 'struct dma_map_ops' |
  xargs -d\\n sed -i \
    -e 's/struct dma_map_ops/const struct dma_map_ops/g' \
    -e 's/const struct dma_map_ops {/struct dma_map_ops {/g' \
    -e 's/^const struct dma_map_ops;$/struct dma_map_ops;/' \
    -e 's/const const struct dma_map_ops /const struct dma_map_ops /g';
sed -i -e 's/const \(struct dma_map_ops intel_dma_ops\)/\1/' \
  $(git grep -l 'struct dma_map_ops intel_dma_ops');
sed -i -e 's/const \(struct dma_map_ops dma_iommu_ops\)/\1/' \
  $(git grep -l 'struct dma_map_ops' | grep ^arch/powerpc);
sed -i -e '/^struct vmd_dev {$/,/^};$/ s/const \(struct dma_map_ops[[:blank:]]dma_ops;\)/\1/' \
       -e '/^static void vmd_setup_dma_ops/,/^}$/ s/const \(struct dma_map_ops \*dest\)/\1/' \
       -e 's/const \(struct dma_map_ops \*dest = \&vmd->dma_ops\)/\1/' \
    drivers/pci/host/*.c
sed -i -e '/^void __init pci_iommu_alloc(void)$/,/^}$/ s/dma_ops->/intel_dma_ops./' arch/ia64/kernel/pci-dma.c
sed -i -e 's/static const struct dma_map_ops sn_dma_ops/static struct dma_map_ops sn_dma_ops/' arch/ia64/sn/pci/pci_dma.c
sed -i -e 's/(const struct dma_map_ops \*)//' drivers/misc/mic/bus/vop_bus.c

Signed-off-by: Bart Van Assche <bart.vanassche@sandisk.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Juergen Gross <jgross@suse.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: linux-arch@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Russell King <linux@armlinux.org.uk>
Cc: x86@kernel.org
Signed-off-by: Doug Ledford <dledford@redhat.com>
2017-01-24 12:23:35 -05:00
Kevin Hilman
7eea67101b ARM64: dts: meson-gxl: rename Nexbox A95x for consistency
Since the GXL family has S905X and S905D SoCs, we're keeping the SoC
name in the DTS filename for clarity.  Rename this file accordingly to
be consistent with the rest of the GXL DTS files.

Cc: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-23 10:18:24 -08:00
Neil Armstrong
d537d289de ARM64: dts: meson-gxbb: Add support for WeTek Hub and Play
Adds support for the WeTek Hub and Play2 boards.
The Hub is an extremely small IPTv Set-Top-Box and the Play2 is a more
traditionnal Satellite or Terrestrial and IPTv Set-Top-Box.

Both are based on the p200 Reference Design and out-of-tree support is
based on LibreELEC kernel at [1].

[1] https://github.com/wetek-enigma/linux-amlogic

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-23 10:18:11 -08:00
Andrzej Hajda
4e09f4a6b6 arm64: dts: exynos: configure TV path clocks for Ultra HD modes
Ultra HD modes requires clock ticking at increased rate.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-01-23 18:32:57 +02:00
Will Deacon
4a8d8a14c0 arm64: dma-mapping: Only swizzle DMA ops for IOMMU_DOMAIN_DMA
The arm64 DMA-mapping implementation sets the DMA ops to the IOMMU DMA
ops if we detect that an IOMMU is present for the master and the DMA
ranges are valid.

In the case when the IOMMU domain for the device is not of type
IOMMU_DOMAIN_DMA, then we have no business swizzling the ops, since
we're not in control of the underlying address space. This patch leaves
the DMA ops alone for masters attached to non-DMA IOMMU domains.

Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-23 15:05:40 +00:00
Ard Biesheuvel
11e3b725cf crypto: arm64/aes-blk - honour iv_out requirement in CBC and CTR modes
Update the ARMv8 Crypto Extensions and the plain NEON AES implementations
in CBC and CTR modes to return the next IV back to the skcipher API client.
This is necessary for chaining to work correctly.

Note that for CTR, this is only done if the request is a round multiple of
the block size, since otherwise, chaining is impossible anyway.

Cc: <stable@vger.kernel.org> # v3.16+
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-01-23 22:41:33 +08:00
dawei.chien@mediatek.com
6de18454e0 arm64: dts: mt8173: add node for thermal calibration
Add this for supporting thermal calibration by e-fuse data.

Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-01-23 10:18:13 +01:00
Masahiro Yamada
3a93cc261a arm64: dts: uniphier: add eMMC controller node for LD11/LD20
Add Cadence's eMMC controller node for LD11/LD20.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-22 21:12:42 +09:00
Masahiro Yamada
8f32b8124a arm64: dts: uniphier: add SD-ctrl node for LD11 SoC
The LD11 SoC is equipped with SD-ctrl (0x59810000) as well as
MIO-ctrl (0x5b3e0000).  The SD-ctrl block on this SoC has just
one register for controlling RST_n pin of the eMMC device.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-22 21:12:42 +09:00
Pankaj Dubey
9f6fe6f013 arm64: dts: exynos: Fix drive strength of sd0_xxx pin definitions
As per Exynos7 datasheet FSYS1 pinctrl block does not support drive
strength value of 0x3. This patch fixes this and update the correct
drive strength for sd0_xxx pin definitions.

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-01-21 18:26:16 +02:00
Linus Torvalds
4c9eff7af6 KVM fixes for v4.10-rc5
ARM:
  - Fix for timer setup on VHE machines
  - Drop spurious warning when the timer races against the vcpu running
    again
  - Prevent a vgic deadlock when the initialization fails (for stable)
 
 s390:
  - Fix a kernel memory exposure (for stable)
 
 x86:
  - Fix exception injection when hypercall instruction cannot be patched
 -----BEGIN PGP SIGNATURE-----
 
 iQEcBAABCAAGBQJYglwIAAoJEED/6hsPKofoZp0H+gLLEeKP0Mu+olXiOWjB/KFp
 WBDAR1872xIjvEcOl9l6AZgdmp2hk7KW1t+kJj5npgu237v6fHBO9ybqrAfhfU4l
 PH23zOebL15HINcwCK6OcxOTiOtgae5Nui1cnLJBHDQgPTC/VmIE8NgV/qrMyo2r
 Vth+K/cBLKiWG9JhyQvxmrfupNJUknLSH7CTnlO/fC8GEJzDfMpUl7B1Ui0TGK53
 ExVgVLg3F28SErj9bUU8y4VJhMrwDAf2Kx2BNHqDbzXMzTdp0LrGRymFLl2/Gxez
 zLtZDfGYYzEhPp1NuDydlxLb8ymnsQNB7K6Kau0w9JoAvOYwfUYfDt+GaTegwYM=
 =dPtS
 -----END PGP SIGNATURE-----

Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

Pull KVM fixes from Radim Krčmář:
 "ARM:
   - Fix for timer setup on VHE machines
   - Drop spurious warning when the timer races against the vcpu running
     again
   - Prevent a vgic deadlock when the initialization fails (for stable)

  s390:
   - Fix a kernel memory exposure (for stable)

  x86:
   - Fix exception injection when hypercall instruction cannot be
     patched"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
  KVM: s390: do not expose random data via facility bitmap
  KVM: x86: fix fixing of hypercalls
  KVM: arm/arm64: vgic: Fix deadlock on error handling
  KVM: arm64: Access CNTHCTL_EL2 bit fields correctly on VHE systems
  KVM: arm/arm64: Fix occasional warning from the timer work function
2017-01-20 14:19:34 -08:00
Linus Torvalds
f8f2d4bdb5 - Avoid potential stack information leak via the ptrace ABI caused by
uninitialised variables
 
 - SWIOTLB DMA API fall-back allocation fix when the SWIOTLB buffer is
   not initialised (all RAM is suitable for 32-bit DMA masks)
 
 - Fix the bad_mode function returning for unhandled exceptions coming
   from user space
 
 - Fix name clash in __page_to_voff()
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJYghTJAAoJEGvWsS0AyF7xCTsP/jKcUyfpDVwegS/Qf66pTfnQ
 THDDgNvadnFuU+qUJc+97ZV0V4q1l2azxbelK8tG0i68jRQtf41gY13yXtxyvUzl
 u4stMhlIZX7VSIUhfti+cfER+VObAvA4f5XK7taXgDFUqgaFOLapjyzzKC40djim
 OLAo8PtxB9n3AgV8M5uDvdHIvxVkot84k0vKlQO1wBYQowMDMTkHw9HLbGx2pHnm
 58xFB/aSwEYOy4wJcPISQu1pq02T8LwCnOU7tE4tNkcQSIopEsbqX3+TXMktlvc8
 f9W8J0knLRGwp0nGw3+qnmDu1r5juFkrE6U/0jxTxLGnH6voPemlWmzuZQMTqJTW
 uPvALhkU5qd8S4FaOxGMZb01F7xisvBgD984Ej2uYyTBCS5Q0iyB/Z/szDMFZh4C
 1v2W2eDGUvJgt5f8b83/s9j637OxT2M3P/swZYo4lqQ18srzMzgN2/RkoJuBcjmW
 mLkm4qcswWpmItmwGgW3yRaBTZfbO1ab/fuXFe+AtwPhNyClMU/88L90Sn7zgOET
 rCcm6gJe0RwaFJ2tjUWpx6Ygejn/eOsDXCo3DRnyOEQq26KOjjimMct0uR4z2INV
 ODrLYZjRMIwNAMdD3vcFvIBfHrlKqK0lq8T+lc0wk+6Pggu2X5yDqPP8ckNImfRv
 aTD7Rsbk7/P5IgtKwwjV
 =IArX
 -----END PGP SIGNATURE-----

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Catalin Marinas:

 - avoid potential stack information leak via the ptrace ABI caused by
   uninitialised variables

 - SWIOTLB DMA API fall-back allocation fix when the SWIOTLB buffer is
   not initialised (all RAM is suitable for 32-bit DMA masks)

 - fix the bad_mode function returning for unhandled exceptions coming
   from user space

 - fix name clash in __page_to_voff()

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: avoid returning from bad_mode
  arm64/ptrace: Reject attempts to set incomplete hardware breakpoint fields
  arm64/ptrace: Avoid uninitialised struct padding in fpr_set()
  arm64/ptrace: Preserve previous registers for short regset write
  arm64/ptrace: Preserve previous registers for short regset write
  arm64/ptrace: Preserve previous registers for short regset write
  arm64: mm: avoid name clash in __page_to_voff()
  arm64: Fix swiotlb fallback allocation
2017-01-20 11:44:47 -08:00
Kefeng Wang
0f84832fb8 arm64: defconfig: Enable NUMA and NUMA_BALANCING
Since much more arm64 SoCs with numa nodes, it's better to enable
NUMA and NUMA_BALANCING to improve the performance on test.

Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-01-20 16:14:26 +00:00
Zhou Wang
e2d2cfac44 arm64: defconfig: enable SMMUv3 config
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-01-20 15:30:26 +00:00
Marek Szyprowski
20422a0c29 arm64: dts: exynos: Disable pull down for audio pins in Exynos5433 SoCs
Common definition for I2S, PMC, SPDIF buses should not define any pull
control for the individual pins. Correct this by changing samsung,pin-pud
property to EXYNOS_PIN_PULL_NONE like it is defined for other Exynos SoCs.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-01-20 17:15:15 +02:00
Linus Torvalds
44b4b461a0 ARM: SoC fixes
We've been sitting on fixes for a while, and they keep trickling in at a low
 rate. Nothing in here comes across as particularly scary or noteworthy, for
 the most part it's a large collection of small DT tweaks.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJYgVpgAAoJEIwa5zzehBx3umkP/A2082k9R6srk+/bdeDf6F+w
 YiiMJdu37jWb/W71gMlr95NC3zmk4c+U0eHj8iOdsuOYyzSZ6uUQcm8Etg7N2JwR
 cupsySXvlRJ9Hq28SPe6vRnNFqGiDGmGrcfNlwnfHd/CausaJBdcocbyTsVt+omO
 WGMDPy5miN8TIbYQiu6jF2sXkuuVHwXlQyBi52xW5w7Uy0iZDZdsW6GuziK0zpDH
 k0QktKkVx/Q8Riy3b9Vj7kKwvaGXF2JBMsGpORhs4+JcdZl9u+GBJnmehpXmABTn
 8mXEU5zu6gnBHMXxExaK/ZlFDk0yHNxGfapoRQwYecPeBZQGXWu9vyUa3/38npLr
 egyMDzBgJJyHXbs7BXy6weiysn8adsNS3juhniL7mLuTp2hGZHNK6IcH2tV4Z/kD
 hq/VTK/BzmKAY/GP3psoQXVavIUifh498ymCkgoZtUx8Eqq9ZrFA9hkm86F/9eOJ
 vfGNTdVuPI51tdKrmqMXglI4iBc35oSyOQUlUL0DXVlKrzzaVPbQwnIZclgI+VGn
 qos8l8vPxDzQ7lRgMzXsmq8D6pDSfUZQqvUr8gld/zNvd8+LsdmVYHdrvbIQu+sN
 TsI0TyfU4JphSdCPtFKasu7aDBmwfB8npDXUcOazAyG8UyHZpikR9WmmIQ63BwRL
 DYVre9JMhrfL6ZY2kaKC
 =cc1U
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "We've been sitting on fixes for a while, and they keep trickling in at
  a low rate. Nothing in here comes across as particularly scary or
  noteworthy, for the most part it's a large collection of small DT
  tweaks"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (24 commits)
  ARM: dts: da850-evm: fix read access to SPI flash
  ARM: dts: omap3: Fix Card Detect and Write Protect on Logic PD SOM-LV
  ARM64: dts: meson-gxbb-odroidc2: Disable SCPI DVFS
  ARM: dts: OMAP5 / DRA7: indicate that SATA port 0 is available.
  ARM: dts: NSP: Fix DT ranges error
  ARM: multi_v7_defconfig: set bcm47xx watchdog
  ARM: multi_v7_defconfig: fix config typo
  ARM: dts: dra72-evm-revc: fix typo in ethernet-phy node
  soc: ti: wkup_m3_ipc: Fix error return code in wkup_m3_ipc_probe()
  ARM: ux500: fix prcmu_is_cpu_in_wfi() calculation
  ARM: dts: sunxi: Change node name for pwrseq pin on Olinuxino-lime2-emmc
  ARM: dts: sun8i: Support DTB build for NanoPi M1
  ARM: dts: sun6i: hummingbird: Enable display engine again
  ARM: dts: sun6i: Disable display pipeline by default
  ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus" part 3
  ARM: dts: imx6qdl-nitrogen6_som2: fix sgtl5000 pinctrl init
  ARM: dts: imx6qdl-nitrogen6_max: fix sgtl5000 pinctrl init
  ARM: OMAP1: DMA: Correct the number of logical channels
  ARM: dts: am335x-icev2: Remove the duplicated pinmux setting
  ARM: OMAP2+: Fix WL1283 Bluetooth Baud Rate
  ...
2017-01-19 16:40:03 -08:00
Russell King
d3f4759bcf arm64: dts: marvell: Add DT for MACCHIATOBin board
Add a cut-down version of the DTS file for the community board
MACCHIATOBin from SolidRun based on Marvell Armada 8040 SoC to suit
the current mainlined Armada 8040 state.

This brings support for mainly SATA, SPI flash and UART.  The USB
descriptions are included but are not tested in this form due to the
lack of mainline GPIO.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Acked-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-01-19 23:52:17 +01:00
Jaechul Lee
5205761d7a arm64: dts: exynos: Add TM2 touchkey node
Add DT node for TM2 touchkey device.

Signed-off-by: Beomho Seo <beomho.seo@samsung.com>
Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-01-19 22:08:45 +02:00
Neil Armstrong
4e6118974c ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency
In order to keep consistency naming with the Nexbox A1 DTS file, remove the
S912 SoC name in the GXM DT files.

Suggested-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-19 10:05:18 -08:00
Mitchel Humpherys
737c85ca1c arm64/dma-mapping: Implement DMA_ATTR_PRIVILEGED
The newly added DMA_ATTR_PRIVILEGED is useful for creating mappings that
are only accessible to privileged DMA engines.  Implement it in
dma-iommu.c so that the ARM64 DMA IOMMU mapper can make use of it.

Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Tested-by: Robin Murphy <robin.murphy@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-19 15:56:19 +00:00
Mark Rutland
7d9e8f71b9 arm64: avoid returning from bad_mode
Generally, taking an unexpected exception should be a fatal event, and
bad_mode is intended to cater for this. However, it should be possible
to contain unexpected synchronous exceptions from EL0 without bringing
the kernel down, by sending a SIGILL to the task.

We tried to apply this approach in commit 9955ac47f4 ("arm64:
don't kill the kernel on a bad esr from el0"), by sending a signal for
any bad_mode call resulting from an EL0 exception.

However, this also applies to other unexpected exceptions, such as
SError and FIQ. The entry paths for these exceptions branch to bad_mode
without configuring the link register, and have no kernel_exit. Thus, if
we take one of these exceptions from EL0, bad_mode will eventually
return to the original user link register value.

This patch fixes this by introducing a new bad_el0_sync handler to cater
for the recoverable case, and restoring bad_mode to its original state,
whereby it calls panic() and never returns. The recoverable case
branches to bad_el0_sync with a bl, and returns to userspace via the
usual ret_to_user mechanism.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Fixes: 9955ac47f4 ("arm64: don't kill the kernel on a bad esr from el0")
Reported-by: Mark Salter <msalter@redhat.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: stable@vger.kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-01-19 15:38:22 +00:00
Olof Johansson
560741d7d9 This pull request contains Broadcom ARM64-based SoC Device Tree changes for
4.11, please pull the following changes:
 
 - Jon adds Device Tree nodes for the GICv2m and PAXB/PAXC PCIe interfaces on
   the Northstar 2 SoCs, he also enables PAXC on the Northstar 2 SVK reference
   board. He also updates the reserved memory entry for the Nitro firmware,
   required to get the on-chip NICs to work. Finally he adds support for the
   BCM958712DxXMC reference board which is a subset of existing boards.
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJYfsSQAAoJEIfQlpxEBwcEGDUP+gLIXb7EJ7rzNOYskYuf5blU
 Uidfec5wbdu8Tnm4KbqWxopKdfvg13tx6YTwVjmtVwNP06iG9g9ytC3XA/YTYbLw
 Gs8S0QhMpPn9mJ94ix0+DUT8NwTFLxPS/veCqpQLG/usOkXkt8xR36DfA63C+qK/
 s6G87AZklsjUtkJn06FtrtvdyxRDHsl7Tj/7U+J9/mGoWdmZDbtooMP6GXDMS34N
 XDMU1L18Kr74R5YUyTotzu2D0y/CG1edSTGPpHbrVKnI8YGTkLHyL9V1anbGS7v0
 z+E+K6Lbe4M0xBqDVH/fOejwOxg30qDc4t9SDjMV813txZChwyVhNswNH6Nnn+3I
 zcN5bRs9fT71B7H2Q+zkqRDf0nLx6fJt3rvQ/iPHOHil3wgpa1yckHnAi11BE1gp
 hBEZPZkMw4ZPjtPc+CUoE9vWRzdJtoGYlE6dOxzz4UbP9QYmU0ai7F7OhxsQ+lKM
 LpVM7jAf+E4lRBsOSkKuV/3uDzLqwIKdEBqjYaSe83MIO1uC1XIgN2lHU4Q3BITx
 nyYdiJymr2AwXjyi8W7nN9neAmDiNlfi7fPZvYy0crd8GWn3uoROBLR7NoL+alPo
 eBjiKJe6WJen+0VQR67a17kZ7WCkqCR0QUrXZTl8yVdzDZWaPHLXcCR8dulYwvMT
 zvT+oFf7yA+DB3bCykd5
 =JBHv
 -----END PGP SIGNATURE-----

Merge tag 'arm-soc/for-4.11/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64

This pull request contains Broadcom ARM64-based SoC Device Tree changes for
4.11, please pull the following changes:

- Jon adds Device Tree nodes for the GICv2m and PAXB/PAXC PCIe interfaces on
  the Northstar 2 SoCs, he also enables PAXC on the Northstar 2 SVK reference
  board. He also updates the reserved memory entry for the Nitro firmware,
  required to get the on-chip NICs to work. Finally he adds support for the
  BCM958712DxXMC reference board which is a subset of existing boards.

* tag 'arm-soc/for-4.11/devicetree-arm64' of http://github.com/Broadcom/stblinux:
  arm64: dts: NS2: add support for XMC form factor
  arm64: dts: NS2: reserve memory for Nitro firmware
  arm64: dts: NS2: enable PAXC on NS2 SVK
  arm64: dts: NS2: enable GICv2m for PAXB/PAXC interfaces

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-18 16:30:43 -08:00
Olof Johansson
992ffc3eb1 ARMv8 Vexpress/Juno DT updates for v4.11
1. Addition of Coresight support on Juno R1 and R2 variants
 
 2. Addition of STM(System Trace Macrocell) support on all Juno variants
 
 3. Removed incorrect nesting of dtsi files
 
 4. Removed untested USB hub only available on initial Juno R0 motherboard
 
 5. Added ETR SMMU power domain and dma-ranges property
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABCAAGBQJYf3YFAAoJEABBurwxfuKYq2YP/3Yknoe0K+h6c0N7yyQVWsbd
 5qbY3xcbQDh7JsDz2AuTeRJtgP4V6cUqe9LbNF4Z0myOmrNSLhPNLKxm9OCsbxty
 bL7rSIXjL3dPCm4MENFw3yNzgIukZGTyFrtDMbYcqxXlSo5JMWEn/yztBeP1onmn
 aFiy1FBRtkuAe5gVMAwIz1oK/0eCBqlKfa9SXq9dmCXKv5fuq51aMr5dlAq8Q5ja
 RvxDaNvh8P4Vh/DVZrRBAmhA5uw3dovgAQiSIg56TermEk64UOGksv1pGE4ycMFU
 TOQ5YuxqT2J7HLUy2TqwZhaNcblGlG98fpqLCMWC1r4GkO0KwGimnXTGSiZxJIMk
 0/quwCO6PguHacCGV+PUV7HH3WriH0REjbKEuZ0louYBtjHj1rvZJLC0fO6Mt2i7
 EDdVqiPwfAAbHo6zrK1Axz1Q7FTEYRcvaZV5QXmz9rLjUFMFtzHg7r+L21TAtxoq
 Q9l589/vO5f8t9B6notXV1hgg0RRI+jGH8KeDO2lvNfpXgGC3BkwnWcJlv2AkhgG
 +TrpOtkXbdsKee6G0mW/W1vtooDh/w7IKU7ncaPp+9Sq/uvkKYnDS9ubfAkgIjwT
 turauXHIeFS6AID+Y+O2/q/hDve0eNXKFV6CheZHgDKEXAp+LCQm7Wtd8HYNuG3S
 FBnUYKVEswLaFDUUv8Wk
 =VeiR
 -----END PGP SIGNATURE-----

Merge tag 'juno-updates-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt64

ARMv8 Vexpress/Juno DT updates for v4.11

1. Addition of Coresight support on Juno R1 and R2 variants
2. Addition of STM(System Trace Macrocell) support on all Juno variants
3. Removed incorrect nesting of dtsi files
4. Removed untested USB hub only available on initial Juno R0 motherboard
5. Added ETR SMMU power domain and dma-ranges property

* tag 'juno-updates-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  arm64: dts: juno: remove motherboard USB node
  arm64: dts: juno: add ETR SMMU power domain
  arm64: dts: juno: add dma-ranges property
  arm64: dts: juno: add missing CoreSight STM component
  arm64: dts: juno: add CoreSight support for Juno r1/r2 variants
  arm64: dts: juno: refactor CoreSight support on Juno r0
  arm64: dts: juno: remove dtsi nesting inside tree structure

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-18 16:14:29 -08:00
Neil Armstrong
b949165c86 ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes
Add pinctrl nodes for HDMI HPD and DDC pins modes for Amlogic Meson GXL
and GXBB SoCs.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-18 14:35:07 -08:00
Andreas Färber
2fbbc4bf69 ARM64: dts: meson-gxbb-vega-s95: Add LED
There is one blue LED on the front of the device. Keep it lit and
configure it as panic indicator.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-18 14:35:04 -08:00
Martin Blumenstingl
261e1d5cc5 ARM64: dts: meson-gx: add the serial CTS and RTS pin groups
This adds pinctrl group nodes for the CTS and RTS pins of each serial
controller. This makes it possible to enable the CTS and RTS pins which
are controlled by the serial controller hardware (through the meson_uart
driver).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-18 14:35:01 -08:00
Martin Blumenstingl
890a96a257 ARM64: dts: meson-gx: add the missing uart_AO_B
This adds the missing node for the uart_AO_B port to the meson-gx.dtsi
(as this is supported by GXBB, GXL and GXM) along with the required
pinctrl pins. This is required as some boards are using it (the boards
from the Khadas VIM series for example have it exposed on the pin
headers).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-18 14:34:50 -08:00
Dave Martin
ad9e202aa1 arm64/ptrace: Reject attempts to set incomplete hardware breakpoint fields
We cannot preserve partial fields for hardware breakpoints, because
the values written by userspace to the hardware breakpoint
registers can't subsequently be recovered intact from the hardware.

So, just reject attempts to write incomplete fields with -EINVAL.

Cc: <stable@vger.kernel.org> # 3.7.x-
Fixes: 478fcb2cdb ("arm64: Debugging support")
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Acked-by: Will Deacon <Will.Deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-01-18 18:05:12 +00:00
Dave Martin
aeb1f39d81 arm64/ptrace: Avoid uninitialised struct padding in fpr_set()
This patch adds an explicit __reserved[] field to user_fpsimd_state
to replace what was previously unnamed padding.

This ensures that data in this region are propagated across
assignment rather than being left possibly uninitialised at the
destination.

Cc: <stable@vger.kernel.org> # 3.7.x-
Fixes: 60ffc30d56 ("arm64: Exception handling")
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Acked-by: Will Deacon <Will.Deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-01-18 18:05:10 +00:00
Dave Martin
a672401c00 arm64/ptrace: Preserve previous registers for short regset write
Ensure that if userspace supplies insufficient data to
PTRACE_SETREGSET to fill all the registers, the thread's old
registers are preserved.

Cc: <stable@vger.kernel.org> # 4.3.x-
Fixes: 5d220ff942 ("arm64: Better native ptrace support for compat tasks")
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Acked-by: Will Deacon <Will.Deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-01-18 18:05:08 +00:00
Dave Martin
9dd73f72f2 arm64/ptrace: Preserve previous registers for short regset write
Ensure that if userspace supplies insufficient data to
PTRACE_SETREGSET to fill all the registers, the thread's old
registers are preserved.

Cc: <stable@vger.kernel.org> # 3.19.x-
Fixes: 766a85d7bc ("arm64: ptrace: add NT_ARM_SYSTEM_CALL regset")
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Acked-by: Will Deacon <Will.Deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-01-18 18:05:06 +00:00
Dave Martin
9a17b876b5 arm64/ptrace: Preserve previous registers for short regset write
Ensure that if userspace supplies insufficient data to
PTRACE_SETREGSET to fill all the registers, the thread's old
registers are preserved.

Cc: <stable@vger.kernel.org> # 3.7.x-
Fixes: 478fcb2cdb ("arm64: Debugging support")
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Acked-by: Will Deacon <Will.Deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-01-18 18:05:02 +00:00
Javier Martinez Canillas
0e879a3e7d arm64: dts: exynos: Remove unneeded unit names in Exynos5433 nodes
The "samsung,exynos5433-mipi-video-phy" and "samsung,exynos5250-dwusb3"
DT bindings don't specify a reg property for these nodes, so having a
unit name leads to the following DTC warnings:

Node /soc/video-phy@105c0710 has a unit name, but no reg property
Node /soc/usb@15400000 has a unit name, but no reg property
Node /soc/usb@15a00000 has a unit name, but no reg property

Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-01-18 18:25:09 +02:00
Robin Murphy
1492a86436 arm64: dts: juno: remove motherboard USB node
The first batch of Juno boards included a discrete USB controller chip
as a contingency in case of issues with the USB 2.0 IP integrated into
the SoC. As it turned out, the latter was fine, and to the best of my
knowledge the motherboard USB was never even brought up and validated.

Since this also isn't present on later boards, and uses a compatible
string undocumented and unmatched by any driver in the kernel, let's
just tidy it away for ever to avoid any confusion.

Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2017-01-18 14:01:20 +00:00
Robin Murphy
fd47c2062a arm64: dts: juno: add ETR SMMU power domain
It is not at all clear from the documentation, but straightforward to
determine in practice, that the ETR SMMU is actually in the DEBUGSYS
power domain. Add that to the DT so that anyone brave enough to enable
said SMMU doesn't experience a system lockup on boot, especially a
sneaky one which goes away as soon as you connect an external debugger
to have a look at where it's stuck (thus powering up DEBUGSYS by other
means and allowing it to make progress again before actually halting...)

Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2017-01-18 14:01:10 +00:00
Robin Murphy
193d00a2b3 arm64: dts: juno: add dma-ranges property
The interconnects around Juno have a 40-bit address width, and DMA
masters have no restrictions beyond their own individual limitations.
Describe this to ensure that DT-based DMA masks get set up correctly
for all devices capable of 40-bit addressing.

Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2017-01-18 14:01:02 +00:00
Oleksandr Andrushchenko
1c8a946bf3 arm64: mm: avoid name clash in __page_to_voff()
The arm64 __page_to_voff() macro takes a parameter called 'page', and
also refers to 'struct page'. Thus, if the value passed in is not
called 'page', we'll refer to the wrong struct name (which might not
exist).

Fixes: 3fa72fe9c6 ("arm64: mm: fix __page_to_voff definition")
Acked-by: Mark Rutland <mark.rutland@arm.com>
Suggested-by: Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>
Signed-off-by: Oleksandr Andrushchenko <Oleksandr_Andrushchenko@epam.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-01-18 11:24:04 +00:00
Mike Leach
cde6f9ab10 arm64: dts: juno: add missing CoreSight STM component
This patch adds the missing CoreSight STM component definition to the
device tree of all the juno variants(r0,r1,r2)

STM component is connected to different funnels depending on Juno
platform variant.

Reviewed-and-tested-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mike Leach <mike.leach@linaro.org>
[sudeep.holla@arm.com: minor changelog update and reorganising the STM
	node back into juno-base.dtsi to avoid duplication]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2017-01-18 11:14:41 +00:00
Mike Leach
cdc07e9604 arm64: dts: juno: add CoreSight support for Juno r1/r2 variants
The CoreSight support added for Juno is valid for only Juno r0.
The Juno r1 and r2 variants have additional components and alternative
connection routes between trace source and sinks.

This patch builds on top of the existing r0 support and extends it to
Juno r1/r2 variants.

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mike Leach <mike.leach@linaro.org>
[sudeep.holla@arm.com: minor changelog update and major reorganisation of
	the common coresight components back into juno-base.dtsi to avoid
	duplication, also renamed funnel node names]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2017-01-18 11:14:23 +00:00
Sudeep Holla
19ac17c031 arm64: dts: juno: refactor CoreSight support on Juno r0
Currently the Coresight components are supported only on Juno r0
variant. In preparation to add support to Juno r1/r2 variants, this
patch refactors the existing coresight device nodes so that r1/r2
support can be added easily.

It also cleans up some of the device node names which were previously
named so as they were confused as the labels rather than the node names.

Reviewed-and-tested-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2017-01-18 11:14:14 +00:00
Sudeep Holla
d29e849caf arm64: dts: juno: remove dtsi nesting inside tree structure
Currently juno-clock.dtsi and juno-base.dtsi are nested badly inside
the device tree structure. It's generally good practice to ensure that
individual dtsi stand by themselves at the top of the file.

This patch removes the nesting of the above mentioned dtsi files and
makes them independent.

Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2017-01-18 11:14:07 +00:00
Neil Armstrong
f7bcd4b6f6 ARM64: dts: meson-gxbb-odroidc2: Disable SCPI DVFS
The current hardware is not able to run with all cores enabled at a
cluster frequency superior at 1536MHz.
But the currently shipped u-boot for the platform still reports an OPP
table with possible DVFS frequency up to 2GHz, and will not change since
the off-tree linux tree supports limiting the OPPs with a kernel parameter.
A recent u-boot change reports the boot-time DVFS around 100MHz and
the default performance cpufreq governor sets the maximum frequency.
Previous version of u-boot reported to be already at the max OPP and
left the OPP as is.
Nevertheless, other governors like ondemand could setup the max frequency
and make the system crash.

This patch disables the DVFS clock and disables cpufreq.

Fixes: 70db166a2b ("ARM64: dts: meson-gxbb: Add SCPI with cpufreq & sensors Nodes")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-17 12:10:54 -08:00
Mark Rutland
829d2bd133 arm64: entry-ftrace.S: avoid open-coded {adr,ldr}_l
Some places in the kernel open-code sequences using ADRP for a symbol
another instruction using a :lo12: relocation for that same symbol.
These sequences are easy to get wrong, and more painful to read than is
necessary. For these reasons, it is preferable to use the
{adr,ldr,str}_l macros for these cases.

This patch makes use of these in entry-ftrace.S, removing open-coded
sequences using adrp. This results in a minor code change, since a
temporary register is not used when generating the address for some
symbols, but this is fine, as the value of the temporary register is not
used elsewhere.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-17 17:41:19 +00:00
Mark Rutland
526d10ae02 arm64: efi-entry.S: avoid open-coded adr_l
Some places in the kernel open-code sequences using ADRP for a symbol
another instruction using a :lo12: relocation for that same symbol.
These sequences are easy to get wrong, and more painful to read than is
necessary. For these reasons, it is preferable to use the
{adr,ldr,str}_l macros for these cases.

This patch makes use of these in efi-entry.S, removing open-coded
sequences using adrp.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Matt Fleming <matt@codeblueprint.co.uk>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-17 17:41:14 +00:00
Mark Rutland
9bb003600e arm64: head.S: avoid open-coded adr_l
Some places in the kernel open-code sequences using ADRP for a symbol
another instruction using a :lo12: relocation for that same symbol.
These sequences are easy to get wrong, and more painful to read than is
necessary. For these reasons, it is preferable to use the
{adr,ldr,str}_l macros for these cases.

This patch makes use of adr_l these in head.S, removing an open-coded
sequence using adrp.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-17 17:41:02 +00:00
Radim Krčmář
1b1973ef9a KVM/ARM updates for 4.10-rc4
- Fix for timer setup on VHE machines
 - Drop spurious warning when the timer races against
   the vcpu running again
 - Prevent a vgic deadlock when the initialization fails
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJYeLkqAAoJECPQ0LrRPXpDpasP/iynAP2/28LNQ7L8r3be0m7N
 PCZv3gpsTtu1cmTlpiPQVPqzBUVPXQMJJAnDIhA7e1YbYfYJUIhEirVUQ56oT+lY
 nmnoquzNFGUNkYRHUj8RTeQ8ISuP/iPlWOVlSh4n2rbrHFAxX1+W1xXdOedbdFJp
 oFDRR6DCB4qdIxt7dtTcfObhwVlro8WDOfClNqiUDUdhxfDBD7mEPYNO2J2D0/ca
 6YQAkxPzP/MJgKl0mVRjjxhkoNSt6lP0uyU65X67g7i2ZlFRyU3PvqwPm3JOY++V
 Uuff2ud81D5yYwf0+6sA+i+707jezgsoiuFnwUFQVjW/9rpIK7W1gzqht2VWZNgJ
 NjhFPtNhOFkam/sxPFiSaTNyhUNgrg6C/qPDBF0pPlyGd0mtrvJdVG4y/R9YGSB3
 JoiwaFdoi9buEakpRbhu4y5bhcDZZPAo+l+2OanpeE6y3zypqTsJRop8H/qhnv8R
 FFzqycBjeEcVo9ZKIpqQVEnp0njBcHKmqblMswgSgGKe3816iGC+kj4oMm7J57Yq
 vy1OKQMuur+rSRyH7LpVN1HYiq9yBHdbHsXxUjEWSD5dtPAGdOhAP0kAzXlPbEot
 WkVQO2uEV3EKs0UQjWkLKNVJKh/pPaWH3z8ENRlf+pASzvO+UYRmY3sjfDcg3AsI
 7Lxc+CVJJ4ExJbFe/OTk
 =7cIH
 -----END PGP SIGNATURE-----

Merge tag 'kvm-arm-for-4.10-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm

KVM/ARM updates for 4.10-rc4

- Fix for timer setup on VHE machines
- Drop spurious warning when the timer races against
  the vcpu running again
- Prevent a vgic deadlock when the initialization fails
2017-01-17 15:04:59 +01:00
Sudeep Holla
9a802431c5 arm64: cacheinfo: add support to override cache levels via device tree
The cache hierarchy can be identified through Cache Level ID(CLIDR)
architected system register. However in some cases it will provide
only the number of cache levels that are integrated into the processor
itself. In other words, it can't provide any information about the
caches that are external and/or transparent.

Some platforms require to export the information about all such external
caches to the userspace applications via the sysfs interface.

This patch adds support to override the cache levels using device tree
to take such external non-architected caches into account.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Tested-by: Tan Xiaojun <tanxiaojun@huawei.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-17 12:09:54 +00:00
Alexander Graf
524dabe1c6 arm64: Fix swiotlb fallback allocation
Commit b67a8b29df introduced logic to skip swiotlb allocation when all memory
is DMA accessible anyway.

While this is a great idea, __dma_alloc still calls swiotlb code unconditionally
to allocate memory when there is no CMA memory available. The swiotlb code is
called to ensure that we at least try get_free_pages().

Without initialization, swiotlb allocation code tries to access io_tlb_list
which is NULL. That results in a stack trace like this:

  Unable to handle kernel NULL pointer dereference at virtual address 00000000
  [...]
  [<ffff00000845b908>] swiotlb_tbl_map_single+0xd0/0x2b0
  [<ffff00000845be94>] swiotlb_alloc_coherent+0x10c/0x198
  [<ffff000008099dc0>] __dma_alloc+0x68/0x1a8
  [<ffff000000a1b410>] drm_gem_cma_create+0x98/0x108 [drm]
  [<ffff000000abcaac>] drm_fbdev_cma_create_with_funcs+0xbc/0x368 [drm_kms_helper]
  [<ffff000000abcd84>] drm_fbdev_cma_create+0x2c/0x40 [drm_kms_helper]
  [<ffff000000abc040>] drm_fb_helper_initial_config+0x238/0x410 [drm_kms_helper]
  [<ffff000000abce88>] drm_fbdev_cma_init_with_funcs+0x98/0x160 [drm_kms_helper]
  [<ffff000000abcf90>] drm_fbdev_cma_init+0x40/0x58 [drm_kms_helper]
  [<ffff000000b47980>] vc4_kms_load+0x90/0xf0 [vc4]
  [<ffff000000b46a94>] vc4_drm_bind+0xec/0x168 [vc4]
  [...]

Thankfully swiotlb code just learned how to not do allocations with the FORCE_NO
option. This patch configures the swiotlb code to use that if we decide not to
initialize the swiotlb framework.

Fixes: b67a8b29df ("arm64: mm: only initialize swiotlb when necessary")
Signed-off-by: Alexander Graf <agraf@suse.de>
CC: Jisheng Zhang <jszhang@marvell.com>
CC: Geert Uytterhoeven <geert+renesas@glider.be>
CC: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-01-17 11:48:11 +00:00
Olof Johansson
f638d8f15f mvebu dt64 for 4.11 (part 1)
- Correct license text which was mangled when switching to dual license
 - Add SPI and I2C nodes on Armada 3700(driver support had been already
   merged)
 - Add support for the ethernet switch on the EspressoBin board (driver
   support not yet merged)
 -----BEGIN PGP SIGNATURE-----
 
 iIEEABECAEEWIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWHkJzyMcZ3JlZ29yeS5j
 bGVtZW50QGZyZWUtZWxlY3Ryb25zLmNvbQAKCRALBhiOFHI71S01AKCYMJtp3ZYd
 nWFez/9S2sUDbmEQRwCgiwEJ4cDIz68s5+EXJE4nXAKlhrg=
 =HIbH
 -----END PGP SIGNATURE-----

Merge tag 'mvebu-dt64-4.11-1' of git://git.infradead.org/linux-mvebu into next/dt64

mvebu dt64 for 4.11 (part 1)

- Correct license text which was mangled when switching to dual license
- Add SPI and I2C nodes on Armada 3700(driver support had been already
  merged)
- Add support for the ethernet switch on the EspressoBin board (driver
  support not yet merged)

* tag 'mvebu-dt64-4.11-1' of git://git.infradead.org/linux-mvebu:
  ARM64: dts: marvell: Correct license text
  arm64: dts: marvell: Add I2C definitions for the Armada 3700
  arm64: dts: marvell: Enable spi0 on the board Armada-3720-db
  arm64: dts: marvell: Add definition of SPI controller for Armada 3700
  arm64: dts: marvell: Add ethernet switch definition for the ESPRESSObin

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-16 22:46:16 -08:00
Olof Johansson
076b01d3f6 mvebu defconfig64 for 4.11 (part 1)
Update arm64 defconfig by adding XORv2 for Marvell Armada 7K/8K
 -----BEGIN PGP SIGNATURE-----
 
 iIEEABECAEEWIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWHkE/iMcZ3JlZ29yeS5j
 bGVtZW50QGZyZWUtZWxlY3Ryb25zLmNvbQAKCRALBhiOFHI71XkoAJ9NBtmwvDxp
 Rqi2aEq7ki6oU/jybwCdG0CYDLRyzoR4HKVy0mVtgnsMnLw=
 =lET3
 -----END PGP SIGNATURE-----

Merge tag 'mvebu-defconfig64-4.11-1' of git://git.infradead.org/linux-mvebu into next/arm64

mvebu defconfig64 for 4.11 (part 1)

Update arm64 defconfig by adding XORv2 for Marvell Armada 7K/8K

* tag 'mvebu-defconfig64-4.11-1' of git://git.infradead.org/linux-mvebu:
  arm64: defconfig: enable XORv2 for Marvell Armada 7K/8K

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-16 22:43:17 -08:00
Olof Johansson
127e0ee0e5 Samsung DeviceTree ARM64 update for v4.11:
1. Add bus frequency and voltage scalling on Exynos5433 TM2 device (along with
    necessary bus nodes and Platform Performance Monitoring Unit on Exynos5433).
 2. Use macros for pinctrl settings on Exynos5433.
    This contains necessary header with bindings.
 3. Minor cleanups in Exynos5433 DTSI and boards using it.
 4. Create common DTSI betweem Exynos5433 TM2E and TM2E.
 5. Add HDMI/TV to Exynos5433 TM2.
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJYeO01AAoJEME3ZuaGi4PXX7QP/0wlZmoUeBiAGuVDsOUqS5jT
 FQd+lC4r1croSn8oFMKx6Ta8LxwI8XjmuCOvRjBxBtNxzq4wTCABlVOexWjAHCMz
 KhYWcTBGIj+8Nk6BkBg8ga5iQAqQY6JhKKRBg0xbe8XqlkMThapJ3C90A4oWTeqm
 D9SERXJzeJiBr2dqVORxt3d/XtLXXKEw+3/qK9iOu4uAZE7NECUD1EIOM6gGXkLM
 55hOw7Qzh7g4L9umqVCj37gNK5nu4HLvvVA0FasMi6CL+EuHs5im9NOP3naN152f
 /W4xPRS6hVYzvueWHILBmaxNbwYMthJ34gXIdMg4td/nO/nVRMCplnsjbm+1rQDQ
 UoasRanobu+s+5nzRGybkM5Ni8QHZ/CsXK8DtSSlPC3tPMs5GywGIEfXqHqJzabs
 WlmhD68LWFzh2Og8X2KzB+5Pkmvp3HuUVLqPtsPpjnHQOFDrbWTjH3tCSpF/oCZV
 eWBrWoYZq4ZvzmiHWPrUsOuw0E1qpGg+QY169+/X8+4NBDglCGVN+d6Z83fb1qEA
 Kcej1kdCvg47xg4l9x+OamlVBkspnG/n/uDX4zkv5Vo0VOmU6kfpA2/zI9UW2UMB
 4rmol7Zw+MW8e5o49dgO9q1bEO2EqJj/7tVTVlhAYy8IS8G8i/FUK5zd2FKoqpzj
 z1hky4Wc1Lof9sIiQfKY
 =reZn
 -----END PGP SIGNATURE-----

Merge tag 'samsung-dt64-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64

Samsung DeviceTree ARM64 update for v4.11:
1. Add bus frequency and voltage scalling on Exynos5433 TM2 device (along with
   necessary bus nodes and Platform Performance Monitoring Unit on Exynos5433).
2. Use macros for pinctrl settings on Exynos5433.
   This contains necessary header with bindings.
3. Minor cleanups in Exynos5433 DTSI and boards using it.
4. Create common DTSI betweem Exynos5433 TM2E and TM2E.
5. Add HDMI/TV to Exynos5433 TM2.

* tag 'samsung-dt64-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: dts: exynos: Enable HDMI/TV path on Exynos5433-TM2
  arm64: dts: exynos: Add HDMI node to Exynos5433
  arm64: dts: exynos: Add DECON_TV node to Exynos5433
  arm64: dts: exynos: Fix addresses in node names on Exynos5433
  arm64: dts: exynos: Make TM2 and TM2E independent from each other
  arm64: dts: exynos: Fix wrong values for ldo23 and ldo25 on TM2/TM2E
  arm64: dts: exynos: Remove unsupported regulator-always-off property from TM2E
  arm64: dts: exynos: Comply to the samsung pinctrl naming convention in TM2
  arm64: dts: exynos: Use macros for pinctrl configuration on Exynos5433
  pinctrl: dt-bindings: samsung: add drive strength macros for Exynos5433
  arm64: dts: exynos: Add support of bus frequency using VDD_INT on Exynos5433 TM2
  arm64: dts: exynos: Add bus nodes using VDD_INT for Exynos5433
  arm64: dts: exynos: Add PPMU node to Exynos5433

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-16 22:31:07 -08:00
Srinivas Kandagatla
3a52153975 arm64: dts: db820c: add support to volume up key
This patch adds support to volume-up key found on the board.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-01-13 13:17:29 -06:00
Ivan T. Ivanov
b4dba94765 arm64: dts: apq8016-sbc: Limit MPP4 high state to 1.8V
96Boards specs require all GPIO signals to be at 1.8V.
Limit MPP4, which is PIN28 on J8, to 1.8V(L5).

Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-01-13 13:17:29 -06:00
Ivan T. Ivanov
f953d999d2 arm64: dts: apq8016-sbc: Add Volume Up key device node
VOL/ZOOM+ button on DB410c is connected to
SoC GPIO 104. Add support for it.

Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-01-13 13:17:28 -06:00
Srinivas Kandagatla
70151ff46c arm64: dts: apq8016-sbc: add support to hdmi audio via adv7533
This patch adds support to hdmi audio via adv7533.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-01-13 13:17:28 -06:00
Srinivas Kandagatla
227c35835a arm64: dts: db820c: fix gpio pinctrl name correctly
Fix typo in node name to reflect the correct pin name.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-01-13 13:17:27 -06:00
Bjorn Andersson
88106096cb ARM: dts: msm8916: Add and enable wcnss node
Add the wcnss remoteproc node the SMD edge and the wcnss ctrl, bluetooth
and wifi nodes specified and enable this on db410c.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-01-13 13:13:07 -06:00
spjoshi@codeaurora.org
702956a187 arm64: dts: msm8996: Add SCM DT node
Add SCM DT node to enable SCM functionality on MSM8996.

Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-01-13 13:13:06 -06:00
Georgi Djakov
a402a354dc arm64: dts: qcom: msm8916: Use fixed factor xo clock
The rpmcc driver is providing the XO clock, which is the parent of almost
all clocks. But during boot, this driver may probe later and leave most of
the clocks without parent. The common clock framework currently reports
invalid rate for orphan clocks and this may confuse drivers.

To resolve this, use fixed clocks registration until we have some support
to deal with the this issue. Removing the generic rpmcc compatible is
enough to switch back to fixed factor XO clock.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-01-13 13:11:57 -06:00
Xing Zheng
8cbb59af7e arm64: dts: rockchip: add rockchip,grf property for RK3399 PMUCRU/CRU
The structure rockchip_clk_provider needs to refer the GRF regmap
in somewhere, if the CRU node has not "rockchip,grf" property,
calling syscon_regmap_lookup_by_phandle will return an invalid GRF
regmap, and the MUXGRF type clock will be not supported.

Therefore, we need to add them.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-13 20:03:15 +01:00
Daniel Kurtz
7fcef92db8 arm64: dts: mt8173: Fix cpu_thermal cooling-maps contributions
According to [0], the contribution field for each cooling-device express
their relative power efficiency. Higher weights express higher power
efficiency.  Weighting is relative such that if each cooling device has a
weight of 1 they are considered equal. This is particularly useful in
heterogeneous systems where two cooling devices may perform the same kind
of compute, but with different efficiency.

[0] Documentation/thermal/power_allocator.txt

According to Mediatek IC designer, the power efficiency ratio between the
LITTLE core cluster (cooling-device cpu0) and big core cluster
(cooling-device cpu1) is around 3:1 (3072:1024).

Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-01-13 16:35:55 +01:00
Bibby Hsieh
fc6634ac0e arm64: dts: mt8173: add mmsel clocks for 4K support
To support HDMI 4K resolution, mmsys need clcok
mm_sel to be 400MHz.

The board .dts file should override the clock rate
property with the higher VENCPLL frequency the board
supports HDMI 4K resolution.

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-01-13 16:31:33 +01:00
Robert Richter
fa5ce3d192 arm64: errata: Provide macro for major and minor cpu revisions
Definition of cpu ranges are hard to read if the cpu variant is not
zero. Provide MIDR_CPU_VAR_REV() macro to describe the full hardware
revision of a cpu including variant and (minor) revision.

Signed-off-by: Robert Richter <rrichter@cavium.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-13 13:15:52 +00:00
Miles Chen
eac8017f0c arm64: mm: use phys_addr_t instead of unsigned long in __map_memblock
Cosmetic change to use phys_addr_t instead of unsigned long for the
return value of __pa_symbol().

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Miles Chen <miles.chen@mediatek.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-13 12:06:29 +00:00
Jintack Lim
488f94d721 KVM: arm64: Access CNTHCTL_EL2 bit fields correctly on VHE systems
Current KVM world switch code is unintentionally setting wrong bits to
CNTHCTL_EL2 when E2H == 1, which may allow guest OS to access physical
timer.  Bit positions of CNTHCTL_EL2 are changing depending on
HCR_EL2.E2H bit.  EL1PCEN and EL1PCTEN are 1st and 0th bits when E2H is
not set, but they are 11th and 10th bits respectively when E2H is set.

In fact, on VHE we only need to set those bits once, not for every world
switch. This is because the host kernel runs in EL2 with HCR_EL2.TGE ==
1, which makes those bits have no effect for the host kernel execution.
So we just set those bits once for guests, and that's it.

Signed-off-by: Jintack Lim <jintack@cs.columbia.edu>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-01-13 11:19:25 +00:00
Shawn Lin
59cf70be5b arm64: dts: rockchip: add aspm-no-l0s for rk3399
Per the discussion of bug fix[1], we now actually
leaves the default clock choice for pcie phy is
derived from 24MHz OSC to guarantee the least BER.
So let's add aspm-no-l0s here and folks could delete
this property from their dts.

[1] https://patchwork.kernel.org/patch/9470519/
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-13 12:03:55 +01:00
Ard Biesheuvel
41c066f2c4 arm64: assembler: make adr_l work in modules under KASLR
When CONFIG_RANDOMIZE_MODULE_REGION_FULL=y, the offset between loaded
modules and the core kernel may exceed 4 GB, putting symbols exported
by the core kernel out of the reach of the ordinary adrp/add instruction
pairs used to generate relative symbol references. So make the adr_l
macro emit a movz/movk sequence instead when executing in module context.

While at it, remove the pointless special case for the stack pointer.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-01-12 18:10:52 +00:00
Suzuki K Poulose
f92f5ce01e arm64: Advertise support for Rounding double multiply instructions
ARM v8.1 extensions include support for rounding double multiply
add/subtract instructions to the A64 SIMD instructions set. Let
the userspace know about it via a HWCAP bit.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-12 17:19:06 +00:00
Ard Biesheuvel
1abee99eaf crypto: arm64/aes - reimplement bit-sliced ARM/NEON implementation for arm64
This is a reimplementation of the NEON version of the bit-sliced AES
algorithm. This code is heavily based on Andy Polyakov's OpenSSL version
for ARM, which is also available in the kernel. This is an alternative for
the existing NEON implementation for arm64 authored by me, which suffers
from poor performance due to its reliance on the pathologically slow four
register variant of the tbl/tbx NEON instruction.

This version is about ~30% (*) faster than the generic C code, but only in
cases where the input can be 8x interleaved (this is a fundamental property
of bit slicing). For this reason, only the chaining modes ECB, XTS and CTR
are implemented. (The significance of ECB is that it could potentially be
used by other chaining modes)

* Measured on Cortex-A57. Note that this is still an order of magnitude
  slower than the implementations that use the dedicated AES instructions
  introduced in ARMv8, but those are part of an optional extension, and so
  it is good to have a fallback.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-01-13 00:26:51 +08:00
Ard Biesheuvel
bed593c0e8 crypto: arm64/aes - add scalar implementation
This adds a scalar implementation of AES, based on the precomputed tables
that are exposed by the generic AES code. Since rotates are cheap on arm64,
this implementation only uses the 4 core tables (of 1 KB each), and avoids
the prerotated ones, reducing the D-cache footprint by 75%.

On Cortex-A57, this code manages 13.0 cycles per byte, which is ~34% faster
than the generic C code. (Note that this is still >13x slower than the code
that uses the optional ARMv8 Crypto Extensions, which manages <1 cycles per
byte.)

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-01-13 00:26:49 +08:00
Ard Biesheuvel
293614ce3e crypto: arm64/aes-blk - expose AES-CTR as synchronous cipher as well
In addition to wrapping the AES-CTR cipher into the async SIMD wrapper,
which exposes it as an async skcipher that defers processing to process
context, expose our AES-CTR implementation directly as a synchronous cipher
as well, but with a lower priority.

This makes the AES-CTR transform usable in places where synchronous
transforms are required, such as the MAC802.11 encryption code, which
executes in sotfirq context, where SIMD processing is allowed on arm64.
Users of the async transform will keep the existing behavior.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-01-13 00:26:49 +08:00
Ard Biesheuvel
b7171ce9eb crypto: arm64/chacha20 - implement NEON version based on SSE3 code
This is a straight port to arm64/NEON of the x86 SSE3 implementation
of the ChaCha20 stream cipher. It uses the new skcipher walksize
attribute to process the input in strides of 4x the block size.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-01-13 00:26:48 +08:00
Takeshi Kihara
7f332fc1f0 arm64: Add support for DMA_ATTR_SKIP_CPU_SYNC attribute to swiotlb
This patch adds support for DMA_ATTR_SKIP_CPU_SYNC attribute for
dma_{un}map_{page,sg} functions family to swiotlb.

DMA_ATTR_SKIP_CPU_SYNC allows platform code to skip synchronization of
the CPU cache for the given buffer assuming that it has been already
transferred to 'device' domain.

Ported from IOMMU .{un}map_{sg,page} ops.

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-12 15:34:15 +00:00
Laura Abbott
ec6d06efb0 arm64: Add support for CONFIG_DEBUG_VIRTUAL
x86 has an option CONFIG_DEBUG_VIRTUAL to do additional checks
on virt_to_phys calls. The goal is to catch users who are calling
virt_to_phys on non-linear addresses immediately. This inclues callers
using virt_to_phys on image addresses instead of __pa_symbol. As features
such as CONFIG_VMAP_STACK get enabled for arm64, this becomes increasingly
important. Add checks to catch bad virt_to_phys usage.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Laura Abbott <labbott@redhat.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-12 15:05:39 +00:00
Laura Abbott
2077be6783 arm64: Use __pa_symbol for kernel symbols
__pa_symbol is technically the marcro that should be used for kernel
symbols. Switch to this as a pre-requisite for DEBUG_VIRTUAL which
will do bounds checking.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Laura Abbott <labbott@redhat.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-12 15:05:39 +00:00
Laura Abbott
869dcfd10d arm64: Add cast for virt_to_pfn
virt_to_pfn lacks a cast at the top level. Don't rely on __virt_to_phys
and explicitly cast to unsigned long.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Laura Abbott <labbott@redhat.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-12 15:05:39 +00:00
Laura Abbott
9e22eb616f arm64: Move some macros under #ifndef __ASSEMBLY__
Several macros for various x_to_y exist outside the bounds of an
__ASSEMBLY__ guard. Move them in preparation for support for
CONFIG_DEBUG_VIRTUAL.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Laura Abbott <labbott@redhat.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-12 15:05:39 +00:00
Suzuki K Poulose
4aa8a472c3 arm64: Documentation - Expose CPU feature registers
Documentation for the infrastructure to expose CPU feature
register by emulating MRS.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Dave Martin <dave.martin@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-12 12:31:31 +00:00
Suzuki K Poulose
77c97b4ee2 arm64: cpufeature: Expose CPUID registers by emulation
This patch adds the hook for emulating MRS instruction to
export the 'user visible' value of supported system registers.
We emulate only the following id space for system registers:

 Op0=3, Op1=0, CRn=0, CRm=[0, 4-7]

The rest will fall back to SIGILL. This capability is also
advertised via a new HWCAP_CPUID.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
[will: add missing static keyword to enable_mrs_emulation]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-12 12:31:09 +00:00
Andrzej Hajda
e4e3811332 arm64: dts: exynos: Enable HDMI/TV path on Exynos5433-TM2
TV path consist of following interconnected components:
- DECON_TV - display controller,
- HDMI - video signal converter RGB / HDMI,
- MHL - video signal converter HDMI / MHL,
- DDC - i2c slave device for EDID reading (on hsi2c_11 bus).

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-01-11 18:20:28 +02:00
Andrzej Hajda
cb872bd936 arm64: dts: exynos: Add HDMI node to Exynos5433
HDMI converts RGB/I80 signal from DECON_TV to HDMI/TMDS video stream.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-01-11 18:20:21 +02:00
Andrzej Hajda
e80deee0a5 arm64: dts: exynos: Add DECON_TV node to Exynos5433
DECON_TV is 2nd display controller on Exynos5433, used in HDMI path
or 2nd DSI path.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-01-11 18:20:11 +02:00