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arm64: tegra: Device tree changes for v4.11-rc1
This contains three patches that reintroduce symbolic identifiers for clocks, resets and mailboxes. These had been converted to literals in the v4.10 release to avoid complicated dependencies between branches. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAliLECQTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoTa2EACD9/bu6s6tJopSAPBxKCI1voclTsXQ du1TCe2PO6Vz4CFkmpCo8mAsAexr+pQ6b8yX/SVOr/8A5N1J7TtQTUfK7Mzggeh+ hI07xNDcE6LskOsEiLSApBpTwbCbpju7efIQWlnYByznfElnfLzuVUaXwezZTdG4 rdXl2tCJOAuHwaA0dhlgj3YerVnDADSqZGMAa8tfpp0tN3P1/H9k7Q8Ze8Xcm2ag DZAo5XxL5XqcvEz1Rt8pTBHdtkGKeIO+3P6az2sCHMzqvB1Ejpa6sx6WIEQvJqxX VuTX27fFepWhEHfQMktLobxYl9zfsP/XMzlAve4EDrtJMmNjZ3glPNOuoEzicgsQ QpnYiF1HR/Q7BeZpGHDpSd3skTgtLvQZq9+CSQrOkXmhTnoHea5e1vHw6mR5Xi9V jvitE7bLSW2cWxHZ51QNDygobF4Gqmk9DFuKBDv22QYqh2d67J5TqpSJ2xURDH58 GK5g32LAyoX8xehA1I+insyObKxe6QWOAg1Ukt1S0BgUHQhwBx/qh0ZVv0ktwcyF fYcnJmvvAHiaYJvePoy0aBRN01JCnYwzbKlM+KjfT6juuSiPqaJNVErurTYc2Gfz 7/lT2EmhNbFnveflZGODpWTuygJZkmoGxADfyzP1D4U+6P35yaWVRTiGha4FWMEn spltHyMXJ4tBpQ== =eeee -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.11-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64 arm64: tegra: Device tree changes for v4.11-rc1 This contains three patches that reintroduce symbolic identifiers for clocks, resets and mailboxes. These had been converted to literals in the v4.10 release to avoid complicated dependencies between branches. * tag 'tegra-for-4.11-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Use symbolic reset identifiers arm64: tegra: Use symbolic clock identifiers arm64: tegra: Use symbolic HSP identifiers Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
4c8cb9c40a
@ -1,5 +1,8 @@
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#include <dt-bindings/clock/tegra186-clock.h>
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#include <dt-bindings/gpio/tegra186-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/tegra186-hsp.h>
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#include <dt-bindings/reset/tegra186-reset.h>
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/ {
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compatible = "nvidia,tegra186";
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@ -29,9 +32,9 @@ uarta: serial@3100000 {
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reg = <0x0 0x03100000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp 55>;
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clocks = <&bpmp TEGRA186_CLK_UARTA>;
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clock-names = "serial";
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resets = <&bpmp 47>;
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resets = <&bpmp TEGRA186_RESET_UARTA>;
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reset-names = "serial";
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status = "disabled";
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};
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@ -41,9 +44,9 @@ uartb: serial@3110000 {
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reg = <0x0 0x03110000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp 56>;
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clocks = <&bpmp TEGRA186_CLK_UARTB>;
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clock-names = "serial";
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resets = <&bpmp 48>;
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resets = <&bpmp TEGRA186_RESET_UARTB>;
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reset-names = "serial";
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status = "disabled";
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};
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@ -53,9 +56,9 @@ uartd: serial@3130000 {
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reg = <0x0 0x03130000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp 77>;
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clocks = <&bpmp TEGRA186_CLK_UARTD>;
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clock-names = "serial";
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resets = <&bpmp 50>;
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resets = <&bpmp TEGRA186_RESET_UARTD>;
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reset-names = "serial";
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status = "disabled";
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};
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@ -65,9 +68,9 @@ uarte: serial@3140000 {
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reg = <0x0 0x03140000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp 194>;
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clocks = <&bpmp TEGRA186_CLK_UARTE>;
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clock-names = "serial";
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resets = <&bpmp 132>;
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resets = <&bpmp TEGRA186_RESET_UARTE>;
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reset-names = "serial";
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status = "disabled";
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};
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@ -77,9 +80,9 @@ uartf: serial@3150000 {
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reg = <0x0 0x03150000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp 195>;
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clocks = <&bpmp TEGRA186_CLK_UARTF>;
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clock-names = "serial";
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resets = <&bpmp 111>;
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resets = <&bpmp TEGRA186_RESET_UARTF>;
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reset-names = "serial";
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status = "disabled";
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};
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@ -90,9 +93,9 @@ gen1_i2c: i2c@3160000 {
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp 47>;
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clocks = <&bpmp TEGRA186_CLK_I2C1>;
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clock-names = "div-clk";
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resets = <&bpmp 19>;
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resets = <&bpmp TEGRA186_RESET_I2C1>;
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reset-names = "i2c";
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status = "disabled";
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};
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@ -103,9 +106,9 @@ cam_i2c: i2c@3180000 {
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp 75>;
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clocks = <&bpmp TEGRA186_CLK_I2C3>;
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clock-names = "div-clk";
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resets = <&bpmp 21>;
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resets = <&bpmp TEGRA186_RESET_I2C3>;
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reset-names = "i2c";
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status = "disabled";
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};
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@ -117,9 +120,9 @@ dp_aux_ch1_i2c: i2c@3190000 {
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp 86>;
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clocks = <&bpmp TEGRA186_CLK_I2C4>;
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clock-names = "div-clk";
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resets = <&bpmp 22>;
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resets = <&bpmp TEGRA186_RESET_I2C4>;
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reset-names = "i2c";
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status = "disabled";
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};
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@ -131,9 +134,9 @@ pwr_i2c: i2c@31a0000 {
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp 48>;
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clocks = <&bpmp TEGRA186_CLK_I2C5>;
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clock-names = "div-clk";
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resets = <&bpmp 23>;
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resets = <&bpmp TEGRA186_RESET_I2C5>;
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reset-names = "i2c";
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status = "disabled";
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};
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@ -145,9 +148,9 @@ dp_aux_ch0_i2c: i2c@31b0000 {
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp 125>;
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clocks = <&bpmp TEGRA186_CLK_I2C6>;
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clock-names = "div-clk";
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resets = <&bpmp 24>;
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resets = <&bpmp TEGRA186_RESET_I2C6>;
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reset-names = "i2c";
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status = "disabled";
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};
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@ -158,9 +161,9 @@ gen7_i2c: i2c@31c0000 {
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp 182>;
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clocks = <&bpmp TEGRA186_CLK_I2C7>;
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clock-names = "div-clk";
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resets = <&bpmp 81>;
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resets = <&bpmp TEGRA186_RESET_I2C7>;
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reset-names = "i2c";
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status = "disabled";
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};
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@ -171,9 +174,9 @@ gen9_i2c: i2c@31e0000 {
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp 183>;
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clocks = <&bpmp TEGRA186_CLK_I2C9>;
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clock-names = "div-clk";
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resets = <&bpmp 83>;
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resets = <&bpmp TEGRA186_RESET_I2C9>;
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reset-names = "i2c";
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status = "disabled";
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};
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@ -182,9 +185,9 @@ sdmmc1: sdhci@3400000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x03400000 0x0 0x10000>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp 52>;
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clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
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clock-names = "sdhci";
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resets = <&bpmp 33>;
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resets = <&bpmp TEGRA186_RESET_SDMMC1>;
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reset-names = "sdhci";
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status = "disabled";
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};
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@ -193,9 +196,9 @@ sdmmc2: sdhci@3420000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x03420000 0x0 0x10000>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp 53>;
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clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
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clock-names = "sdhci";
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resets = <&bpmp 34>;
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resets = <&bpmp TEGRA186_RESET_SDMMC2>;
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reset-names = "sdhci";
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status = "disabled";
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};
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@ -204,9 +207,9 @@ sdmmc3: sdhci@3440000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x03440000 0x0 0x10000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp 76>;
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clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
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clock-names = "sdhci";
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resets = <&bpmp 35>;
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resets = <&bpmp TEGRA186_RESET_SDMMC3>;
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reset-names = "sdhci";
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status = "disabled";
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};
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@ -215,9 +218,9 @@ sdmmc4: sdhci@3460000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x03460000 0x0 0x10000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp 54>;
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clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
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clock-names = "sdhci";
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resets = <&bpmp 36>;
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resets = <&bpmp TEGRA186_RESET_SDMMC4>;
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reset-names = "sdhci";
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status = "disabled";
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};
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@ -248,9 +251,9 @@ gen2_i2c: i2c@c240000 {
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp 218>;
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clocks = <&bpmp TEGRA186_CLK_I2C2>;
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clock-names = "div-clk";
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resets = <&bpmp 20>;
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resets = <&bpmp TEGRA186_RESET_I2C2>;
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reset-names = "i2c";
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status = "disabled";
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};
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@ -261,9 +264,9 @@ gen8_i2c: i2c@c250000 {
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp 219>;
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clocks = <&bpmp TEGRA186_CLK_I2C8>;
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clock-names = "div-clk";
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resets = <&bpmp 82>;
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resets = <&bpmp TEGRA186_RESET_I2C8>;
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reset-names = "i2c";
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status = "disabled";
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};
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@ -273,9 +276,9 @@ uartc: serial@c280000 {
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reg = <0x0 0x0c280000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp 215>;
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clocks = <&bpmp TEGRA186_CLK_UARTC>;
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clock-names = "serial";
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resets = <&bpmp 49>;
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resets = <&bpmp TEGRA186_RESET_UARTC>;
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reset-names = "serial";
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status = "disabled";
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};
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@ -285,9 +288,9 @@ uartg: serial@c290000 {
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reg = <0x0 0x0c290000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp 216>;
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clocks = <&bpmp TEGRA186_CLK_UARTG>;
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clock-names = "serial";
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resets = <&bpmp 112>;
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resets = <&bpmp TEGRA186_RESET_UARTG>;
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reset-names = "serial";
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status = "disabled";
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};
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@ -369,7 +372,8 @@ cpu@5 {
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bpmp: bpmp {
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compatible = "nvidia,tegra186-bpmp";
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mboxes = <&hsp_top0 0 19>;
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mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
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TEGRA_HSP_DB_MASTER_BPMP>;
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shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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