Link the ARM GIC to the INTC-AP module clock, and add it to the SYSC
"always-on" PM Domain, so it can be power managed using that clock.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This went unnoticed as the sata_rcar driver doesn't support Runtime PM
yet, but manages module clocks manually.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Exynos5433 LPASS module requires some clocks for proper operation with
power domain.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
All dts files for the sunxi platform have been switched to the generic
pinconf bindings. As a result, the sunxi specific pinctrl macros are
no longer used.
Remove the #include entry with the following command:
sed -i -e '/pinctrl\/sun4i-a10.h/D' \
arch/arm64/boot/dts/allwinner/*.dts?
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add initial dtsi file to support Hisilicon Hi3660 SoC with
support of Octal core CPUs in two clusters(4 * A53 & 4 * A73).
Also add dts file to support HiKey960 development board which
based on Hi3660 SoC.
The output console is earlycon "earlycon=pl011,0xfdf05000".
And the con_init uart5 with a fixed clock, which already
configured at bootloader.
When clock is available, the uart5 will be modified.
Tested on HiKey960 Board.
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Now that the corresponding device tree binding include has been merged,
convert the DTS files to use symbolic names instead of numeric ones.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Now that the corresponding device tree binding include has been merged,
convert the DTS files to use symbolic names instead of numeric ones.
Signed-off-by: Thierry Reding <treding@nvidia.com>
LDO7 regulator beside DSI and HDMI provides power for core blocks in Exynos
5433 SoC. Disabling it causes serious current leak - about 200mA.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Since the GXL family has S905X and S905D SoCs, we're keeping the SoC
name in the DTS filename for clarity. Rename this file accordingly to
be consistent with the rest of the GXL DTS files.
Cc: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Adds support for the WeTek Hub and Play2 boards.
The Hub is an extremely small IPTv Set-Top-Box and the Play2 is a more
traditionnal Satellite or Terrestrial and IPTv Set-Top-Box.
Both are based on the p200 Reference Design and out-of-tree support is
based on LibreELEC kernel at [1].
[1] https://github.com/wetek-enigma/linux-amlogic
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Ultra HD modes requires clock ticking at increased rate.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
The LD11 SoC is equipped with SD-ctrl (0x59810000) as well as
MIO-ctrl (0x5b3e0000). The SD-ctrl block on this SoC has just
one register for controlling RST_n pin of the eMMC device.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
As per Exynos7 datasheet FSYS1 pinctrl block does not support drive
strength value of 0x3. This patch fixes this and update the correct
drive strength for sd0_xxx pin definitions.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Common definition for I2S, PMC, SPDIF buses should not define any pull
control for the individual pins. Correct this by changing samsung,pin-pud
property to EXYNOS_PIN_PULL_NONE like it is defined for other Exynos SoCs.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Add a cut-down version of the DTS file for the community board
MACCHIATOBin from SolidRun based on Marvell Armada 8040 SoC to suit
the current mainlined Armada 8040 state.
This brings support for mainly SATA, SPI flash and UART. The USB
descriptions are included but are not tested in this form due to the
lack of mainline GPIO.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Acked-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
In order to keep consistency naming with the Nexbox A1 DTS file, remove the
S912 SoC name in the GXM DT files.
Suggested-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
4.11, please pull the following changes:
- Jon adds Device Tree nodes for the GICv2m and PAXB/PAXC PCIe interfaces on
the Northstar 2 SoCs, he also enables PAXC on the Northstar 2 SVK reference
board. He also updates the reserved memory entry for the Nitro firmware,
required to get the on-chip NICs to work. Finally he adds support for the
BCM958712DxXMC reference board which is a subset of existing boards.
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJYfsSQAAoJEIfQlpxEBwcEGDUP+gLIXb7EJ7rzNOYskYuf5blU
Uidfec5wbdu8Tnm4KbqWxopKdfvg13tx6YTwVjmtVwNP06iG9g9ytC3XA/YTYbLw
Gs8S0QhMpPn9mJ94ix0+DUT8NwTFLxPS/veCqpQLG/usOkXkt8xR36DfA63C+qK/
s6G87AZklsjUtkJn06FtrtvdyxRDHsl7Tj/7U+J9/mGoWdmZDbtooMP6GXDMS34N
XDMU1L18Kr74R5YUyTotzu2D0y/CG1edSTGPpHbrVKnI8YGTkLHyL9V1anbGS7v0
z+E+K6Lbe4M0xBqDVH/fOejwOxg30qDc4t9SDjMV813txZChwyVhNswNH6Nnn+3I
zcN5bRs9fT71B7H2Q+zkqRDf0nLx6fJt3rvQ/iPHOHil3wgpa1yckHnAi11BE1gp
hBEZPZkMw4ZPjtPc+CUoE9vWRzdJtoGYlE6dOxzz4UbP9QYmU0ai7F7OhxsQ+lKM
LpVM7jAf+E4lRBsOSkKuV/3uDzLqwIKdEBqjYaSe83MIO1uC1XIgN2lHU4Q3BITx
nyYdiJymr2AwXjyi8W7nN9neAmDiNlfi7fPZvYy0crd8GWn3uoROBLR7NoL+alPo
eBjiKJe6WJen+0VQR67a17kZ7WCkqCR0QUrXZTl8yVdzDZWaPHLXcCR8dulYwvMT
zvT+oFf7yA+DB3bCykd5
=JBHv
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-4.11/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64
This pull request contains Broadcom ARM64-based SoC Device Tree changes for
4.11, please pull the following changes:
- Jon adds Device Tree nodes for the GICv2m and PAXB/PAXC PCIe interfaces on
the Northstar 2 SoCs, he also enables PAXC on the Northstar 2 SVK reference
board. He also updates the reserved memory entry for the Nitro firmware,
required to get the on-chip NICs to work. Finally he adds support for the
BCM958712DxXMC reference board which is a subset of existing boards.
* tag 'arm-soc/for-4.11/devicetree-arm64' of http://github.com/Broadcom/stblinux:
arm64: dts: NS2: add support for XMC form factor
arm64: dts: NS2: reserve memory for Nitro firmware
arm64: dts: NS2: enable PAXC on NS2 SVK
arm64: dts: NS2: enable GICv2m for PAXB/PAXC interfaces
Signed-off-by: Olof Johansson <olof@lixom.net>
1. Addition of Coresight support on Juno R1 and R2 variants
2. Addition of STM(System Trace Macrocell) support on all Juno variants
3. Removed incorrect nesting of dtsi files
4. Removed untested USB hub only available on initial Juno R0 motherboard
5. Added ETR SMMU power domain and dma-ranges property
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCAAGBQJYf3YFAAoJEABBurwxfuKYq2YP/3Yknoe0K+h6c0N7yyQVWsbd
5qbY3xcbQDh7JsDz2AuTeRJtgP4V6cUqe9LbNF4Z0myOmrNSLhPNLKxm9OCsbxty
bL7rSIXjL3dPCm4MENFw3yNzgIukZGTyFrtDMbYcqxXlSo5JMWEn/yztBeP1onmn
aFiy1FBRtkuAe5gVMAwIz1oK/0eCBqlKfa9SXq9dmCXKv5fuq51aMr5dlAq8Q5ja
RvxDaNvh8P4Vh/DVZrRBAmhA5uw3dovgAQiSIg56TermEk64UOGksv1pGE4ycMFU
TOQ5YuxqT2J7HLUy2TqwZhaNcblGlG98fpqLCMWC1r4GkO0KwGimnXTGSiZxJIMk
0/quwCO6PguHacCGV+PUV7HH3WriH0REjbKEuZ0louYBtjHj1rvZJLC0fO6Mt2i7
EDdVqiPwfAAbHo6zrK1Axz1Q7FTEYRcvaZV5QXmz9rLjUFMFtzHg7r+L21TAtxoq
Q9l589/vO5f8t9B6notXV1hgg0RRI+jGH8KeDO2lvNfpXgGC3BkwnWcJlv2AkhgG
+TrpOtkXbdsKee6G0mW/W1vtooDh/w7IKU7ncaPp+9Sq/uvkKYnDS9ubfAkgIjwT
turauXHIeFS6AID+Y+O2/q/hDve0eNXKFV6CheZHgDKEXAp+LCQm7Wtd8HYNuG3S
FBnUYKVEswLaFDUUv8Wk
=VeiR
-----END PGP SIGNATURE-----
Merge tag 'juno-updates-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt64
ARMv8 Vexpress/Juno DT updates for v4.11
1. Addition of Coresight support on Juno R1 and R2 variants
2. Addition of STM(System Trace Macrocell) support on all Juno variants
3. Removed incorrect nesting of dtsi files
4. Removed untested USB hub only available on initial Juno R0 motherboard
5. Added ETR SMMU power domain and dma-ranges property
* tag 'juno-updates-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: remove motherboard USB node
arm64: dts: juno: add ETR SMMU power domain
arm64: dts: juno: add dma-ranges property
arm64: dts: juno: add missing CoreSight STM component
arm64: dts: juno: add CoreSight support for Juno r1/r2 variants
arm64: dts: juno: refactor CoreSight support on Juno r0
arm64: dts: juno: remove dtsi nesting inside tree structure
Signed-off-by: Olof Johansson <olof@lixom.net>
Add pinctrl nodes for HDMI HPD and DDC pins modes for Amlogic Meson GXL
and GXBB SoCs.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
There is one blue LED on the front of the device. Keep it lit and
configure it as panic indicator.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This adds pinctrl group nodes for the CTS and RTS pins of each serial
controller. This makes it possible to enable the CTS and RTS pins which
are controlled by the serial controller hardware (through the meson_uart
driver).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This adds the missing node for the uart_AO_B port to the meson-gx.dtsi
(as this is supported by GXBB, GXL and GXM) along with the required
pinctrl pins. This is required as some boards are using it (the boards
from the Khadas VIM series for example have it exposed on the pin
headers).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The "samsung,exynos5433-mipi-video-phy" and "samsung,exynos5250-dwusb3"
DT bindings don't specify a reg property for these nodes, so having a
unit name leads to the following DTC warnings:
Node /soc/video-phy@105c0710 has a unit name, but no reg property
Node /soc/usb@15400000 has a unit name, but no reg property
Node /soc/usb@15a00000 has a unit name, but no reg property
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
The first batch of Juno boards included a discrete USB controller chip
as a contingency in case of issues with the USB 2.0 IP integrated into
the SoC. As it turned out, the latter was fine, and to the best of my
knowledge the motherboard USB was never even brought up and validated.
Since this also isn't present on later boards, and uses a compatible
string undocumented and unmatched by any driver in the kernel, let's
just tidy it away for ever to avoid any confusion.
Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
It is not at all clear from the documentation, but straightforward to
determine in practice, that the ETR SMMU is actually in the DEBUGSYS
power domain. Add that to the DT so that anyone brave enough to enable
said SMMU doesn't experience a system lockup on boot, especially a
sneaky one which goes away as soon as you connect an external debugger
to have a look at where it's stuck (thus powering up DEBUGSYS by other
means and allowing it to make progress again before actually halting...)
Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
The interconnects around Juno have a 40-bit address width, and DMA
masters have no restrictions beyond their own individual limitations.
Describe this to ensure that DT-based DMA masks get set up correctly
for all devices capable of 40-bit addressing.
Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
This patch adds the missing CoreSight STM component definition to the
device tree of all the juno variants(r0,r1,r2)
STM component is connected to different funnels depending on Juno
platform variant.
Reviewed-and-tested-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mike Leach <mike.leach@linaro.org>
[sudeep.holla@arm.com: minor changelog update and reorganising the STM
node back into juno-base.dtsi to avoid duplication]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
The CoreSight support added for Juno is valid for only Juno r0.
The Juno r1 and r2 variants have additional components and alternative
connection routes between trace source and sinks.
This patch builds on top of the existing r0 support and extends it to
Juno r1/r2 variants.
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mike Leach <mike.leach@linaro.org>
[sudeep.holla@arm.com: minor changelog update and major reorganisation of
the common coresight components back into juno-base.dtsi to avoid
duplication, also renamed funnel node names]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Currently the Coresight components are supported only on Juno r0
variant. In preparation to add support to Juno r1/r2 variants, this
patch refactors the existing coresight device nodes so that r1/r2
support can be added easily.
It also cleans up some of the device node names which were previously
named so as they were confused as the labels rather than the node names.
Reviewed-and-tested-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Currently juno-clock.dtsi and juno-base.dtsi are nested badly inside
the device tree structure. It's generally good practice to ensure that
individual dtsi stand by themselves at the top of the file.
This patch removes the nesting of the above mentioned dtsi files and
makes them independent.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
The current hardware is not able to run with all cores enabled at a
cluster frequency superior at 1536MHz.
But the currently shipped u-boot for the platform still reports an OPP
table with possible DVFS frequency up to 2GHz, and will not change since
the off-tree linux tree supports limiting the OPPs with a kernel parameter.
A recent u-boot change reports the boot-time DVFS around 100MHz and
the default performance cpufreq governor sets the maximum frequency.
Previous version of u-boot reported to be already at the max OPP and
left the OPP as is.
Nevertheless, other governors like ondemand could setup the max frequency
and make the system crash.
This patch disables the DVFS clock and disables cpufreq.
Fixes: 70db166a2b ("ARM64: dts: meson-gxbb: Add SCPI with cpufreq & sensors Nodes")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
- Correct license text which was mangled when switching to dual license
- Add SPI and I2C nodes on Armada 3700(driver support had been already
merged)
- Add support for the ethernet switch on the EspressoBin board (driver
support not yet merged)
-----BEGIN PGP SIGNATURE-----
iIEEABECAEEWIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWHkJzyMcZ3JlZ29yeS5j
bGVtZW50QGZyZWUtZWxlY3Ryb25zLmNvbQAKCRALBhiOFHI71S01AKCYMJtp3ZYd
nWFez/9S2sUDbmEQRwCgiwEJ4cDIz68s5+EXJE4nXAKlhrg=
=HIbH
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt64-4.11-1' of git://git.infradead.org/linux-mvebu into next/dt64
mvebu dt64 for 4.11 (part 1)
- Correct license text which was mangled when switching to dual license
- Add SPI and I2C nodes on Armada 3700(driver support had been already
merged)
- Add support for the ethernet switch on the EspressoBin board (driver
support not yet merged)
* tag 'mvebu-dt64-4.11-1' of git://git.infradead.org/linux-mvebu:
ARM64: dts: marvell: Correct license text
arm64: dts: marvell: Add I2C definitions for the Armada 3700
arm64: dts: marvell: Enable spi0 on the board Armada-3720-db
arm64: dts: marvell: Add definition of SPI controller for Armada 3700
arm64: dts: marvell: Add ethernet switch definition for the ESPRESSObin
Signed-off-by: Olof Johansson <olof@lixom.net>
1. Add bus frequency and voltage scalling on Exynos5433 TM2 device (along with
necessary bus nodes and Platform Performance Monitoring Unit on Exynos5433).
2. Use macros for pinctrl settings on Exynos5433.
This contains necessary header with bindings.
3. Minor cleanups in Exynos5433 DTSI and boards using it.
4. Create common DTSI betweem Exynos5433 TM2E and TM2E.
5. Add HDMI/TV to Exynos5433 TM2.
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJYeO01AAoJEME3ZuaGi4PXX7QP/0wlZmoUeBiAGuVDsOUqS5jT
FQd+lC4r1croSn8oFMKx6Ta8LxwI8XjmuCOvRjBxBtNxzq4wTCABlVOexWjAHCMz
KhYWcTBGIj+8Nk6BkBg8ga5iQAqQY6JhKKRBg0xbe8XqlkMThapJ3C90A4oWTeqm
D9SERXJzeJiBr2dqVORxt3d/XtLXXKEw+3/qK9iOu4uAZE7NECUD1EIOM6gGXkLM
55hOw7Qzh7g4L9umqVCj37gNK5nu4HLvvVA0FasMi6CL+EuHs5im9NOP3naN152f
/W4xPRS6hVYzvueWHILBmaxNbwYMthJ34gXIdMg4td/nO/nVRMCplnsjbm+1rQDQ
UoasRanobu+s+5nzRGybkM5Ni8QHZ/CsXK8DtSSlPC3tPMs5GywGIEfXqHqJzabs
WlmhD68LWFzh2Og8X2KzB+5Pkmvp3HuUVLqPtsPpjnHQOFDrbWTjH3tCSpF/oCZV
eWBrWoYZq4ZvzmiHWPrUsOuw0E1qpGg+QY169+/X8+4NBDglCGVN+d6Z83fb1qEA
Kcej1kdCvg47xg4l9x+OamlVBkspnG/n/uDX4zkv5Vo0VOmU6kfpA2/zI9UW2UMB
4rmol7Zw+MW8e5o49dgO9q1bEO2EqJj/7tVTVlhAYy8IS8G8i/FUK5zd2FKoqpzj
z1hky4Wc1Lof9sIiQfKY
=reZn
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt64-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64
Samsung DeviceTree ARM64 update for v4.11:
1. Add bus frequency and voltage scalling on Exynos5433 TM2 device (along with
necessary bus nodes and Platform Performance Monitoring Unit on Exynos5433).
2. Use macros for pinctrl settings on Exynos5433.
This contains necessary header with bindings.
3. Minor cleanups in Exynos5433 DTSI and boards using it.
4. Create common DTSI betweem Exynos5433 TM2E and TM2E.
5. Add HDMI/TV to Exynos5433 TM2.
* tag 'samsung-dt64-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Enable HDMI/TV path on Exynos5433-TM2
arm64: dts: exynos: Add HDMI node to Exynos5433
arm64: dts: exynos: Add DECON_TV node to Exynos5433
arm64: dts: exynos: Fix addresses in node names on Exynos5433
arm64: dts: exynos: Make TM2 and TM2E independent from each other
arm64: dts: exynos: Fix wrong values for ldo23 and ldo25 on TM2/TM2E
arm64: dts: exynos: Remove unsupported regulator-always-off property from TM2E
arm64: dts: exynos: Comply to the samsung pinctrl naming convention in TM2
arm64: dts: exynos: Use macros for pinctrl configuration on Exynos5433
pinctrl: dt-bindings: samsung: add drive strength macros for Exynos5433
arm64: dts: exynos: Add support of bus frequency using VDD_INT on Exynos5433 TM2
arm64: dts: exynos: Add bus nodes using VDD_INT for Exynos5433
arm64: dts: exynos: Add PPMU node to Exynos5433
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds support to volume-up key found on the board.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
96Boards specs require all GPIO signals to be at 1.8V.
Limit MPP4, which is PIN28 on J8, to 1.8V(L5).
Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
VOL/ZOOM+ button on DB410c is connected to
SoC GPIO 104. Add support for it.
Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds support to hdmi audio via adv7533.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Fix typo in node name to reflect the correct pin name.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add the wcnss remoteproc node the SMD edge and the wcnss ctrl, bluetooth
and wifi nodes specified and enable this on db410c.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The rpmcc driver is providing the XO clock, which is the parent of almost
all clocks. But during boot, this driver may probe later and leave most of
the clocks without parent. The common clock framework currently reports
invalid rate for orphan clocks and this may confuse drivers.
To resolve this, use fixed clocks registration until we have some support
to deal with the this issue. Removing the generic rpmcc compatible is
enough to switch back to fixed factor XO clock.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The structure rockchip_clk_provider needs to refer the GRF regmap
in somewhere, if the CRU node has not "rockchip,grf" property,
calling syscon_regmap_lookup_by_phandle will return an invalid GRF
regmap, and the MUXGRF type clock will be not supported.
Therefore, we need to add them.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
According to [0], the contribution field for each cooling-device express
their relative power efficiency. Higher weights express higher power
efficiency. Weighting is relative such that if each cooling device has a
weight of 1 they are considered equal. This is particularly useful in
heterogeneous systems where two cooling devices may perform the same kind
of compute, but with different efficiency.
[0] Documentation/thermal/power_allocator.txt
According to Mediatek IC designer, the power efficiency ratio between the
LITTLE core cluster (cooling-device cpu0) and big core cluster
(cooling-device cpu1) is around 3:1 (3072:1024).
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
To support HDMI 4K resolution, mmsys need clcok
mm_sel to be 400MHz.
The board .dts file should override the clock rate
property with the higher VENCPLL frequency the board
supports HDMI 4K resolution.
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Per the discussion of bug fix[1], we now actually
leaves the default clock choice for pcie phy is
derived from 24MHz OSC to guarantee the least BER.
So let's add aspm-no-l0s here and folks could delete
this property from their dts.
[1] https://patchwork.kernel.org/patch/9470519/
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
HDMI converts RGB/I80 signal from DECON_TV to HDMI/TMDS video stream.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
DECON_TV is 2nd display controller on Exynos5433, used in HDMI path
or 2nd DSI path.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This adds the SCPI DVFS clock index and configures the CPU cores
accordingly.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
SCPI and SRAM are identical on GXBB and GXL. Moving the corresponding
nodes to meson-gx adds support for the thermal sensor on GXL based
devices.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
[khilman: add scpi_clocks label]
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Address should not contain 0x prefix.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
* Add PWM, and sound MIX and CTU support to r8a7795 SoC
* Add CAN, CAN FD and all MSIOF nodes to r8a7796 SoC
* Use Gen 3 fallback binding for i2c, msiof, PCIE and USB2 phy
* Enable Ethernet and 4 GiB memory on r8a7796/salvator-x board
* Add r8a7796/salvator-x board part number to bindings
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYb3m2AAoJENfPZGlqN0++FXwP/RKem2QbPujn+OQLPZefMjnc
5ps9d/u739h8o26tYLm1nwWLi3Zajt6XPh3kbv1TQE9y6mI0ySGx2GOLvNKOySNs
Xqinkcjsz1WNujH7ICtAAmdEfoQCAU2vgxrcYMc5w9oeGPEdT/+xGMf7NCPXNgR5
S0qjK5Zc+XZ1lI3nMBS8EJX7D5jBV/X6dy8zyZbNnjfw1QUDNp1c0nBdx5FRMRmj
kUKO8LWo7/zhilLBBWhuNhmILTRa7iUULNr9O9sdq4BmobW7SwSOEJSGTEpvj3hH
6d/WL8b6mOhFUyO4CeAIajOqxhJj+w+7Xcppxwb9Khzi/FJLx71nJ4e0rkIXJrYG
HIqA6et+IWVtoyy0eP85qvKP12gqsoaTcuGGjcm158+UcYVFGE7pnK67IQzPqqkW
iy21gw3owmmuNdJbvNP+vjJKWR2gRCZpy3BAM/4jB8P1V3zqvlhCekMzE7mTF1Uk
V/pI8V0RnKbcE2SGZHOdJvnj1GLPkaBKBMFbkod9++20D21y7UQ19B4Mzq44aSDu
Aul0Igm60Hi+ncsbRWdNjOmChWQoBZzNBtU3UfO7mWjli2JgVzhzH0xK4gI06bGN
coLOBKBkC2z4oQv7eW2nCHX0Qp06f6USwcRQPazWnVPb0g8bNcwwB6iaahDm9zrY
7btgbO+iJv8HxFyOQIrI
=s00S
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm64-dt-for-v4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64
Renesas ARM64 Based SoC DT Updates for v4.11
* Add PWM, and sound MIX and CTU support to r8a7795 SoC
* Add CAN, CAN FD and all MSIOF nodes to r8a7796 SoC
* Use Gen 3 fallback binding for i2c, msiof, PCIE and USB2 phy
* Enable Ethernet and 4 GiB memory on r8a7796/salvator-x board
* Add r8a7796/salvator-x board part number to bindings
* tag 'renesas-arm64-dt-for-v4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: dts: r8a7795: Add PWM support
arm64: dts: r8a7796: Use R-Car Gen 3 fallback binding for msiof nodes
arm64: dts: r8a7796: salvator-x: Enable EthernetAVB
arm64: dts: renesas: r8a7796: Add EthernetAVB instance
arm64: dts: r8a7796: salvator-x: Update memory node to 4 GiB map
arm64: dts: r8a7796: Use R-Car Gen 3 fallback binding for i2c nodes
arm64: dts: r8a7795: Use R-Car Gen 3 fallback binding for i2c nodes
arm64: dts: r8a7795: Use Gen 3 fallback compat string for PCIE
arm64: dts: r8a7795: add sound MIX support
arm64: dts: r8a7795: add sound CTU support
arm64: dts: r8a7795: Use renesas,rcar-gen3-usb2-phy fallback binding
arm64: renesas: r8a7796/salvator-x: Add board part number to DT bindings
arm64: dts: r8a7796: Add CAN FD support
arm64: dts: r8a7796: Add CAN support
arm64: dts: r8a7796: Add CAN external clock support
arm64: dts: r8a7796: Add all MSIOF nodes
Signed-off-by: Olof Johansson <olof@lixom.net>
Tree-wide replacement was done by commit 2ef7d5f342 ("ARM, ARM64:
dts: drop "arm,amba-bus" in favor of "simple-bus"), then the 2nd
round by commit 15b7cc78f0 ("arm64: dts: drop "arm,amba-bus" in
favor of "simple-bus" part 2").
Here, some new users have appeared for Linux v4.10-rc1. Eliminate
them now.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
LS1012A features an advanced 64-bit ARM v8 CortexA53 processor
with 32 KB of parity protected L1-I cache, 32 KB of ECC protected
L1-D cache, as well as 256 KB of ECC protected L2 cache.
Features summary
One 64-bit ARM-v8 Cortex-A53 core with the following capabilities
- Arranged as a cluster of one core supporting a 256 KB L2 cache with ECC
protection
- Speed up to 800 MHz
- Parity-protected 32 KB L1 instruction cache and 32 KB L1 data cache
- Neon SIMD engine
- ARM v8 cryptography extensions
One 16-bit DDR3L SDRAM memory controller
ARM core-link CCI-400 cache coherent interconnect
Cryptography acceleration (SEC)
One Configurable x3 SerDes
One PCI Express Gen2 controller, supporting x1 operation
One serial ATA (SATA Gen 3.0) controller
One USB 3.0/2.0 controller with integrated PHY
Following levels of DTSI/DTS files have been created for the LS1012A
SoC family:
- fsl-ls1012a.dtsi:
DTS-Include file for FSL LS1012A SoC.
- fsl-ls1012a-frdm.dts:
DTS file for FSL LS1012A FRDM board.
- fsl-ls1012a-qds.dts:
DTS file for FSL LS1012A QDS board.
- fsl-ls1012a-rdb.dts:
DTS file for FSL LS1012A RDB board.
Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Currently TM2E dts includes TM2 but there are some differences
between the two boards and TM2 has some properties that TM2E
doesn't have.
That's why it's important to keep the two dts files independent
and put all the commonalities in a tm2-common.dtsi file.
At the current status the only two differences between the two
dts files (besides the board name) are ldo31 and ldo38.
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This patch fixes wrong values assigned to ldo23 and ldo25 on both TM2 and TM2E.
Fixes: 01e5d23521 ("arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board")
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Per the errata of TRM, rk3399 won't support gen2 from
now on, so let's set max-link-speed to 1 in order not
to doing training for gen2.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change the PIN() macro definition so that it can use the macros
from pinctrl/samsung.h header file.
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Use the macros defined in include/dt-bindings/pinctrl/samsung.h
instead of hardcoded values.
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
A64 has a MUSB controller wired to the USB PHY 0, which is connected
to the upper USB Type-A port of Pine64.
As the port is a Type-A female port, enable it in host-only mode in the
device tree, which makes devices with USB Type-A male port can work on
this port (which is originally designed by Pine64 team).
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Allwinner A64 SoC has a MUSB controller like the one in A33, so add
a node for it, just use the compatible of A33 MUSB.
Host mode is tested to work properly on Pine64 and will be added into
the device tree of Pine64 in next patch.
Peripheral mode is also tested on Pine64, by changing dr_mode property
of usb_otg node and use a non-standard USB Type-A to Type-A cable.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Pine64 have two USB Type-A ports, which are wired to the two ports of
A64 USB PHY, and the lower port is the EHCI/OHCI1 port.
Enable the necessary nodes to enable the lower USB port to work.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
In this dts file, uart0 node is put before i2c1.
Move the uart0 node to the end to satisfy alphebetical order.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Allwinner A64 have two HCI USB controllers, a OTG controller and a USB
PHY device which have two ports. One of the port is wired to both a HCI
USB controller and the OTG controller, which is currently not supported.
The another one is only wired to a HCI controller, and the device node of
OHCI/EHCI controller of the port can be added now.
Also the A64 USB PHY device node is also added for the HCI controllers to
work.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
- DT: GXL: fix GPIO include
- add DT and defconfig for newly merged DRM driver
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJYbIZJAAoJEFk3GJrT+8ZlDb0P/1nnnbnxYP2IQzI+XggSLACq
DznCawJmzJaYtvq8LM/BqfIoQW2x32VG5G1a1FYbbv4hySOa5Q5hFwN4/eUSQJq8
nT5fFCwRFl4G2u6fdlBiNUxmN+iguCbY8uAYfVQcsWJ8CUtHjdZnpvopXM8nB0/x
tbOh8rhN042q5SMq74STeBR+YeJyVN9osa8lChL3rVqTuvEHYDScUgDjx2grXzVw
K9rqoEKL/qMN7HWpa/O2hEEvO0sR5UXbB5KIa3j47Vxf7dVRRvPE8fU4mAqqRgxo
NSpceF1YmB90AG+7x8z8ndxJXHbP4DwcJwvwSD+bvuKEBsbfCHuPqQE5lzFSM+Kn
j21NEH7x8tKmKWeoCX2o+mHjn4B3y4SpDnot8CQ/l9nqQxrgxF7u05PckBauprGL
7K/txdS1xYAJ42pBymtgwXzZajaHfLu1i5PA+Fuq80g8VBCgTopv+syAZfSwU/xn
vF8bASfwQYYnVfF05z2K7chyHJiVLdCnIrRQzaHb7QcCMYnhTm9YrVyQ5UXsOaIz
WI2u5ptZUFYs2HGLm3M78IZtN9Ash3XAnrPAR+0R2DF2tyE2686scn/uakcFhVJt
oojrtkmHUbQih48yzI41EtLlviJ41hzykMknzqVfUs4eQayYBayGNAUefFBOwFZb
4JgW2I/SwficH0zKHK/Y
=7ngo
-----END PGP SIGNATURE-----
Merge tag 'amlogic-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into fixes
Pull "Amlogic fixes for v4.10" from Kevin Hilman:
- DT: GXL: fix GPIO include
- add DT and defconfig for newly merged DRM driver
This pull has one real fix, as a couple non-critical ones. The DRM
DT/defconfig patches are coming now because I didn't expect the new
driver to make it for the v4.10 merge window, but since it did[1], the
DT and defconfig should go into the same release.
[1] bbbe775ec5 drm: Add support for Amlogic Meson Graphic Controller
* tag 'amlogic-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
ARM64: defconfig: enable DRM_MESON as module
ARM64: dts: meson-gx: Add Graphic Controller nodes
ARM64: dts: meson-gxl: fix GPIO include
A simple fix to extend GICv2 CPU interface registers from 4K to 8K
on AEMv8 FVP/RTSM models in order to support split priority drop and
interrupt deactivation.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCAAGBQJYZn50AAoJEABBurwxfuKYlUYQAJ4qNonGGnzErQE7bdYS2M+A
fB2R14lhDmCx9HZ7K3ld00x1gaKMJsh1uEU+WXpAt+AFEtJWEaEvWrxcBAY7fQRU
HWs/127+AQgpvKEgVMyOCoc+jj80HipoRMCCzfTZYpbI3LxfvQ7OwV47JpnKmo92
KO/4KZRvODBkupEkMF27ZtrScipLvHsgaYo2H2M2V/AatZ2e1XwGa6r0dxSqauuR
ZEc0C6i3ln8HGOikPwaf5o11MA+m4GHKPQJ55tRjjvn0dIxrh4rshvt+Fiu4h/eX
ImYAtsJS0PhZhRoqamWcfpzKhHQyQF6K05lX2AGBpKEuYjURqSppnndi43oGPIXw
WMe2uS6Ay6Xs9X/viBEJY5B4Cs6STVBVKERJGglHktHn2RGlzLS47XINH/yvOjiv
cbMqTe/PMYgh13QwpQjcuVkgDqhG2LlxueHaptEmJAW0X+juJQVgvSdmb359pn3O
sq+4omo3Z7KnHjBAwDOHVOB9fqTMLNJ/E9MIqEjZ1JrbMmI6C+JUxHBYJ9+Rm9jc
iSkgW1B9I/0lr5kNFLdsvvi9o5yPouZZvOB7DQoj8wnY0NqvmEVNLSRiCsuU4BkT
SFIxo+BK+jLrlAf6imB7jPpl8pM3KL0/BpsvBFRdq7iI7KNUxlPneQNKXYQO1sii
Gh1HgcgTCylRbPqYXhDD
=BoKJ
-----END PGP SIGNATURE-----
Merge tag 'juno-fixes-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into fixes
Pull "ARMv8 Juno/VExpress fixes for v4.10" from Sudeep Holla:
A simple fix to extend GICv2 CPU interface registers from 4K to 8K
on AEMv8 FVP/RTSM models in order to support split priority drop and
interrupt deactivation.
* tag 'juno-fixes-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: vexpress: Support GICC_DIR operations
* Provide sd0_uhs node
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYTl4ZAAoJENfPZGlqN0++vTQP/0hIiDC3Jeb7bkpAX+ZuzHq6
XG/TK5cHaho7Xep/eitlc8gxmO8kL/j5UJIExb0WoBW31QmPhymZnrBiKGHand3Q
OjpmVhK9FeWXcQs4QvL9Lp82Z7qWMaTMhaYDucpd2b4P4GUfpAd3zccsbvqP156k
tG71mYAPIRmXFZgJ+ih57ytwNklSlEm4/84/7oklmNU4Pi0EMyC2eB9DJInMUeyq
QH+8KEx5TBaimHBeGvgYnihIyk3WwoB1ULrZlaOQ/FfjnnK7TZdWhWt4gZUys7qi
GCmbhWR6qoovKxEg9j3cBO1wgWg6AXLrNxs/F1IUBDRViVUFzxJS/14/eW5SfRG3
b7VWm0xpC8RkOaA8yHD4nkpuqXlROVHr0EUkZ9ny6QflEDL8/Pg2SUJCZr7xCFUN
vVyWM1Do/R1ogSmR+Z1RO8omgJEoztFnzNc7d4q9fRAB4o8512oJ1xJFHpv6y3XW
wYRA/SiksEFoYnDXcSkBd2ZMZTiKNvhPWv3yPbP6nJxOpEF6/OWS7VBpGRisLjVk
EksoLn+WliC+1nRrc/S0Nf1YmY8tc62Pg1FwwniS8uTYQFrPNEbc/V/mNU2Sfv/y
ZPnhv6Km33q9xwB0Q94vHLIXMXuaaM90XCT9fSemIoUiDj8lcjE+WYQLxn6WG8ii
a0JlaFlvVkfqYqQFC/cX
=XZkS
-----END PGP SIGNATURE-----
Merge tag 'renesas-fixes-for-v4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes
Renesas ARM Based SoC Fixes for v4.10
* Provide sd0_uhs node
* tag 'renesas-fixes-for-v4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: dts: h3ulcb: Provide sd0_uhs node
Add the 7 PWM channels to the r8a7795 device tree, in the disabled
state.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The BCM958712DxXMC board is a smaller form factor typically used as
controller boards for switches. This smaller board has less devices
pinned out, so only a few need be populated in the device tree.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Nitro firmware is loaded into memory by the bootloader at a specific
location. Set this memory range aside to prevent the kernel from using
it.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This enables the PAXC based PCIe root complex on NS2 SVK. The PAXC based
root complex is connected to internally emulated PCIe endpoints
Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
PAXB and PAXC PCIe interfaces on NS2 have been using the iProc event
queue to handle MSI. With the gicv2m support ready, we should now switch
to gicv2m for MSI handling
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add Video Processing Unit and CVBS Output nodes, and enable CVBS on selected
boards.
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The license text has been mangled at some point then copy pasted across
multiple files. Restore it to what it should be.
Note that this is not intended as a license change.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The Armada 3700 has two i2c bus interface units, this commit adds the
definitions of the corresponding device nodes. It also enables the node
on the development board for this SoC.
Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This commit enables the device node spi0 on the official development
board for the Marvell Armada 3700. It also adds sub-node for the 128Mb
SPI-NOR present on the board.
Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Armada 3700 SoC has an SPI Controller, this commit adds the definition
of the SPI device node at the SoC level.
Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This defines and enables the Marvell ethernet switch MVE886341 on the
Marvell ESPRESSObin board.
Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Use recently added R-Car Gen 3 fallback binding for msiof nodes in
DT for r8a7796 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7796 and the
fallback binding for R-Car Gen 3.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch updates memory region:
- After changes, the new map of the Salvator-X board on R8A7796 SoC
Bank0: 2GiB RAM : 0x000048000000 -> 0x000bfffffff
Bank1: 2GiB RAM : 0x000600000000 -> 0x0067fffffff
- Before changes, the old map looked like this:
Bank0: 2GiB RAM : 0x000048000000 -> 0x000bfffffff
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Correct size of old map]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Use recently added R-Car Gen 3 fallback binding for i2c nodes in
DT for r8a7796 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7796 and the
fallback binding for R-Car Gen 3.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Use recently added R-Car Gen 3 fallback binding for i2c nodes in
DT for r8a7795 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7795 and the
fallback binding for R-Car Gen 3.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Use recently added en 3 fallback compat string for PCIE
in r8a7795 DT.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds CTU (= Channel Transfer Unit) support which is needed
to sound mixing.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
A fallback binding for the Renesas R-Car Gen3 for USB2.0 PHY driver was
added by commit cde7bc367f ("phy: rcar-gen3-usb2: add fallback binding").
This patch makes use of this binding in the DT for the r8a7795 SoC.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Adds CAN FD controller node for r8a7796.
Based on a patch for r8a7795 by Ramesh Shanmugasundaram.
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
