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arm64: dts: allwinner: add USB1-related nodes of Allwinner A64
Allwinner A64 have two HCI USB controllers, a OTG controller and a USB PHY device which have two ports. One of the port is wired to both a HCI USB controller and the OTG controller, which is currently not supported. The another one is only wired to a HCI controller, and the device node of OHCI/EHCI controller of the port can be added now. Also the A64 USB PHY device node is also added for the HCI controllers to work. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -42,8 +42,10 @@
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/clock/sun50i-a64-ccu.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/sun4i-a10.h>
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#include <dt-bindings/reset/sun50i-a64-ccu.h>
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/ {
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interrupt-parent = <&gic>;
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@ -120,6 +122,50 @@ soc {
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#size-cells = <1>;
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ranges;
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usbphy: phy@01c19400 {
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compatible = "allwinner,sun50i-a64-usb-phy";
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reg = <0x01c19400 0x14>,
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<0x01c1b800 0x4>;
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reg-names = "phy_ctrl",
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"pmu1";
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clocks = <&ccu CLK_USB_PHY0>,
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<&ccu CLK_USB_PHY1>;
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clock-names = "usb0_phy",
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"usb1_phy";
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resets = <&ccu RST_USB_PHY0>,
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<&ccu RST_USB_PHY1>;
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reset-names = "usb0_reset",
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"usb1_reset";
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status = "disabled";
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#phy-cells = <1>;
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};
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ehci1: usb@01c1b000 {
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compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
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reg = <0x01c1b000 0x100>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_OHCI1>,
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<&ccu CLK_BUS_EHCI1>,
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<&ccu CLK_USB_OHCI1>;
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resets = <&ccu RST_BUS_OHCI1>,
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<&ccu RST_BUS_EHCI1>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci1: usb@01c1b400 {
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compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
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reg = <0x01c1b400 0x100>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_OHCI1>,
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<&ccu CLK_USB_OHCI1>;
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resets = <&ccu RST_BUS_OHCI1>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ccu: clock@01c20000 {
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compatible = "allwinner,sun50i-a64-ccu";
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reg = <0x01c20000 0x400>;
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