Commit Graph

33333 Commits

Author SHA1 Message Date
Alexandre Courbot
63f542e473 drm/nouveau/secboot: clear halt interrupt after ACR is run
The halt interrupt must be cleared after ACR is run, otherwise the LS
PMU firmware will not be able to run.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:32 +10:00
Alexandre Courbot
425c816a80 drm/nouveau/secboot: add lazy-bootstrap flag
When the PMU firmware is present, the falcons it manages need to have
the lazy-bootstrap flag of their WPR header set so the ACR does not boot
them. Add support for this.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:32 +10:00
Alexandre Courbot
64a94ded89 drm/nouveau/secboot: fix WPR descriptor generation
Generate the WPR descriptor closer to what RM does. In particular, set
the expected masks, and only set the ucode members on Tegra.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:32 +10:00
Alexandre Courbot
45ef845009 drm/nouveau/secboot: set default error value in error register
Set a default error value in the mailbox 0 register so we can catch
cases where the secure boot binary fails early without being able to
report anything.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:32 +10:00
Alexandre Courbot
b606234e2f drm/nouveau/secboot: add missing fields to BL structure
Since DMEM was initialized to zero, these fields went unnoticed. Add
them for safety.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:32 +10:00
Alexandre Courbot
b2888c650e drm/nouveau/secboot: safer zeroing of BL descriptors
Perform the zeroing of BL descriptors in the caller function instead of
trusting each generator will do it. This could avoid a few pulled hairs.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:32 +10:00
Alexandre Courbot
9d896f3e41 drm/nouveau/secboot: abstract LS firmware loading functions
The WPR and LSB headers, used to generate the LS blob, may have a
different layout and sizes depending on the driver version they come
from. Abstract them and confine their use to driver-specific code.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:32 +10:00
Alexandre Courbot
9839307cfe drm/nouveau/secboot: remove ls_ucode_mgr
This was used only locally to one function and can be replaced by ad-hoc
variables.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:32 +10:00
Alexandre Courbot
88490323e4 drm/nouveau/secboot: remove unneeded ls_ucode_img member
ucode_header is not used anywhere, so just get rid of it.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:32 +10:00
Alexandre Courbot
3454a034b7 drm/nouveau/secboot: disable falcon interrupts when running blob
Make sure we are not disturbed by spurious interrupts, as we poll the
halt bit anyway.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
555cafb404 drm/nouveau/secboot: split reset function
Split the reset function into more meaningful and reusable ones.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
8a50452c89 drm/nouveau/secboot: add LS flags to LS func structure
Add a flag that can be set when declaring how a LS firmware should be
loaded. This allows us to remove falcon-specific code in the loader.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
72e0642fb4 drm/nouveau/secboot: reorganize into more files
Split the act of building the ACR blob from firmware files from the rest
of the (chip-dependent) secure boot logic. ACR logic is moved into
acr_rxxx.c files, where rxxx corresponds to the compatible release of
the NVIDIA driver. At the moment r352 and r361 are supported since
firmwares have been released for these versions. Some abstractions are
added on top of r352 so r361 can easily be implemented on top of it by
just overriding a few hooks.

This split makes it possible and easy to reuse the same ACR version on
different chips. It also hopefully makes the code much more readable as
the different secure boot logics are separated. As more chips and
firmware versions will be supported, this is a necessity to not get lost
in code that is already quite complex.

This is a big commit, but it essentially moves things around (and split
the nvkm_secboot structure into two, nvkm_secboot and nvkm_acr). Code
semantics should not be affected.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
8f491c892e drm/nouveau/secboot: generate HS BL descriptor in hook
Use the HS hook to completely generate the HS BL descriptor, similarly
to what is done in the LS hook, instead of (arbitrarily) using the
acr_v1 format as an intermediate.

This allows us to make the bootloader descriptor structures private to
each implementation, resulting in a cleaner an more consistent design.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
e781ff9118 drm/nouveau/secboot: add low-secure firmware hooks
Secure firmwares provided by NVIDIA will follow the same overall
principle, but may slightly differ in format, or not use the same
bootloader descriptor even on the same chip. In order to handle
this as gracefully as possible, turn the LS firmware functions into
hooks that can be overloaded as needed.

The current hooks cover the external firmware loading as well as the
bootloader descriptor generation.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
a9b333a50e drm/nouveau/secboot: remove fixup_hs_desc hook
This hook can be removed if the function writing the HS
descriptor is aware of WPR settings. Let's do that as it allows us to
make the ACR descriptor structure private and save some code.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
808d6efdeb drm/nouveau/secboot: rename init() hook to oneinit()
The init() hook is called by the subdev's oneinit(). Rename it
accordingly to avoid confusion about the lifetime of objects allocated
in it.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
c8225b54fe drm/nouveau/secboot: remove nvkm_secboot_start()
Since GR has moved to using the falcon library to start the falcons,
this function is not needed anymore.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
89cd6e2071 drm/nouveau/gr/gf100: instantiate and reserve GR falcons
Create instances for the FECS and GPCCS falcons and use the init() and
fini() hooks to reserve them for as long as GR controls them.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
0296b5d985 drm/nouveau/gr/gf100: split gf100_gr_init_ctxctl()
gf100_gr_init_ctxctl() is basically two different functions (one for
use of internal firmware, the other for use of external firmware), but
its current layout makes it look more complex than it is. Split it to
better reflect that fact.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
d2753f40a9 drm/nouveau/gr: add fini() hook
Add a fini() hook to the GR engine. This will be used by gf100+ to
properly release the FECS and GPCCS falcons.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
d72fb36c45 drm/nouveau/secboot: use falcon library
Use the falcon library functions in secure boot. This removes a lot of
code and makes the secure boot flow easier to understand as no register
is directly accessed.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
236f474791 drm/nouveau/secboot: fix functions definitions
These functions should use the nvkm_secboot_falcon enum. Fix this.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
b1c39d801a drm/nouveau/gm20b: add dummy PMU device
Add a dummy PMU device so the PMU falcon is instanciated and can be used
by secure boot.

We could reuse gk20a's implementation here, but it would fight with
secboot over PMU falcon's ownership and secboot will reset the PMU,
preventing it from operating afterwards. Proper handout between secboot
and pmu is coming along with the actual gm20b PMU implementation, so
use this as a temporary solution.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
9b071c7935 drm/nouveau/pmu/gk20a: use falcon library functions
Use the falcon library functions where relevant.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
68d82161fd drm/nouveau/pmu/gk20a: simplify code a bit
Some functions always succeed - change their return type to void and
remove the error-handling code in their caller.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
d8711c5a9c drm/nouveau/pmu/gk20a: use nvkm_pmu_ctor()
Use the PMU constructor so that all base members (in particular the
falcon instance) are initialized properly.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:30 +10:00
Alexandre Courbot
1e2115d8c0 drm/nouveau/pmu: instanciate the falcon in PMU device
Have an instance of nvkm_falcon in the PMU structure, ready to be used
by other subdevs (i.e. secboot).

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:30 +10:00
Alexandre Courbot
e72da6e04f drm/nouveau/pmu: add nvkm_pmu_ctor() function
Add a PMU constructor so implementations that extend the nvkm_pmu
structure can have all base members properly initialized.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:30 +10:00
Alexandre Courbot
31214108ad drm/nouveau/core: add falcon library functions
Falcon processors are used in various places of GPU chips. Although there
exist different versions of the falcon, and some variants exist, the
base set of actions performed on them is the same, which results in lots
of duplicated code.

This patch consolidates the current nvkm_falcon structure and extends it
with the following features:

* Ability for an engine to obtain and later release a given falcon,
* Abstractions for basic operations (IMEM/DMEM access, start, etc)
* Abstractions for secure operations if a falcon is secure

Abstractions make it easy to e.g. start a falcon, without having to care
about its details. For instance, falcons in secure mode need to be
started by writing to a different register.

Right now the abstractions variants only cover secure vs. non-secure
falcon, but more will come as e.g. SEC2 support is added.

This is still a WIP as other functions previously done by
engine/falcon.c need to be reimplemented. However this first step allows
to keep things simple and to discuss basic design.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:30 +10:00
Alexandre Courbot
c599dd4b70 drm/nouveau/mc: add nvkm_mc_enabled() function
Add a function that allows us to query whether a given subdev is
currently enabled or not.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:30 +10:00
Alexandre Courbot
c1fcb14879 drm/nouveau/core: constify nv*_printk macros
Constify the local variables declared in these macros so we can pass
const pointers to them.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:30 +10:00
Dave Airlie
9ca70356a9 Revert "drm: Resurrect atomic rmfb code, v3"
This reverts commit 1592364de3.

This apparantly causes some regressions so pull it out for now.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-17 12:39:04 +10:00
Dave Airlie
08293fe8d3 omapdrm fixes for v4.11
Fix regressions:
 - Planes might have been left enabled
 - Scaling checks did not use the new config
 
 Also limit downscaling decimation to prevent HW underflows.
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Merge tag 'omapdrm-4.11-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux into drm-next

omapdrm fixes for v4.11

Fix regressions:
- Planes might have been left enabled
- Scaling checks did not use the new config

Also limit downscaling decimation to prevent HW underflows.

* tag 'omapdrm-4.11-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux:
  drm/omapdrm: dispc: Refuse x-decimation above 4 for all but 8-bit formats
  drm/omapdrm: Move commit_modeset_enables() before commit_planes()
  Revert "drm: omapdrm: Let the DRM core skip plane commit on inactive CRTCs"
2017-02-17 12:04:09 +10:00
Dave Airlie
dec13c8ba2 Merge branch 'drm-next-4.11' of git://people.freedesktop.org/~agd5f/linux into drm-next
Fixes for 4.11. Highlights:
- fix >2 displays on asics with 3 or 5 crtcs
- fix SI headless asics
- powerplay fixes for new polaris variants
- misc fixes

* 'drm-next-4.11' of git://people.freedesktop.org/~agd5f/linux:
  drm/amdgpu: fix warning on older gcc releases
  drm/ttm: make TTM_MAX_BO_PRIORITY unsigned
  drm/amd/amdgpu: Fix flow control in uvd_v4_2_stop()
  drm/amd/powerplay: add didt config table for polaris kicker
  drm/amd/powerplay: modify VddcPhase value for polaris kicker
  drm/amd/powerplay: add kicker flag into smumgr
  drm/amdgpu: Initialize pipe priority order on graphic initialization
  drm/amdgpu: read hw register to check pg status.
  drm/amdgpu: Add to initialization of mmVCE_VCPU_CNTL register
  drm/amdgpu/pm: check for headless before calling compute_clocks
  drm/amdgpu: use amdgpu_gem_va_check() in amdgpu_gem_va_update_vm()
  drm/amdgpu: add more cases to DCE11 possible crtc mask setup
2017-02-17 11:55:12 +10:00
Arnd Bergmann
e8411302b4 drm/amdgpu: fix warning on older gcc releases
gcc-4.8 warns about '{0}' being used an an initializer for nested structures:

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c: In function ‘gfx_v8_0_ring_emit_ce_meta_init’:
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:7263:2: warning: missing braces around initializer [-Wmissing-braces]
  } ce_payload = {0};
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c: In function ‘gfx_v8_0_ring_emit_de_meta_init’:
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:7290:2: warning: missing braces around initializer [-Wmissing-braces]
  } de_payload = {0};

Using an empty {} initializer however has the same effect and works on all versions.

Fixes: acad2b2a7b ("drm/amdgpu:implement CE/DE meta-init routines")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-02-16 12:19:52 -05:00
Tom St Denis
e89d5b5c20 drm/amd/amdgpu: Fix flow control in uvd_v4_2_stop()
Break out of outer loop properly.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-02-16 11:43:44 -05:00
Huang Rui
fce293ca3d drm/amd/powerplay: add didt config table for polaris kicker
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-02-16 11:43:32 -05:00
Huang Rui
28a488848f drm/amd/powerplay: modify VddcPhase value for polaris kicker
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-02-16 11:43:22 -05:00
Huang Rui
5d7213b0be drm/amd/powerplay: add kicker flag into smumgr
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-02-16 11:43:11 -05:00
Jyri Sarha
1b30ab0c40 drm/omapdrm: dispc: Refuse x-decimation above 4 for all but 8-bit formats
Let's disable all scaling that requires horizontal decimation with
higher factor than 4, until we have better estimates of what we can
and can not do. However, NV12 color format appears to work Ok with
all decimation factors.

When decimating horizontally by more that 4 the dss is not able to
fetch the data in burst mode. When this happens it is hard to tell if
there enough bandwidth. Despite what theory says this appears to be
true also for 16-bit color formats.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2017-02-16 14:11:08 +02:00
Jyri Sarha
897145d0c7 drm/omapdrm: Move commit_modeset_enables() before commit_planes()
Move drm_atomic_helper_commit_modeset_enables() call to before
drm_atomic_helper_commit_planes() call and have a
omap_atomic_wait_for_completion() call after both.

With the current dss dispc implementation we have to enable the new
modeset before we can commit planes. The dispc ovl configuration
relies on the video mode configuration been written into the HW when
the ovl configuration is calculated.

This approach is not ideal because after a mode change the plane
update is executed only after the first vblank interrupt. The dispc
implementation should be fixed so that it is able use uncommitted drm
state information.  information.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2017-02-16 14:09:55 +02:00
Jyri Sarha
e025d3860b Revert "drm: omapdrm: Let the DRM core skip plane commit on inactive CRTCs"
This reverts commit dadf4659d0.

If planes are not disabled when the they are not on any crtc anymore
they will remain active and may show as "ghosts" when the crtc they
were last on is active again.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2017-02-16 14:09:55 +02:00
Dave Airlie
be3c9f5eed Merge branch 'drm-rockchip-next-2017-02-16' of https://github.com/markyzq/kernel-drm-rockchip into drm-next
Use iommu for rockchip arm64 platform.

* 'drm-rockchip-next-2017-02-16' of https://github.com/markyzq/kernel-drm-rockchip:
  drm/rockchip: Use common IOMMU API to attach devices
  drm/rockchip: Do not use DMA mapping API if attached to IOMMU domain
2017-02-16 13:57:37 +10:00
Dave Airlie
b7bc0daa88 Merge tag 'drm-misc-next-fixes-2017-02-15' of git://anongit.freedesktop.org/git/drm-misc into drm-next
Fixes for the v4.11 merge window.

* tag 'drm-misc-next-fixes-2017-02-15' of git://anongit.freedesktop.org/git/drm-misc:
  drm: Resurrect atomic rmfb code, v3
  uapi: add missing install of dma-buf.h
2017-02-16 13:27:55 +10:00
Maarten Lankhorst
1592364de3 drm: Resurrect atomic rmfb code, v3
This was somehow lost between v3 and the merged version in Maarten's
patch merged as:

commit f2d580b9a8
Author: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Date:   Wed May 4 14:38:26 2016 +0200

    drm/core: Do not preserve framebuffer on rmfb, v4.

This introduces a slight behavioral change to rmfb. Instead of
disabling a crtc when the primary plane is disabled, we try to
preserve it.

Apart from old versions of the vmwgfx xorg driver, there is
nothing depending on rmfb disabling a crtc. Since vmwgfx is
a legacy driver we can safely only disable the plane with atomic.

If this commit is rejected by the driver then we will still fall
back to the old behavior and turn off the crtc.

v2:
- Remove plane->fb assignment, done by drm_atomic_clean_old_fb.
- Add WARN_ON when atomic_remove_fb fails.
- Always call drm_atomic_state_put.
v3:
- Use drm_drv_uses_atomic_modeset
- Handle the case where the first plane-disable-only commit fails
  with -EINVAL. Some drivers do not support this, fall back to
  disabling all crtc's in this case.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/66fc3da5-697b-1613-0a67-a5293209f0dc@linux.intel.com
2017-02-15 15:40:57 +02:00
Shunqian Zheng
1aa5ca6e3e drm/rockchip: Use common IOMMU API to attach devices
Rockchip DRM used the arm special API, arm_iommu_*(), to attach
iommu for ARM32 SoCs. This patch convert to common iommu API
so it would support ARM64 like RK3399.

Since previous patch added support for direct IOMMU address space
management, there is no need to use DMA API anymore and this patch wires
things to use the new method.

Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
2017-02-15 08:52:13 +08:00
Tomasz Figa
38f993b7c5 drm/rockchip: Do not use DMA mapping API if attached to IOMMU domain
The API is not suitable for subsystems consisting of multiple devices
and requires severe hacks to use it. To mitigate this, this patch
implements allocation and address space management locally by using
helpers provided by DRM framework, like other DRM drivers do, e.g.
Tegra.

This patch should not introduce any functional changes until the driver
is made to attach subdevices into an IOMMU domain with the generic IOMMU
API, which will happen in following patch. Based heavily on GEM
implementation of Tegra DRM driver.

Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: rjan Eide <orjan.eide@arm.com>
2017-02-15 08:52:13 +08:00
ozeng
d238326755 drm/amdgpu: Initialize pipe priority order on graphic initialization
Initialized PIPE_ORDER_TS0/1/2/3 field of SPI_ARB_PRIORITY register to 2.
This set the pipe priority order to:
02 - HP3D, CS_H, GFX, CS_M, CS_L

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-02-13 15:08:33 -05:00
Rex Zhu
254cd2e08d drm/amdgpu: read hw register to check pg status.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-02-13 12:43:04 -05:00