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drm/nouveau/secboot: fix WPR descriptor generation
Generate the WPR descriptor closer to what RM does. In particular, set the expected masks, and only set the ucode members on Tegra. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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@ -496,19 +496,22 @@ acr_r352_fixup_hs_desc(struct acr_r352 *acr, struct nvkm_secboot *sb,
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{
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struct nvkm_gpuobj *ls_blob = acr->ls_blob;
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desc->ucode_blob_base = ls_blob->addr;
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desc->ucode_blob_size = ls_blob->size;
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desc->wpr_offset = 0;
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/* WPR region information if WPR is not fixed */
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if (sb->wpr_size == 0) {
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u32 wpr_start = ls_blob->addr;
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u32 wpr_end = wpr_start + ls_blob->size;
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desc->wpr_region_id = 1;
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desc->regions.no_regions = 1;
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desc->regions.no_regions = 2;
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desc->regions.region_props[0].start_addr = wpr_start >> 8;
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desc->regions.region_props[0].end_addr = wpr_end >> 8;
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desc->regions.region_props[0].region_id = 1;
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desc->regions.region_props[0].start_addr = ls_blob->addr >> 8;
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desc->regions.region_props[0].end_addr =
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(ls_blob->addr + ls_blob->size) >> 8;
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desc->regions.region_props[0].read_mask = 0xf;
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desc->regions.region_props[0].write_mask = 0xc;
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desc->regions.region_props[0].client_mask = 0x2;
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} else {
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desc->ucode_blob_base = ls_blob->addr;
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desc->ucode_blob_size = ls_blob->size;
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}
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}
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