Commit Graph

378041 Commits

Author SHA1 Message Date
Alex Deucher
5c7524bf06 drm/radeon/atom: fix endian bug in radeon_atom_init_mc_reg_table()
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 15:46:40 -04:00
Alex Deucher
aa71d830c4 drm/radeon: remove sumo dpm/uvd bringup leftovers
Function doesn't do anything useful.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 15:46:32 -04:00
Dave Airlie
f7d452f4fd Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next
- Various fixes that make surviving concurrent piglit more possible.
- Buffer object deletion no longer synchronous
- Context/register initialisation updates that have been reported to
solve some stability issues (particularly on some problematic GF119
chips)
- Kernel side support for VP2 video decoding engines

* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (44 commits)
  drm/nvd0-/disp: handle case where display engine is missing/disabled
  drm/gr/nvc0-: merge nvc0/nve0 ucode, and use cpp instead of m4
  drm/nouveau/bsp/nv84: initial vp2 engine implementation
  drm/nouveau/vp/nv84: initial vp2 engine implementation
  drm/nouveau/core: xtensa engine base class implementation
  drm/nouveau/vdec: fork vp3 implementations from vp2
  drm/nouveau/core: move falcon class to engine/
  drm/nouveau/kms: don't fail if there's no dcb table entries
  drm/nouveau: remove limit on gart
  drm/nouveau/vm: perform a bar flush when flushing vm
  drm/nvc0/gr: cleanup register lists, and add nvce/nvcf to switches
  drm/nvc8/gr: update initial register/context values
  drm/nvc4/gr: update initial register/context values
  drm/nvc1/gr: update initial register/context values
  drm/nvc3/gr: update initial register/context values
  drm/nvc0/gr: update initial register/context values
  drm/nvd9/gr: update initial register/context values
  drm/nve4/gr: update initial register/context values
  drm/nvc0-/gr: bump maximum gpc/tpc limits
  drm/nvf0/gr: initial register/context setup
  ...
2013-07-01 14:10:20 +10:00
Maarten Lankhorst
791dc143ed drm/nvd0-/disp: handle case where display engine is missing/disabled
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:50 +10:00
Ben Skeggs
e99716f13d drm/gr/nvc0-: merge nvc0/nve0 ucode, and use cpp instead of m4
No code changes, proven by envyas producing identical binaries.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:50 +10:00
Ilia Mirkin
05f9a5bc58 drm/nouveau/bsp/nv84: initial vp2 engine implementation
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:49 +10:00
Ilia Mirkin
a0376b1481 drm/nouveau/vp/nv84: initial vp2 engine implementation
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:49 +10:00
Ilia Mirkin
44b1e3bd6a drm/nouveau/core: xtensa engine base class implementation
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:48 +10:00
Ilia Mirkin
0d4a1450c9 drm/nouveau/vdec: fork vp3 implementations from vp2
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:48 +10:00
Ben Skeggs
a0fd4ec8f1 drm/nouveau/core: move falcon class to engine/
Not really "core" per-se.  About to merge Ilia's work adding another
similar class for the VP2 xtensa engines, so, seems like a good time to
move all these to engine/.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:47 +10:00
Ben Skeggs
d2898713fb drm/nouveau/kms: don't fail if there's no dcb table entries
Fixes module not loading on Tesla K20.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:46 +10:00
Maarten Lankhorst
79442c3af0 drm/nouveau: remove limit on gart
Most graphics cards nowadays have a multiple of this limit as their vram,
so limiting GART doesn't seem to make much sense.

Signed-off-by: Maarten >Lnkhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:43 +10:00
Maarten Lankhorst
36798b61ed drm/nouveau/vm: perform a bar flush when flushing vm
Appears to fix the regression from "drm/nvc0/vm: handle bar tlb flushes
internally".

nvidia always seems to do this flush after writing values.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:42 +10:00
Ben Skeggs
57f0ec159b drm/nvc0/gr: cleanup register lists, and add nvce/nvcf to switches
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:41 +10:00
Ben Skeggs
eb12f57be6 drm/nvc8/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:41 +10:00
Ben Skeggs
dba50728fd drm/nvc4/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:40 +10:00
Ben Skeggs
58ef23056a drm/nvc1/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:40 +10:00
Ben Skeggs
8b637ae3a3 drm/nvc3/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:39 +10:00
Ben Skeggs
d8b02dbbc3 drm/nvc0/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:39 +10:00
Ben Skeggs
37c3afd07c drm/nvd9/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:38 +10:00
Ben Skeggs
1dd44acfab drm/nve4/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:37 +10:00
Ben Skeggs
a8004a9edd drm/nvc0-/gr: bump maximum gpc/tpc limits
Needed for GK110, separate commit to catch any unexpected breaks to
other parts of the code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:37 +10:00
Ben Skeggs
cb1e06e0e3 drm/nvf0/gr: initial register/context setup
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:36 +10:00
Ben Skeggs
507cd5b553 drm/nve7/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:36 +10:00
Ben Skeggs
99bd5537bd drm/nve6/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:35 +10:00
Ben Skeggs
c4c7044ffc drm/nouveau: delay busy bo vma removal until fence signals
As opposed to an explicit wait.  Allows userspace to not stall waiting
on buffer deletion.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:31 +10:00
Ben Skeggs
780194b1b9 drm/nouveau/vm: make each vma take a reference on its parent vm
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:45:09 +10:00
Ben Skeggs
51a506c012 drm/nouveau/core: remove nouveau_mm.mutex, no more users
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:45:05 +10:00
Ben Skeggs
4e67bee8e1 drm/nouveau/vm: take subdev mutex, not the mm, protects against race with vm/nvc0
nvc0_vm_flush() accesses the pgd list, which will soon be able to race
with vm_unlink() during channel destruction.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:45:03 +10:00
Ben Skeggs
15cace5917 drm/nvc0/vm: handle bar tlb flushes internally
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:44:57 +10:00
Ben Skeggs
ca97a36698 drm/nv50-/vm: take mutex rather than irqsave spinlock
These operations can take quite some time, and we really don't want to
have to hold a spinlock for too long.

Now that the lock ordering for vm and the gr/nv84 hw bug workaround has
been reversed, it's possible to use a mutex here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:44:50 +10:00
Ben Skeggs
464d636bd0 drm/nv50/vm: remove explicit vm knowledge from engines
This reverses the lock ordering between VM and gr/nv84:nvc0.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:44:44 +10:00
Ben Skeggs
c3032adb5c drm/nv50/vm: handle bar tlb flushes internally
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:44:37 +10:00
Ben Skeggs
fec43a722a drm/nvc0/gr: port mp trap handling from calim's kepler code
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:44:32 +10:00
Ben Skeggs
16b133df33 drm/nve0/gr: attempt to resume after sm traps
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:44:26 +10:00
Ben Skeggs
3d8a6ed247 drm/nve0/gr: s/tp/tpc/
NVIDIA's name...

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:44:20 +10:00
Ben Skeggs
8d6f585d00 drm/nve0/fifo: create our playlists up-front, at startup
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:44:12 +10:00
Ben Skeggs
da746d4ec9 drm/nva3/clk: minor improvements to fractional N calculation
Helps us to get identical numbers to the binary driver for (at least)
Kepler memory PLLs, and fixes a rounding error.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:44:06 +10:00
Ben Skeggs
dceef5d87c drm/nouveau/fb: initialise vram controller as pfb sub-object
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:44:04 +10:00
Ben Skeggs
54ecff3e1a drm/nouveau/clk: change init ordering, no longer needed by devinit
And, will depend on FB/VOLT/DAEMON being ready when it gets initialised
so that it can set/restore clocks.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:44:01 +10:00
Ben Skeggs
88524bc069 drm/nouveau/devinit: move simple pll setting routines to devinit
These are pretty much useless for reclocking purposes.  Lets make it
clearer what they're for and move them to DEVINIT to signify they're
for the very simple PLL setting requirements of running the init
tables.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:43:54 +10:00
Ben Skeggs
7ada785f18 drm/nouveau: pass generic subdev to calculation routines
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:43:47 +10:00
Ben Skeggs
aca78e9158 drm/nve0/ce: stub interrupt handler
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:43:42 +10:00
Ben Skeggs
48506d17d5 drm/nve0/ce: link ce2 to its engine, rather than from graphics
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:43:36 +10:00
Ben Skeggs
01672ef454 drm/nve0/fifo: copy engine context stored in ramfc, not externally
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:43:30 +10:00
Ben Skeggs
b0bc5304fe drm/nve0/ce: create engine object for ce2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:43:23 +10:00
Ben Skeggs
d53635a980 drm/nouveau: pull in latest ucode builds from external tree
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:43:21 +10:00
Dave Airlie
c344ee6809 Merge branch 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next
Feature summary:
Add S3C64XX SoC series support - S3C64XX SoC series are previous version
chips of Exynos SoC series. With this patch set, KMS driver of Exynos drm
supports those chips also.

Update device tree support - This patch set corrects compatible strings,
and adds Exynos5420 SoC support for hdmi subsystem.

Consider CCF (Common Clock Framework) support - With reference to CCF
support, it uses clock_prepare_enable/clock_disable_unprepare instead of
clk_enable/clk_disable for hdmi subsystem.

Big cleanups - This patch just removes unnecessary all debug logs.

* 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos: (22 commits)
  ARM: dts: change compatible strings for EXYNOS5250 hdmi subsystem
  drm/exynos: add support for exynos5420 mixer
  drm/exynos: add new compatible strings for hdmi subsystem
  drm/exynos: fix interlace resolutions for exynos5420
  drm/exynos: use of_get_named_gpio to get hdmi hpd gpio
  drm/exynos: make sure to handle an error case to vm_mmap call
  drm/exynos: exynos_drm_ipp: Remove redundant break statement
  drm/exynos: add mout_hdmi clock in hdmi driver to change parent
  drm/exynos: Prepare/Unprepare HDMI subsystem clocks
  drm/exynos: Clean up logs for DRM_ERROR / DRM_DEBUG_KMS
  drm/exynos: Remove tracking log functions
  drm/exynos: hdmi: use drm_display_mode to check the supported modes
  drm/exynos: fimd: Add support for S3C64xx SoCs
  drm/exynos: fimd: Add support for FIMD variants with clock selection
  drm/exynos: fimd: Add support for FIMD versions without SHADOWCON register
  drm/exynos: fimd: Hold pointer to driver data in context struct
  drm/exynos: do not use mode_set_base function directly
  drm/exynos: Remove redundant use of of_match_ptr macro
  drm/exynos: remove ignoring return value warning in hdmi
  drm/exynos: fix WINDOWS_NR checking to vidi driver
  ...
2013-07-01 10:08:45 +10:00
Rahul Sharma
0d1fc82979 ARM: dts: change compatible strings for EXYNOS5250 hdmi subsystem
This patch renames the combatible strings for hdmi, mixer, ddc
and hdmiphy. It follows the convention of using compatible string
which represent the SoC in which the IP was added for the first
time.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-06-28 21:13:57 +09:00
Rahul Sharma
def5e09571 drm/exynos: add support for exynos5420 mixer
Add support for exynos5420 mixer IP in the drm mixer driver.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Acked-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-06-28 21:13:57 +09:00