Commit Graph

78 Commits

Author SHA1 Message Date
Marek Vasut
b8d9b3e407 ARM: dts: socfpga: Fix the ethernet clock phandle
The ethernet block clock phandle must point to the clock node which
represents the clock which directly supply the ethernet block. This
is emac_x_clk , not emacx_clk , so fix this.

From: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-06-23 09:29:08 -05:00
Florian Vaussard
3486935377 ARM: dts: socfpga: Add support for PMU
The dual Cortex-A9 MPCore inside socfpga has a standard PMU unit for
each core mapped in the DAP memory space. Add support for it!

Tested with perf on a Cyclone 5 SoC DK.

Reported-by: Alberto Dassatti <alberto.dassatti@heig-vd.ch>
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Tested-by: Alberto Dassatti <alberto.dassatti@heig-vd.ch>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-06 16:02:58 -06:00
Florian Vaussard
e3e6dba1af ARM: dts: socfpga: Add labels for CPU nodes
This makes it easier to reference the CPU nodes afterwards.

Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-06 16:02:17 -06:00
Florian Vaussard
439f559109 ARM: dts: socfpga: Do not include skeleton.dtsi
The skeleton.dtsi file is now deprecated as noted in commit 9c0da3cc61
("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). The SoCFPGA
device trees already contain the nodes that are defined in skeleton.dtsi
(#address-cells, #size-cells, chosen, aliases, memory).

Including skeleton.dtsi is useless and will produce the following
warning when compiled with W=1:

Node /memory has a reg or ranges property, but no unit name

Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-06 15:54:58 -06:00
Florian Vaussard
0c9ff61586 ARM: dts: socfpga: Remove unneeded unit names
Node eccmgr has a unit name, but do not have a reg property as only the
child nodes do have this property. Likewise the usbphy node do not have
a reg property. This will trigger the following warnings when compiled
with W=1:

Node /soc/eccmgr@ffd08140 has a unit name, but no reg property
Node /soc/usbphy@0 has a unit name, but no reg property

Remove the superfluous unit names.

Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-06 15:54:58 -06:00
Florian Vaussard
9f24e81659 ARM: dts: socfpga: Add unit name to clock nodes
Most clock nodes in Arria5, Cyclone5 and Arria10 have a reg property but
does not have a unit name. This will trigger several warnings like this
one (when compiled with W=1):

Node /soc/clkmgr@ffd04000/clocks/periph_pll has a reg or ranges
property, but no unit name

Add the corresponding unit name to each node.

Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-06 15:54:58 -06:00
Dinh Nguyen
7f0f5460d4 ARM: dts: socfpga: add missing compatible string for SDRAM controller
Add "altr,sdr-ctl" to the SDRAM controller node.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-01-06 01:42:06 -06:00
Alan Tull
7c8e5afd68 ARM: dts: socfpga: add base fpga region and fpga bridges
Add h2f and lwh2f bridges.
Add base FPGA Region to support DT overlays for FPGA programming.
Add l3regs.

Signed-off-by: Alan Tull <atull@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: removed fpga-bridges, ranges, and reset-names
2017-01-06 01:41:17 -06:00
Dinh Nguyen
6ed6bf4762 ARM: dts: socfpga: fpga manager data is 32 bits
Adjust regs property for the FPGA manager data register to
properly reflect that it is a single 32 bit register.

Signed-off-by: Dalon Westergreen <dwesterg@altera.com>
Signed-off-by: Alan Tull <atull@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-01-05 06:12:54 -06:00
Marek Vasut
7c38dc624b ARM: dts: socfpga: fine-tune L2 cache configuration
Enable double-linefill and increase prefetch offset, which gives
considerable read performance boost. The following numbers were
obtained using lmbench 3.0 bw_mem tool, for easier comparison, the
numbers are pasted in two columns. The test machine has Cyclone V
SoC running at 800MHz MPU clock and 512MiB 333MHz 16bit DDR3 DRAM.

Without patch   | With patch
$ for i in rd wr rdwr cp fwr frd fcp bzero bcopy ; do echo $i ; bw_mem 64M $i ; done
rd              | rd
64.00 526.46    | 64.00 1151.06
wr              | wr
64.00 329.95    | 64.00 346.14
rdwr            | rdwr
64.00 342.07    | 64.00 367.24
cp              | cp
64.00 239.79    | 64.00 322.47
fwr             | fwr
64.00 1027.90   | 64.00 1025.38
frd             | frd
64.00 322.36    | 64.00 641.89
fcp             | fcp
64.00 256.99    | 64.00 408.41
bzero           | bzero
64.00 1028.43   | 64.00 1025.07
bcopy           | bcopy
64.00 294.73    | 64.00 357.19

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-11-21 09:23:31 -06:00
Steffen Trumtrar
d837a80d19 ARM: dts: socfpga: add nand controller nodes
Add the denali nand controller to the socfpga dtsi.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2016-11-09 12:40:52 -06:00
Steffen Trumtrar
c6deff00b9 ARM: dts: socfpga: add qspi node
Add the qspi node to the socfpga dtsi file.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-18 22:18:13 -05:00
Dinh Nguyen
ecba2390e3 ARM: dts: socfpga: enable arm,shared-override in the pl310
Enable the bit(22) shared-override bit for the SoCFPGA family. While at it,
enable the prefetch-data and prefetch-instr settings for the Arria10.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-18 15:57:13 -05:00
Dinh Nguyen
249ff32e1f ARM: dts: socfpga: add reset control for USB
Add the resets property for the 2 USB controllers.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-04-11 14:04:06 -05:00
Linus Torvalds
5a6b7e53d0 ARM: DT updates for v4.6
These are all the updates to device tree files for 32-bit platforms,
 plus a couple of related 64-bit updates:
 
 New SoC support:
  - Allwinner A83T
  - Axis Artpec-6 SoC
  - Mediatek MT7623 SoC
  - TI Keystone K2G SoC
  - ST Microelectronics stm32f469
 
 New board or machine support:
  - ARM Juno R2
  - Buffalo Linkstation LS-QVL and LS-GL
  - Cubietruck plus
  - D-Link DIR-885L
  - DT support for ARM RealView PB1176 and PB11MPCore
  - Google Nexus 7
  - Homlet v2
  - Itead Ibox
  - Lamobo R1
  - LG Optimus Black
  - Logicpd dm3730
  - Raspberry Pi Model A
 
 Other changes include
  - Lots of updates for Qualcomm APQ8064, MSM8974 and others
  - Improved support for Nokia N900 and other OMAP machines
  - Common clk support for lpc32xx
  - HDLCD display on ARM
  - Improved stm32f429 support
  - Improved Renesas device support, r8a779x and others
  - Lots of Rockchip updates
  - Samsung cleanups
  - ADC support for Atmel SAMA5D2
  - BCM2835 (Raspberry Pi) improvements
  - Broadcom Northstar Plus enhancements
  - OMAP GPMC rework
  - Several improvements for Atmel SAMA5D2 / Xplained
  - Global change to remove inofficial "arm,amba-bus" compatible string
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIVAwUAVu67PmCrR//JCVInAQIZlA//UV7DK8tHNvLCuHBX8MnW5xxljUWFCoFp
 Zsi9LJj+KDIE+rpY65n75+il+rT1ZcgaITzH+Qvaq75f51ZwW7HY5jHiPYsINa80
 oMtbdWlnpNIH48jD5yMKaDTE8md7lZ8tgA//6aw1doDx2LYX4D1QRG6XI1OC6E62
 OjlzXkTTe50Aowi6aMQz4PZQM89m09FT0aw/Qsokh0fcW8oXhXcJSlFgLF/tZUYs
 VU4oWshUX2/VW3ShXlAJdrItpdDIogwZtDS7xKXmk6AHfapLb7s4HuEOInqbeOa7
 QWTjtoVj6ZHyeVptyn6kj5+xOdL4bXAT4Kg2TctF1iv0I6XG8CKflNqOJt2wLR1M
 DP0VQXK0TmKCeI+vbRhniLRP7EPYp4N9KFAe6M6aVP3nKYX81EqWdtPjuwp7GxAC
 sIGad2ocynKW4Eb4xOD2/5EwzkhwHv7SPQTCyCyQo8ILGN5MOSBZJOC1kXATTtbq
 u7LbOLyFMeWPJFYZyPxe79MwiX0dfJekrZYQ1tYL3MEQqQNmbY6+r+6QLMhT+iSj
 SE1oBaAReOuZUquiBEt398OvdfQ/n+F5BasKKCojXuhueNO3+rY7mT5X/vmOs2eh
 CUpfl766CixaZmF6p8es1Qeu64ASODbPiOw3Dv5Cgwcbfy/C3b3ccty0zazlOaNJ
 Sm6VXU3RavA=
 =RLUc
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM DT updates from Arnd Bergmann:
 "These are all the updates to device tree files for 32-bit platforms,
  plus a couple of related 64-bit updates:

  New SoC support:
   - Allwinner A83T
   - Axis Artpec-6 SoC
   - Mediatek MT7623 SoC
   - TI Keystone K2G SoC
   - ST Microelectronics stm32f469

  New board or machine support:
   - ARM Juno R2
   - Buffalo Linkstation LS-QVL and LS-GL
   - Cubietruck plus
   - D-Link DIR-885L
   - DT support for ARM RealView PB1176 and PB11MPCore
   - Google Nexus 7
   - Homlet v2
   - Itead Ibox
   - Lamobo R1
   - LG Optimus Black
   - Logicpd dm3730
   - Raspberry Pi Model A

  Other changes include
   - Lots of updates for Qualcomm APQ8064, MSM8974 and others
   - Improved support for Nokia N900 and other OMAP machines
   - Common clk support for lpc32xx
   - HDLCD display on ARM
   - Improved stm32f429 support
   - Improved Renesas device support, r8a779x and others
   - Lots of Rockchip updates
   - Samsung cleanups
   - ADC support for Atmel SAMA5D2
   - BCM2835 (Raspberry Pi) improvements
   - Broadcom Northstar Plus enhancements
   - OMAP GPMC rework
   - Several improvements for Atmel SAMA5D2 / Xplained
   - Global change to remove inofficial "arm,amba-bus" compatible
     string"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (350 commits)
  ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus"
  ARM: dts: artpec: dual-license on artpec6.dtsi
  ARM: dts: ux500: add synaptics RMI4 for Ux500 TVK DT
  arm64: dts: juno/vexpress: fix node name unit-address presence warnings
  arm64: dts: foundation-v8: add SBSA Generic Watchdog device node
  ARM: dts: at91: sama5d2 Xplained: add leds node
  ARM: dts: at91: sama5d2 Xplained: add user push button
  ARM: dts: at91: sama5d2 Xplained: set pin muxing for usb gadget and usb host
  ARM: dts: stm32f429: Enable Ethernet on Eval board
  ARM: dts: omap3-sniper: TWL4030 keypad support
  Revert "ARM: dts: DRA7: Add dt nodes for PWMSS"
  ARM: dts: dm814x: dra62x: Disable wait pin monitoring for NAND
  ARM: dts: dm814x: dra62x: Fix NAND device nodes
  ARM: dts: stm32f429: Add Ethernet support
  ARM: dts: stm32f429: Add system config bank node
  ARM: dts: at91: sama5d2: add nand0 and nfc0 nodes
  ARM: dts: at91: sama5d2: add dma properties to UART nodes
  ARM: dts: at91: sama5d2 Xplained: Correct the macb irq pinctrl node
  ARM: dts: exynos: Don't overheat the Odroid XU3-Lite on high load
  ARM: dts: exynos: Add cooling levels for Exynos5422/5800 CPUs
  ...
2016-03-20 15:15:48 -07:00
Masahiro Yamada
2ef7d5f342 ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus"
The compatible string "simple-bus" is well defined in ePAPR, while
I see no documentation for the "arm,amba-bus" arnywhere in ePAPR or
Documentation/devicetree/.

DT is also used by other projects than Linux kernel.  It is not a
good idea to rely on such an unofficial binding.

This commit
  - replaces "arm,amba-bus" with "simple-bus"
  - drops "arm,amba-bus" where it is used along with "simple-bus"

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-03-12 17:40:34 -08:00
Thor Thayer
d31e2e846b ARM: dts: Add Altera L2 Cache and OCRAM EDAC entries
Add the device tree entries and bindings needed to support the Altera L2
cache and On-Chip RAM EDAC. This patch relies upon an earlier patch to
declare and setup On-chip RAM properly:

  8b907c8b62 ("arm: dts: socfpga: Add OCRAM node")

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: galak@codeaurora.org
Cc: grant.likely@linaro.org
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: ijc+devicetree@hellion.org.uk
Cc: Kumar Gala <galak@codeaurora.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-doc@vger.kernel.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: m.chehab@samsung.com
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Russell King <linux@arm.linux.org.uk>
Link: http://lkml.kernel.org/r/1455132384-17108-2-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>
2016-02-11 12:29:38 +01:00
Marek Vasut
91f69147d6 ARM: socfpga: dts: Enable MMC support at correct place in the DT
The socfpga.dtsi explicitly enabled MMC support, but not all boards are
equiped with an MMC card. There are setups which only have QSPI NOR.
Therefore, disable the MMC support on socfpga.dtsi level and enable it
on per-board basis.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alan Tull <atull@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Thor Thayer <tthayer@altera.com>
Cc: Vince Bridgers <vbridgers2013@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-21 00:44:21 -06:00
Olof Johansson
64aa1fe183 SoCFPGA dts cleanup for v4.4
- Re-order DTS nodes into correct alphabetical order
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJWIQUIAAoJEBmUBAuBoyj0/4EQAJ/qm7dW4n7Ma+rfjKUiXvYl
 KvK7ZOV7Tpou/uEv15LJxSmElGweVdx8que8o7MPOsa6fBj52TSP1YymoeLeblN2
 Ho3TVwSn2GKfUsvREr65UbEIG5MQcwKuC0aR5ReFvcw6YFwr0te6ZmO2xeaDzSau
 +qUmA1YCKGRPWP/vgUZ/bvW0QoR6AM6wlhMzosbDwHFiU5z2+FrV7gb95dyIIC2I
 eSTHWHRMAxFlNKDqy3CDnSV5r9n/5DzNvuuaqe1wmQ+M15KjLb03q+Ro7M3Rd0Vb
 NK8v+ECJH7bhgXRz4SXJqCBOE24mMmQPaG5G8Wu9ugbw0rX9TCyEFBpMDEm4jbnR
 TpAaQCrgMreXd4t44KRLG1uBm6MC9hrKRt4ShnYoMeaP+MuMQShIsbLTpMEpKCJw
 tpH9hC3eWmGHuVQ0KjwazopVRTDNq0Rnbt0C0z7WrYz+0XPpmRJvlOVa1e7BeRdM
 v/N0kzc//NOhrrXhFGUzfgAzlGnTBCTqfgnDmsyo68D+2iTq3yp3JPpM6owZNxQY
 MROlx9v3qv5ZbhqpSHcpjLnG1pB14ZmYGn55clsCUhCp38uciUuw1nJVFXYOBGHz
 L1AtwrjZ+lsNzgNkmsYLcTuuQWRvaakvcz2ri1Vjf+dEmx+Pi1vxcEqwfIGWDJZU
 KiA9aGVItcy4IVZ9uo5i
 =r89u
 -----END PGP SIGNATURE-----

Merge tag 'socfpga_for_v4.4_cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt

SoCFPGA dts cleanup for v4.4
- Re-order DTS nodes into correct alphabetical order

* tag 'socfpga_for_v4.4_cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: socfpga: dts: sort nodes alphabetically

Signed-off-by: Olof Johansson <olof@lixom.net>
2015-10-22 10:08:46 -07:00
Steffen Trumtrar
0cdbec626e ARM: socfpga: dts: sort nodes alphabetically
The sorting policy for this file is alphabetically.
Reorder all nodes, that are out of place.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-10-16 08:39:22 -05:00
Alan Tull
ebb251030b ARM: socfpga: dts: add fpga manager
Add FPGA manager to device tree for SoCFPGA.

Signed-off-by: Alan Tull <atull@opensource.altera.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-10-15 22:28:08 -05:00
Olof Johansson
93621d7037 SoCFPGA DTS updates for v4.3, take 2
- Add DTS property "altr,modrst-offset" for reset driver to
   use
 - Add updated reset defines for the reset driver
 - Add reset property for EMACs on Arria10
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJVyBZjAAoJEBmUBAuBoyj0IWEP/jlmY2g+/lloIRI7Yu49wncy
 xOnFX5+1N6NoKaPvSiNO9w2i4QMMw9nCs/+UccQqbjiOS2ggFuU12ODxSw91PadI
 FbDuMgsjXzeCcUK4p9sv+S3YK0FnajLuuB4EI9UhCn1nOnGi8Qs6QKKLnwwCvF+X
 1JB5cWcEz48SRl9p1K7ZmxvBJIjrhghl16sIBfNPWNzin+yjDBCvf2qtLJyzMz+z
 bG+Q3aztrr0vtt7EgEUNaeEZHmseuKtFVLFzL+d4L/HtpnczcNNmbhZDjZZuZjmc
 1jLMHZO7/W28njkmU4rYlQPeA4skKn1/a0BQ6S/UEC/RBNsFgkRGBgfsloslofuO
 kSaTW02g1ekxRPnZZNU+iqFZ3zHTbq609aCF/x48vbl5Ti6xB+RH5g7XGJSxFeRC
 4aEIMaLxyrCTkqN2bh6I4ABLAJnzD4+IcofnLioLiDJOlo0BqEI0mh9KMBHDBoKM
 uvltqwaVuWdMxzJue7SITAobsThkp3IS7ZU05JqKM/y1Qpu7DofplYTSQVN/oaWP
 3XS8M+ZMgAz9o8E67hv/54NX3PM8zw1fbBW1brCKeXdFqGhcww75aLlcfwBTLVaU
 hYDBRMMj2YkRCGjc2mFqlPozy4ovuqQ2ILKAh6/cqWiww1dV0hIw7mP50On7sLU8
 Ip/H2H5Q5OCk1but68iq
 =dKt6
 -----END PGP SIGNATURE-----

Merge tag 'socfpga_dts_for_v4.3_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt

SoCFPGA DTS updates for v4.3, take 2
- Add DTS property "altr,modrst-offset" for reset driver to
  use
- Add updated reset defines for the reset driver
- Add reset property for EMACs on Arria10

* tag 'socfpga_dts_for_v4.3_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: socfpga: dts: Add resets for EMACs on Arria10
  ARM: socfpga: dts: add "altr,modrst-offset" property
  dt-bindings: Add reset manager offsets for Arria10

Signed-off-by: Olof Johansson <olof@lixom.net>
2015-08-13 12:19:38 +02:00
Dinh Nguyen
1a94acf858 ARM: socfpga: dts: add "altr,modrst-offset" property
The "altr,modrst-offset" property represents the offset into the reset manager
that is the first register to be used by the driver to bring peripherals out
of reset.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-09 21:58:46 -05:00
Dinh Nguyen
2e4c7588f6 ARM: socfpga: dts: add osc1 as a possible parent for dbg_base_clk
The dbg_base_clk can also have osc1 has a parent.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-07-24 22:10:59 -05:00
Matthew Gerlach
7db85dd082 ARM: socfpga: dts: add missing clock gates to socfpga.dtsi
The gates for the clocks coming out of the sdram pll
were missing.  The change adds the missing nodes to
the device tree.

Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-07-22 15:17:20 -05:00
Dinh Nguyen
e9f9fe35f8 ARM: socfpga: dts: Fix gpio dts entry for the correct clock
The correct clock for the HPS gpio(s) should be the l4_mp_clk.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-07-22 13:17:12 -05:00
Dinh Nguyen
c5dab6e2c1 ARM: socfpga: dts: Correct the parent clock for l3_sp_clk and dbg_clk
The l3_sp_clk's parent should be the l3_mp_clk. This will account for
the extra divider that is present for the l3_mp_clk.

The dbg_clk's parent should be the dbg_at_clk. This will account for
the extra divider that is present for the dbg_at_clk.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-07-22 13:16:51 -05:00
Dinh Nguyen
2211a65862 ARM: dts: socfpga: enable the data and instruction prefetch for the l2 cache
Just in case the firmware did not enable data and instruction prefetch in
the L2 cache controller, we enable it in the kernel.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-07-20 10:06:11 -05:00
Kevin Hilman
da8d2b5d92 SoCFPGA updates for v4.2 part 3
- Add SCU node for Arria 10
 - Add enable-method for cpu nodes
 - Add SDRAM controller binding doc
 - Enable gpio-leds on SoCFPGA Socrates board
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJVbmTMAAoJEBmUBAuBoyj0iUsP/11m4hJBD2PT11MeXZZy4uWy
 ZzBGobhAWCcMKE/c00W+UpDZ18fXDs9oK3obAFOyDCvJgXAq0RTVZ6Vj5sdFqMHM
 inEnbHVQdYMwd0/WqBVoyNAluQMpSa3yg9YtcBCIzZCxX3DRWk18QAQycHczbxzp
 qM1Z8bXPSPBi5CCX0w68oxnOh+vN6dcz/CTXqMPpU+3Oo1b1h4yZXvLTp4rAboSn
 dr0OnnlD4LlAH0FhJkbVmrU++jeOaUZu491tUSm6EijK+a0ATNwHOn00OMdZYvrb
 AXvUXcjWwezaPx6b+XOAwYS2WFCSTWRcxUo+lmLB2UpzeHNAZp+V6hAtigVEq8au
 03619HXcbWfW2c2d+wDQ01xHA3t30rpWaVMWyf+UGMVoCKgDXYaNh3h5bwYIoUia
 hSqYACO/f3PkGlJrndGRuRMPaJKNE2ihaoJbHtzIBI5rcRnZ2RtRkdg6j6HWBdr4
 Um8Hsi+CJDtXBo4OoVYl8jqCp2Qh7Zq1bKQ99HYFDinQtxYr+Q4G5PsBc/UHDwC0
 0PBJUyneWeJlemKoewR6RRtx0d9IkA02T1ijaaOVjtYp9pU7JDMdkMtHbSgqnnNd
 bFWU49HHDzF92sOEu0wRT5SOlFp3VO2hs/jGWWDlWXrA1iJujuHFofuTEfFrlwLJ
 n5aKtM8w1JJfzWQ06/zz
 =nAUL
 -----END PGP SIGNATURE-----

Merge tag 'socfpga_dts_for_v4.2_part_3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt

SoCFPGA updates for v4.2 part 3
- Add SCU node for Arria 10
- Add enable-method for cpu nodes
- Add SDRAM controller binding doc
- Enable gpio-leds on SoCFPGA Socrates board

* tag 'socfpga_dts_for_v4.2_part_3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: socfpga: socrates: add gpio-leds
  ARM: socfpga: socrates: enable gpio0/1
  ARM: socfpga: dts: add sdram controller dt binding doc
  ARM: socfpga: dts: add enable-method property for cpu nodes
  ARM: socfpga: dts: add the a9-scu node for arria10
2015-06-10 15:40:59 -07:00
Dinh Nguyen
ebbce1bbc4 ARM: socfpga: dts: add enable-method property for cpu nodes
Add the enable-method property for the cpu node on socfpga.dtsi and
socfpga_arria10.dtsi. This is for CPU_METHOD_OF_DECLARE to use to enable
the secondary core.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-06-02 14:18:15 -05:00
Arnd Bergmann
2cac46a415 SoCFPGA update for v4.2 part 2
- Add a DTS node for the A9 SCU
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABAgAGBQJVU1L4AAoJEBmUBAuBoyj05zEP/02UJVcqCHT2P/z/1XJnIwed
 hZgO0Oej4ZEc+futAIx6IeMEkgNoIDZX1rdijiQe3Uv2QK8niC7R8yOjwcZrM8jZ
 ws/jyKWpCBsV0J+lzZevxa3DpxMHPmcx0W9gAqYpikrwgbXt0Dyy62CQkp+XKZ5d
 mluxSEbkSlORddzD8eQbM1yuVlFGg9RAzdwaeZk4j6x+vq2Zk+jEwq5EKLBIiO/U
 kGwu/mEryiWl+lzqV7Nlagt4uLASsT5ZxEjr4zUx9ddDTJo4mqStqONdDPMTdf9h
 0qzHrWa9mMhI7RLoOWBuvTEcvEVPSRNhVfo6cY8ZnQcZ/V5tj4sG3jAPUFXkFSMd
 iZW3mud5P45ugbKiumR5R7ve3t6yxhvNqWH9FZqfnlPPNXtCaUqBGB772A0Xr2Hz
 mRPu2Vl9cjmGdrWQHqF5sViPdm52E8Het3/HO0ccsx4aoH+jhgGKeqmiK779EKTA
 lA0NPBrL5PRzjNacNwnR7RxtLpcISf5CbsV0ojiIDtB8x11TCg1Zct+ogeE03luT
 YpTNuOgTEg7Gy4oa6LPPXahUS+6RffHmASjlt15xaWx/x5MaCXTyk3H4JtSumDiL
 blFzdQmNUcO2YpggSgyS0UzRFyqYJIRPq7lHKMJz5NMfaHVzu4VzoDKmJVo4zG2T
 BftEOP7ROh5wq1HkWJs3
 =23ne
 -----END PGP SIGNATURE-----

Merge tag 'socfpga_dts_for_v4.2_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt

Merge "SoCFPGA update for v4.2 part 2" from Dinh Nguyen:
- Add a DTS node for the A9 SCU

* tag 'socfpga_dts_for_v4.2_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: socfpga: dts: add the a9-scu node
2015-05-13 17:47:47 +02:00
Dinh Nguyen
8508452e57 ARM: socfpga: dts: add the a9-scu node
Add the dts node for the A9 SCU.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-13 08:30:03 -05:00
Vince Bridgers
c01e8cdb7b ARM: socfpga: dts: Add tx-fifo-depth and rx-fifo-depth properties
Add tx-fifo-depth and rx-fifo-depth devicetree properties for socfpga
stmmac. These devicetree properties will be used to configure certain
features of the stmmac on the socfpga.

Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11 13:15:00 -05:00
Dinh Nguyen
5459f9abe2 ARM: socfpga: dts: Add a clock node for sdmmc CIU
The CIU(Card Interface Unit) get its clock from the sdmmc_clk_divided clock
which is used to clock the card. The sdmmc_clk_divided clock is the sdmmc_clk
passed through a fixed divider of 4. This patch adds the sdmmc_clk_divided
node and makes the sdmmc_clk it's parent.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: renamed ciu_clk to sdmmc_clk_divided
2015-05-11 13:14:59 -05:00
Mark James
1ac31de744 ARM: socfpga: dts: fix spi1 interrupt
The socfpga.dtsi currently has the wrong interrupt number set for SPI master 1
Trying to use the master without this change results in the kernel boot
process waiting forever for an interrupt that will never occur while
attempting to probe any slave devices configured in the device tree as being
under SPI master 1.

The change works for the Cyclone V, and according to the Arria 5 handbook
should be good there too.

Signed-off-by: Mark James <maj@jamers.net>
Acked-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-03-19 10:51:15 -05:00
Steffen Trumtrar
78c03c7af8 ARM: socfpga: fix uart DMA binding error
socfpga.dtsi is missing the DMA channels for the uart nodes.
This will produce the following errors:

	of_dma_request_slave_channel: dma-names property of node '/soc/serial0@ffc02000' missing or empty
	ttyS0 - failed to request DMA

Provide the correct DMA channels to fix this.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-03-04 13:03:04 -06:00
Arnd Bergmann
d1940cbd46 SoCFPGA DTS updates for v3.19
- Add DTS support for a new chip in the SOCFPGA family, the Arria 10.
 - Enable watchdog node.
 - Add SPI nodes.
 - Add the OCRAM node.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABAgAGBQJUbslHAAoJEBmUBAuBoyj0R0EP/2nF0rHzM7s9TivfLLnknwu5
 UCPFkuB9DFsfBn6XauAjuioY2/K1yugU5Xh4IyKgXfOdUYDRxT18FzltJl8Tk25h
 yx7tm5DlukQ68sdKgcSNMXgH1VNR0zV0k0P1PBjdB2W78DGpQTi5KUDb29a6wk7a
 g7pYnhrzlKgLVfAazhxsD/N2o+ImxFvsVpdQBxi4/oR5zgYEoLbv6i4CKzPBrPv9
 T/v4MP9E9p8tviSpuj99plMZN8w4uBQ7Clc1xCrh8y+KvKRjViFnUZPXFZHnPENs
 XnqPuDyHvMxYEKQgrSDO5GQ4USUFM+TTSKGSobkCYYmaw53F+g6FxYTCDkubyCW/
 v9OAH5t3lQf3P8SyHdZ2hhGH4EAoTzxC7uYJes/JdjxZgBHpfZv/bj3MGMI6r+w8
 5rUF8ueipQjVOVJtr2YkkGM9U0CFw1dBGFBGk3eMrXPV418fcrIJZkRoDwdnvpQj
 I8sG1rEoZHAbPOu2ejyxVAlvHF5uy7HAXpt3ktekJV70DtcNTUpREbMso7fksEzL
 xufDmwe/BjUzJBFsVhZZLULUlHt1rZLYHXOn/NdfBEWluT4+uhc+1DcsCsc99Bhe
 AIUMX+ngDpWZazxRGhzlOxdzi9dhuN1pFtJlXuj2wBhVNdivac4OjgBgFYWu9lpZ
 cC/byWHasY2Kyyi1+tDd
 =sh1R
 -----END PGP SIGNATURE-----

Merge tag 'socfpga_dts_updates_for_v3.19' of git://git.rocketboards.org/linux-socfpga-next into next/dt

Pull "SoCFPGA DTS updates for v3.19" from Dinh Nguyen:

- Add DTS support for a new chip in the SOCFPGA family, the Arria 10.
- Enable watchdog node.
- Add SPI nodes.
- Add the OCRAM node.

* tag 'socfpga_dts_updates_for_v3.19' of git://git.rocketboards.org/linux-socfpga-next:
  arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC
  arm: dts: socfpga: enable watchdog for socfpga platform
  arm: dts: socfpga: Add SPI nodes to SOCFPGA DT.
  arm: dts: socfpga: Add OCRAM node

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-21 13:31:06 +01:00
Thor Thayer
ba6b96b3e9 arm: dts: socfpga: Add SPI nodes to SOCFPGA DT.
Add 2 SPI nodes to SOCFPGA device tree.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-11-20 23:08:36 -06:00
Dinh Nguyen
8b907c8b62 arm: dts: socfpga: Add OCRAM node
Add a 64KB ocram node for SOCFPGA.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-11-20 23:08:32 -06:00
Dinh Nguyen
d11ac1d2d5 ARM: dts: socfpga: rename gpio nodes
Since the Synopsys GPIO IP can support multiple ports of varying widths, it
would make more sense to have the GPIO node DTS entry as this:

gpio0: gpio@ff708000{
	porta{
	};
};

Also, this is documented in the snps-dwapb-gpio.txt.

Suggested-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-10-22 20:59:07 -05:00
Thor Thayer
75a41826e2 arm: dts: Add Altera SDRAM EDAC bindings & devicetree entries.
Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
project.

There was a discussion thread on whether this driver should be an mfd driver
or just make use of syscon, which is already a mfd. Ultimately, the
decision to use a simple syscon interface was reached.[1]

[1] https://lkml.org/lkml/2014/7/30/514

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
[dinguyen] cleaned-up commit header and remove version history.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-04 10:15:52 -05:00
Linus Torvalds
d4e1f5a14e ARM: SoC device-tree changes for 3.17
Unlike the board branch, this keeps having large sets of changes for
 every release, but that's quite expected and is so far working well.
 
 Most of this is plumbing for various device bindings and new platforms,
 but there's also a bit of cleanup and code removal for things that
 are moved from platform code to DT contents (some OMAP clock code in
 particular).
 
 There's also a pinctrl driver for tegra here (appropriately acked),
 that's introduced this way to make it more bisectable.
 
 I'm happy to say that there were no conflicts at all with this branch
 this release, which means that changes are flowing through our tree as
 expected instead of merged through driver maintainers (or at least not
 done with conflicts).
 
 There are several new boards added, and a couple of SoCs. In no particular
 order:
 
 * Rockchip RK3288 SoC support, including DTS for a dev board that they
   have seeded with some community developers.
 * Better support for Hardkernel Exynos4-based ODROID boards.
 * CCF conversions (and dtsi contents) for several Renesas platforms.
 * Gumstix Pepper (TI AM335x) board support
 * TI eval board support for AM437x
 * Allwinner A23 SoC, very similar to existing ones which mostly has
   resulted in DT changes for support. Also includes support for an Ippo
   tablet with the chipset.
 * Allwinner A31 Hummingbird board support, not to be confused with the
   SolidRun i.MX-based Hummingboard.
 * Tegra30 Apalis board support
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.14 (GNU/Linux)
 
 iQIcBAABAgAGBQJT5DqvAAoJEIwa5zzehBx3tm0QAJk8zFyZuMhUPz6SoZTtO9ti
 zojZ2218oqLRDfLSYdJx/3QE7gb2ef0e2S6FrthecdAY8sqZzDddL7M/cCf1WSgy
 +D4dD1UEq+W/hOeEwIWyo3GR/71exgo/LMTIw8HOJh5c9fanQ2wNChNetCgh8b4u
 sVOEMmP1UTO2W7mH9cCRhWXFifBNi0yNl1QBYnLPzM2CbSEa4qQRarTn/94NSEiY
 U9XgzysklvYEW/30wcEkz8ZonKbJrtP+zEjODU4wN/muhHECeTehDrkJq0WEK/3C
 3ptko2xQGURNaLM6HVvQS9qkXxyhCeZxqkELpjkjjM+YPFN8wdHu7gDctGZlDr39
 LQ2pZF6K8vaFvxp3UM2wzdDeoNi3rxguzpFoBmfRP5NWguDrOvjT3w8W4hO9q04J
 8SqMGca0av9myHmeSjtRRg5rmcC3kBbOgSN6siVJ8W80rHT7tnFjl6eCawDreQzn
 szFzGaOOUnf/kJ/00vzm1dCuluowFPdSYgW3aamZhfkqu2qYJ8Ztuooz5eZGKtex
 zlUfKtpL26gnamoUT42K7E8J968AjHjUc/zimwYzIgHCzTTApYGJQcbD/Y28b8QH
 gTvhRxP+0kFb+NNq4IHStVMvJrFOPvzOHXcL8x07HqTxrl7W4XoW+KJxCJOk433W
 5NJ9s4tEmiTRMtFL1kv6
 =xxlY
 -----END PGP SIGNATURE-----

Merge tag 'dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC device-tree changes from Olof Johansson:
 "Unlike the board branch, this keeps having large sets of changes for
  every release, but that's quite expected and is so far working well.

  Most of this is plumbing for various device bindings and new
  platforms, but there's also a bit of cleanup and code removal for
  things that are moved from platform code to DT contents (some OMAP
  clock code in particular).

  There's also a pinctrl driver for tegra here (appropriately acked),
  that's introduced this way to make it more bisectable.

  I'm happy to say that there were no conflicts at all with this branch
  this release, which means that changes are flowing through our tree as
  expected instead of merged through driver maintainers (or at least not
  done with conflicts).

  There are several new boards added, and a couple of SoCs.  In no
  particular order:

   - Rockchip RK3288 SoC support, including DTS for a dev board that
     they have seeded with some community developers.
   - Better support for Hardkernel Exynos4-based ODROID boards.
   - CCF conversions (and dtsi contents) for several Renesas platforms.
   - Gumstix Pepper (TI AM335x) board support
   - TI eval board support for AM437x
   - Allwinner A23 SoC, very similar to existing ones which mostly has
     resulted in DT changes for support.  Also includes support for an
     Ippo tablet with the chipset.
   - Allwinner A31 Hummingbird board support, not to be confused with
     the SolidRun i.MX-based Hummingboard.
   - Tegra30 Apalis board support"

* tag 'dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (334 commits)
  ARM: dts: Enable USB host0 (EHCI) on rk3288-evb
  ARM: dts: add rk3288 ehci usb devices
  ARM: dts: Turn on USB host vbus on rk3288-evb
  ARM: tegra: apalis t30: fix device tree compatible node
  ARM: tegra: paz00: Fix some indentation inconsistencies
  ARM: zynq: DT: Clarify Xilinx Zynq platform
  ARM: dts: rockchip: add watchdog node
  ARM: dts: rockchip: remove pinctrl setting from radxarock uart2
  ARM: dts: Add missing pinctrl for uart0/1 for exynos3250
  ARM: dts: Remove duplicate 'interrput-parent' property for exynos3250
  ARM: dts: Add TMU dt node to monitor the temperature for exynos3250
  ARM: dts: Specify MAX77686 pmic interrupt for exynos5250-smdk5250
  ARM: dts: cypress,cyapa trackpad is exynos5250-Snow only
  ARM: dts: max77686 is exynos5250-snow only
  ARM: zynq: DT: Remove DMA from board DTs
  ARM: zynq: DT: Add CAN node
  ARM: EXYNOS: Add exynos5260 PMU compatible string to DT match table
  ARM: dts: Add PMU DT node for exynos5260 SoC
  ARM: EXYNOS: Add support for Exynos5410 PMU
  ARM: dts: Add PMU to exynos5410
  ...
2014-08-08 11:16:58 -07:00
Vince Bridgers
ea6856e352 ARM: socfpga: Add socfpga Ethernet filter attributes entries
This patch adds socfpga Ethernet filter attributes for multicast
and unicast filters per Synopsys Ethernet IP configuration chosen
by Altera for the Cyclone 5 and Arria SOC FPGAs.

Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-07-31 14:13:29 -07:00
Vince Bridgers
dc8fbed5d9 ARM: socfpga: Add missing #reset-cells to socfpga device tree
add #reset-cells to socfpga.dtsi. This was missing from the
latest updates and caused the socfpga reset controller to fail
to load like so:

ffd05000.rstmgr: /soc/rstmgr@ffd05000 missing #reset-cells property
probe of ffd05000.rstmgr failed with error -22

Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-14 21:39:54 -07:00
Steffen Trumtrar
a98b605719 ARM: socfpga: dts: add watchdog0+1
The SoCFPGA has two watchdog timers. Add them to the dtsi.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
[dinh: modified patch to have correct irq flag]
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-05-22 16:45:31 -05:00
Sebastian Andrzej Siewior
6ec08c71da ARM: dts: socfpga: add gpio pieces
The cycloneV has three gpio controllers, each one with 29 gpios. This patch
adds the three controller with the gpio driver which is now sitting the
gpio tree.

Cc: devicetree@vger.kernel.org
Acked-by: Alan Tull <atull@altera.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-05-22 16:32:05 -05:00
Dinh Nguyen
8cb289ed60 ARM: socfpga: dts: Add div-reg to the main_pll clocks
The mpu_clk, main_clk, and dbg_base_clk outputs from the main PLL go through a
pre-divider. Update socfpga.dtsi to represent those dividers for these
clocks.

Re-use the "div-reg" property that was used for the socfpga-gate-clock as this
is the same thing. Also update the documentation.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-05-05 22:33:18 -05:00
Steffen Trumtrar
16fb4f8bd5 ARM: socfpga: dts: add reset-controller
Add the necessary #reset-cells property to the rst-mgr node and
provide a header-file with all possible resets specified.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-05-05 22:33:18 -05:00
Dinh Nguyen
1403250b6b ARM: socfpga: dts: Add DTS entries for USB
Update all the SOCFPGA DTS files with USB entries.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-05-05 22:33:16 -05:00
Dinh Nguyen
bd785efda7 ARM: socfpga: dts: Remove hard coded clock-frequency property
The timers and uart can get their clock frequencies using the common clock
driver.

Reviewed-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-05-05 22:33:15 -05:00