Given appropriate devicetree bindings, this driver registers a
pm_power_off function to set a GPIO line high/low to power down
your board.
Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by:Simon Baatz <gmbnomis@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Based on previous work by Michael Walle and Jason Cooper.
Made their work actually work, which required added interrupt from DT
and auxdata, along with setting the dma_mask, which DT does not
currently do.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Pulling in a newer version of the depend branch from the gpio tree,
since there was some randconfig breakage introduced at the version we
had, and we want to keep those things as bisectable as possible. It's
not bad enough to warrant a rebase though, so there'll be a window of
exposure to this.
* depends/gpio-devel:
gpio: SPEAr: add spi chipselect control driver
gpio: gpio-max710x: Support device tree probing
gpio: twl4030: Use only TWL4030_MODULE_LED for LED configuration
gpio: tegra: read output value when gpio is set in direction_out
gpio: pca953x: Add compatible strings to gpio-pca953x driver
gpio: pca953x: Register an IRQ domain
gpio: mvebu: Set free callback for gpio_chip
gpio: tegra: Drop exporting static functions
gpio: tegra: Staticize non-exported symbols
gpio: tegra: fix suspend/resume apis
gpio-pch: Set parent dev for gpio chip
gpio: em: Fix build errors
Signed-off-by: Olof Johansson <olof@lixom.net>
This device doesn't have a pdata definition for legacy boards, and
unless anyone need to control the reset GPIO, it's not worth adding one.
So this feature is only available to DT users for now.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Previously a generic binding 'i2c-client-wake' was created which
enabled I2C devices to register themselves as wake-up devices.
This binding was later over-thrown by 'wakeup-source'. The STMPE
driver was fixed-up, but the document was neglected. This patch
aims to rectify that.
Cc: Samuel Ortiz <sameo@linux.intel.com>
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This patch allows the STMPE Touchscreen driver to be successfully probed and
initialised when Device Tree support is enabled. Bindings are mentioned in
Documentation too.
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Add support for encoding PWM properties in bit encoded form with
of_pwm_xlate_with_flags() function support. Platforms require platform
specific PWM properties has to populate in 3rd cell of the pwm-specifier
and PWM driver should also set .of_xlate support with this function.
Currently PWM property polarity encoded in bit position 0 of the third
cell in pwm-specifier.
Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Add support for PWM chips present on SPEAr platforms. These PWM
chips support 4 channel output with programmable duty cycle and
frequency.
More details on these PWM chips can be obtained from relevant
chapter of reference manual, present at following[1] location.
1. http://www.st.com/internet/mcu/product/251211.jsp
Cc: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Vipin Kumar <vipin.kumar@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
In current code the ethernet PLL is not handled correctly. The PLL runs at 500MHz
and has different outputs. Only the enet reference clock is implemented. This
patch changes the PLL so that it outputs 500MHz and adds the additional outputs
as dividers. This now matches the datasheet which says:
> This PLL synthesizes a low jitter clock from 24 MHz reference clock.
> The PLL outputs a 500 MHz clock. The reference clocks generated by this PLL are:
> • Ref_PCIe = 125 MHz
> • Ref_SATA = 100 MHz
> • Ref_ethernet, which is configurable based on the PLL_ENET[1:0] register field.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
In recent reference manuals the PLLs were renumbered. PLL8 now is
PLL6 and vice versa. Change the code according to the reference
manual to avoid confusion.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Similarly as it was done for mx6q, use a DT lookup in order to make maintainance
task for the clock devices easier.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This will allow to use gpio for chip select with no modification in the
driver binding
When use the cs-gpios, the gpio number will be passed via the cs_gpio field
and the number of chip select will automatically increased with max(hw cs, gpio cs).
So if for example the controller has 2 CS lines, and the cs-gpios
property looks like this:
cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>;
Then it should be configured so that num_chipselect = 4 with the
following mapping:
cs0 : &gpio1 0 0
cs1 : native
cs2 : &gpio1 1 0
cs3 : &gpio1 2 0
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: spi-devel-general@lists.sourceforge.net
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
[grant.likely: fixed up type of cs count so min() can do type checking]
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
The purpose of this patch set is to add hardware I/O Coherency support
for Armada 370 and Armada XP. Theses SoCs come with an unit called
coherency fabric. A beginning of the support for this unit have been
introduced with the SMP patch set. This series extend this support:
the coherency fabric unit allows to use the Armada XP and the Armada
370 as nearly coherent architectures.
The third patches enables this new feature and register our own set
of DMA ops, to benefit this hardware enhancement.
The first patches exports a dma operation function needed to register
our own set of dma ops.
The second patch introduces a new flag for the address decoding
configuration in order to be able to set the memory windows as
shared memory.
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Merge tag 'marvell-hwiocc-for-3.8' of git://github.com/MISL-EBU-System-SW/mainline-public into mvebu/everything
Add hardware I/O coherency support for Armada 370/XP
The purpose of this patch set is to add hardware I/O Coherency support
for Armada 370 and Armada XP. Theses SoCs come with an unit called
coherency fabric. A beginning of the support for this unit have been
introduced with the SMP patch set. This series extend this support:
the coherency fabric unit allows to use the Armada XP and the Armada
370 as nearly coherent architectures.
The third patches enables this new feature and register our own set
of DMA ops, to benefit this hardware enhancement.
The first patches exports a dma operation function needed to register
our own set of dma ops.
The second patch introduces a new flag for the address decoding
configuration in order to be able to set the memory windows as
shared memory.
The purpose of this series is to add the SMP support for the Armada XP
SoCs. Beside the SMP support itself brought by the last 3 commits,
this series also adds the support for the coherency fabric unit and
the power management service unit.
The coherency fabric is responsible for ensuring hardware coherency
between all CPUs and between CPUs and I/O masters. This unit is also
available for Armada 370 and will be used in an incoming patch set
for hardware I/O cache coherency.
The power management service unit is responsible for powering down and
waking up CPUs and other SOC units.
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Merge tag 'marvell-armadaxp-smp-for-3.8' of git://github.com/MISL-EBU-System-SW/mainline-public into mvebu/everything
SMP support for Armada XP
The purpose of this series is to add the SMP support for the Armada XP
SoCs. Beside the SMP support itself brought by the last 3 commits,
this series also adds the support for the coherency fabric unit and
the power management service unit.
The coherency fabric is responsible for ensuring hardware coherency
between all CPUs and between CPUs and I/O masters. This unit is also
available for Armada 370 and will be used in an incoming patch set
for hardware I/O cache coherency.
The power management service unit is responsible for powering down and
waking up CPUs and other SOC units.
From Michal Simek:
This branch depends on arm-soc devel/debug_ll_init branch because
we needed Rob's "ARM: implement debug_ll_io_init()"
(sha1: afaee03511ba8002b26a9c6b1fe7d6baf33eac86)
patch.
This branch also depends on zynq/dt branch because of previous major
zynq changes.
zynq/cleanup branch is subset of zynq/dt.
* 'zynq/multiplatform' of git://git.monstr.eu/linux-2.6-microblaze:
ARM: zynq: Remove all unused mach headers
ARM: zynq: add support for ARCH_MULTIPLATFORM
ARM: zynq: make use of debug_ll_io_init()
ARM: zynq: remove TTC early mapping
ARM: zynq: add clk binding support to the ttc
ARM: zynq: use zynq clk bindings
clk: Add support for fundamental zynq clks
ARM: zynq: dts: split up device tree
ARM: zynq: Allow UART1 to be used as DEBUG_LL console.
ARM: zynq: dts: add description of the second uart
ARM: zynq: move arm-specific sys_timer out of ttc
zynq: move static peripheral mappings
zynq: remove use of CLKDEV_LOOKUP
zynq: use pl310 device tree bindings
zynq: use GIC device tree bindings
Add/add conflict in arch/arm/Kconfig.debug.
Signed-off-by: Olof Johansson <olof@lixom.net>
From Kukjin Kim:
Here is Samsung DT for v3.8 and this is including DT for EXYNOS4X12
SoC, SMDK4412 board, pinctrl for exynos4x12, TMU, MFC, SATA and SATA
PHY.
As I commented on [4/7], this branch merged pinctrl/samsung to support
pinctrl for exynos4x12 without useless merge conflicts.
* 'next/dt-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (32 commits)
ARM: EXYNOS: DT Support for SATA and SATA PHY
ARM: dts: Remove broken-voltage property from sdhci node for exynos4210-trats
ARM: dts: Add node for touchscreen for exynos4210-trats
ARM: dts: Add node for touchscreen voltage regulator for exynos4210-trats
ARM: dts: Add node for i2c3 bus for exynos4210-trats
ARM: dts: Add nodes for GPIO keys available on Trats
ARM: dts: Update for pinctrl-samsung driver for exynos4210-trats
ARM: dts: Add nodes for pin controllers for exynos4x12
pinctrl: samsung: Add support for EXYNOS4X12
gpio: samsung: Skip registration if pinctrl driver is present on EXYNOS4X12
ARM: EXYNOS: Skip wakeup-int setup if pinctrl driver is used on EXYNOS4X12
ARM: dts: add board dts file for EXYNOS4412 based SMDK board
ARM: dts: Add support for EXYNOS4X12 SoCs
ARM: EXYNOS: Add devicetree node for TMU driver for exynos5
ARM: EXYNOS: Add devicetree node for TMU driver for exynos4
ARM: EXYNOS: Add MFC device tree support
ARM: dts: Enable serial controllers on Origen and SMDKV310
Documentation: Update samsung-pinctrl device tree bindings documentation
pinctrl: samsung: Add GPIO to IRQ translation
pinctrl: exynos: Set pin function to EINT in irq_set_type of wake-up EINT
...
Add/add conflicts in:
arch/arm/boot/dts/exynos5250-smdk5250.dts
arch/arm/boot/dts/exynos5250.dtsi
arch/arm/mach-exynos/mach-exynos5-dt.c
Signed-off-by: Olof Johansson <olof@lixom.net>
From Maxime Ripard:
Here is a pull request to add the support for Allwinner A10 SoCs.
* sunxi/soc2:
ARM: sunxi: Add sunxi restart function via onchip watchdog
ARM: sunxi: Add sun4i and cubieboard support
ARM: sunxi: Add earlyprintk support for UART0 (sun4i)
ARM: sunxi: Restructure sunxi dts/dtsi files
Signed-off-by: Olof Johansson <olof@lixom.net>
From Kukjin Kim:
This includes supporting legacy i2c controller and ARM down clock
support for exynos5 and small changes.
[olof: It contains a dependency on samsung/hdmi for HDMI DT bindings, for some reason.]
* 'next/devel-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Clock settings for SATA and SATA PHY
ARM: EXYNOS: Add ARM down clock support
ARM: EXYNOS: Fix i2c suspend/resume for legacy controller
ARM: EXYNOS: Add aliases for i2c controller
ARM: EXYNOS: Setup legacy i2c controller interrupts
ARM: EXYNOS: removing exynos-drm device registration from non-dt platforms
ARM: EXYNOS: add clocks for exynos5 hdmi
ARM: dts: add device tree support for exynos5 hdmiddc
ARM: dts: add device tree support for exynos5 hdmiphy
ARM: dts: add device tree support for exynos5 mixer
ARM: dts: add device tree support for exynos5 hdmi
ARM: EXYNOS: Add dp clock support for EXYNOS5
ARM: SAMSUNG: call clk_get_rate for debugfs rate files
ARM: SAMSUNG: add clock_tree debugfs file in clock
Signed-off-by: Olof Johansson <olof@lixom.net>
From Kukjin Kim:
Here is Samsung DT for v3.8 and this is including DT for EXYNOS4X12
SoC, SMDK4412 board, pinctrl for exynos4x12, TMU, MFC, SATA and SATA
PHY.
As I commented on [4/7], this branch merged pinctrl/samsung to support
pinctrl for exynos4x12 without useless merge conflicts.
* samsung/pinctrl:
pinctrl: samsung: Update error check for unsigned variables
pinctrl: samsung: Add support for EXYNOS4X12
Documentation: Update samsung-pinctrl device tree bindings documentation
pinctrl: samsung: Add GPIO to IRQ translation
pinctrl: exynos: Set pin function to EINT in irq_set_type of wake-up EINT
pinctrl: samsung: Use per-bank IRQ domain for wake-up interrupts
pinctrl: samsung: Use one GPIO chip per pin bank
pinctrl: exynos: Use one IRQ domain per pin bank
pinctrl: samsung: Include bank-specific eint offset in bank struct
pinctrl: samsung: Hold pointer to driver data in bank struct
pinctrl: samsung: Match pin banks with their device nodes
ARM: dts: exynos4210-pinctrl: Add nodes for pin banks
pinctrl: samsung: Distinguish between pin group and bank nodes
pinctrl: samsung: Remove static pin enumerations
pinctrl: samsung: Assing pin numbers dynamically
pinctrl: samsung: Do not pass gpio_chip to pin_to_reg_bank
pinctrl: samsung: Detect and handle unsupported configuration types
From Kukjin Kim:
This is for adding support for DT based exynos5250 hdmi and it adds
device node for hdmi, mixer, hdmiphy and hdmiddc.
* 'next/hdmi-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: removing exynos-drm device registration from non-dt platforms
ARM: EXYNOS: add clocks for exynos5 hdmi
ARM: dts: add device tree support for exynos5 hdmiddc
ARM: dts: add device tree support for exynos5 hdmiphy
ARM: dts: add device tree support for exynos5 mixer
ARM: dts: add device tree support for exynos5 hdmi
Armada 370 and XP come with an unit called coherency fabric. This unit
allows to use the Armada 370/XP as a nearly coherent architecture. The
coherency mechanism uses snoop filters to ensure the coherency between
caches, DRAM and devices. This mechanism needs a synchronization
barrier which guarantees that all the memory writes initiated by the
devices have reached their target and do not reside in intermediate
write buffers. That's why the architecture is not totally coherent and
we need to provide our own functions for some DMA operations.
Beside the use of the coherency fabric, the device units will have to
set the attribute flag of the decoding address window to select the
accurate coherency process for the memory transaction. This is done
each device driver programs the DRAM address windows. The value of the
attribute set by the driver is retrieved through the
orion_addr_map_cfg struct filled during the early initialization of
the platform.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Yehuda Yitschak <yehuday@marvell.com>
Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>
The documentation doesn't match the actual function prototype. This is a
trivial patch to fix it.
Signed-off-by: Alison Chaiken <alison_chaiken@mentor.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
There are several drivers that use LEDs and depend on exactly the same
device tree binding. However, the binding documentation has simply been
cut-and-paste into each of the binding documents. Rather than continue
to duplicate it, this patch adds a common led binding document that all
can reference.
Signed-off-by: Marek Belisko <marek.belisko@open-nandra.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This patch enhances the IRQ controller driver to add support for
Inter-Processor-Interrupts that are needed to enable SMP support.
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The Armada 370 and Armada XP SOCs have a power management service unit
which is responsible for powering down and waking up CPUs and other
SOC units. This patch adds support for this unit.
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The Armada 370 and Armada XP SOCs have a coherency fabric unit which
is responsible for ensuring hardware coherency between all CPUs and
between CPUs and I/O masters. This patch provides the basic support
needed for SMP.
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
This patch adds a way to specify bindings between devices and power
domains using device tree.
A device can be bound to particular power domain by adding a
power-domain property containing a phandle to the domain. The device
will be bound to the domain before binding a driver to it and unbound
after unbinding a driver from it.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Initial state of power domains might vary on different boards and with
different bootloaders.
This patch adds detection of initial state of power domains when being
registered from DT.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Set tps65217 PMIC status to OFF if power enable toggle is supported.
By setting this bit to 1 to enter PMIC to OFF state when PWR_EN pin
is pulled low. Also adds a DT flag to specify that device pmic
supports shutdown control or not.
Signed-off-by: Colin Foe-Parker <colin.foeparker@logicpd.com>
[anilkumar@ti.com: move the additions to tps65217 MFD driver]
Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
From Pawel Moll:
* 'vexpress-clk-soc' of git://git.linaro.org/people/pawelmoll/linux:
ARM: vexpress: Remove motherboard dependencies in the DTS files
ARM: vexpress: Start using new Versatile Express infrastructure
ARM: vexpress: Add config bus components and clocks to DTs
mfd: Versatile Express system registers driver
mfd: Versatile Express config infrastructure
From Stephen Warren:
ARM: bcm2835: core SoC enhancements
A machine restart/reboot implementation is added. The GPIO/pinmux
controller is instantiated, and dummy gpio.h added.
* tag 'bcm2835-for-3.8-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi:
ARM: bcm2835: enable GPIO/pinctrl
ARM: bcm2835: implement machine restart hook
Signed-off-by: Olof Johansson <olof@lixom.net>
A wide variety of device tree additions are made across many Tegra
boards:
* WiFi is supported on Seaboard, Ventana, and Cardhu.
* An I2C mux is added for Ventana, and Tamonten.
* SPI flash is added to Cardhu, and TrimSlice.
* Temperature sensors are added to Harmony, Tamonten, and Ventana.
* host1x (graphics/display controller) is added to the SoC include files.
* HDMI displays are enabled on Harmony, TrimSlice, Tamonten, Plutux, Tec,
and Whistler.
This pull request is based on tegra-for-3.8-soc.
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Merge tag 'tegra-for-3.8-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt
From Stephen Warren:
ARM: tegra: device tree changes
A wide variety of device tree additions are made across many Tegra
boards:
* WiFi is supported on Seaboard, Ventana, and Cardhu.
* An I2C mux is added for Ventana, and Tamonten.
* SPI flash is added to Cardhu, and TrimSlice.
* Temperature sensors are added to Harmony, Tamonten, and Ventana.
* host1x (graphics/display controller) is added to the SoC include files.
* HDMI displays are enabled on Harmony, TrimSlice, Tamonten, Plutux, Tec,
and Whistler.
This pull request is based on tegra-for-3.8-soc.
* tag 'tegra-for-3.8-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (47 commits)
ARM: tegra: whistler: enable HDMI port
ARM: tegra: tec: Enable HDMI output
ARM: tegra: plutux: Enable HDMI output
ARM: tegra: tamonten: Add host1x support
ARM: tegra: trimslice: enable HDMI port
ARM: tegra: harmony: enable HDMI port
ARM: tegra: Add Tegra30 host1x support
ARM: tegra: Add Tegra20 host1x support
ARM: tegra: trimslice: enable SPI flash
ARM: tegra: dts: add sflash controller dt entry
ARM: tegra: ventana: Add NCT1008 temperature sensor
ARM: tegra: tamonten: Add NCT1008 temperature sensor
ARM: tegra: harmony: Add ADT7641 temperature sensor
ARM: tegra: tec: Remove redundant DT properties
ARM: tegra: tamonten: Add DDC/PTA pinmux
ARM: tegra: dts: cardhu: enable SLINK4
ARM: tegra: dts: add slink controller dt entry
ARM: dt: tegra: ventana: define pinmux for ddc
ARM: dt: t30 cardhu: set pinmux and power for wlan
ARM: dt: t20 ventana: set pinmux and power for wlan
...
- conversion of watchdog to DT
- usart definition for evk-pro3 board
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Merge tag 'at91-for-next-dt' of git://github.com/at91linux/linux-at91 into next/dt
From Nicolas Ferre:
More DT material for AT91:
- conversion of watchdog to DT
- usart definition for evk-pro3 board
* tag 'at91-for-next-dt' of git://github.com/at91linux/linux-at91:
ARM: at91/dts: evk-pro3: enable watchdog
ARM: at91/dts: add at91sam9_wdt driver to at91sam926x, at91sam9g45
watchdog: at91sam9_wdt: add device tree support
ARM: at91: dt: evk-pro3: enable uart0 and uart2
Also the driver was modifued to take advantage of recent improvements in
matrix_keypad_build_keymap() implementation, which automatically allocates
memory for keymap.
The driver was tested on AM335x EVM.
Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
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Merge tag 'tags/sunxi-support-for-3.8' of git://github.com/mripard/linux into next/soc
From Maxime Ripard:
Allwinner SoC support for 3.8
* tag 'tags/sunxi-support-for-3.8' of git://github.com/mripard/linux:
ARM: sunxi: Add entry to MAINTAINERS
ARM: sunxi: Add device tree for the A13 and the Olinuxino board
ARM: sunxi: Add earlyprintk support
ARM: sunxi: Add basic support for Allwinner A1x SoCs
irqchip: sunxi: Add irq controller driver
clocksource: sunxi: Add Allwinner A1X Timer Driver
clk: sunxi: Add dummy fixed rate clock for Allwinner A1X SoCs
Signed-off-by: Olof Johansson <olof@lixom.net>
Their stock ticker is 3407.T which wouldn't make a good DT vendor
prefix. Use the company name initials instead.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
This patch adds a device tree vendor prefix for Synopsys Inc.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Now that the Armada 370/XP platform has gained proper integration with
the clock framework, we add clk support in the Marvell Armada 370/XP
Ethernet driver.
Since the existing Device Tree binding that exposes a
'clock-frequency' property has never been exposed in any stable kernel
release, we take the freedom of removing this property to replace it
with the standard 'clocks' clock pointer property.
The Device Tree binding documentation is updated accordingly.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
This patch finally adds a Device Tree binding to the mv_xor
driver. Thanks to the previous cleanup patches, the Device Tree
binding is relatively simply: one DT node per XOR engine, with
sub-nodes for each XOR channel of the XOR engine. The binding
obviously comes with the necessary documentation.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: devicetree-discuss@lists.ozlabs.org
This driver allows to provide DT clocks for clock gates found on
Marvell Dove and Kirkwood SoCs. The clock gates are referenced by
the phandle index of the corresponding bit in the clock gating control
register to ease lookup in the datasheet.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Add Armada 370/XP specific CPU clocks
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This driver allows to provide DT clocks for core clocks found on
Marvell Kirkwood, Dove & 370/XP SoCs. The core clock frequencies and
ratios are determined by decoding the Sample-At-Reset registers.
Although technically correct, using a divider of 0 will lead to
div_by_zero panic. Let's use a ratio of 0/1 instead to fail later
with a zero clock.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by Gregory CLEMENT <gregory.clement@free-electrons.com>
This patch adds Device Nodes for SATA and SATA PHY device.
Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
[kgene.kim@samsung.com: removed address definitions as per comments]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
In order to start upstreaming Broadcom SoC support, create
a starting hierarchy, arch and dts files.
The first support SoC family that is planned is the
BCM281XX (BCM11130/11140/11351/28145/28155) family of dual A9 mobile
SoC cores.
This code is just the skeleton code for get the machine upstreamed. It
has been made MULTIPLATFORM compatible.
Next steps
----------
Upstream a basic set of drivers - sufficient for a console boot to
ramdisk. These will includer timer, gpio, i2c drivers.
After this basic set, we will proceed with a more comprehensive set
of drivers for the 281XX SoC family.
v2 patch mods
--------
- Remove l2x0_of_init call as there were problems with the code.
A separate patch will be submitted with cache init code
- Rename capri files and refs to bcm281xx-based names
- Add bcm281xx binding doc
- various misc cleanups
v3 patch mods
-------------
- Remove extra #include lines
- Remove remaining references to capri
- dt uart chipset string added
- cleaned up chip # references
v4 patch mods
-------------
- swap order of compatible definitions for uart
- fix typo
v5 patch mods
-------------
- Rename bcm281xx to bcm11351 in dts+code,
leaving references to bcm281xx only in help+comments.
v6 patch mods
-------------
- fix typo in uart 'compatible' string
Signed-off-by: Christian Daudt <csd@broadcom.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
SoC.
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Merge tag 'davinci-for-v3.8/dt' of git://gitorious.org/linux-davinci/linux-davinci into next/dt
From Sekhar Nori:
These changes add DT boot support to DaVinci DA850
SoC.
* tag 'davinci-for-v3.8/dt' of git://gitorious.org/linux-davinci/linux-davinci:
ARM: davinci: da850: generate dtbs for da850 boards
ARM: davinci: add support for am1808 based EnBW CMC board
ARM: davinci: da850 evm: add DT data
ARM: davinci: da850: add SoC DT data
ARM: davinci: da850: add DT boot support
ARM: davinci: da8xx: add DA850 PRUSS support
ARM: davinci: add platform hook to fetch the SRAM pool
ARM: davinci: da850: changed SRAM allocator to shared ram.
ARM: davinci: sram: switch from iotable to ioremapped regions
uio: uio_pruss: replace private SRAM API with genalloc
ARM: davinci: serial: provide API to initialze UART clocks
ARM: davinci: convert platform code to use clk_prepare/clk_unprepare
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit adds a KMS driver for the Tegra20 SoC. This includes basic
support for host1x and the two display controllers found on the Tegra20
SoC. Each display controller can drive a separate RGB/LVDS output.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Mark Zhang <markz@nvidia.com>
Reviewed-by: Mark Zhang <markz@nvidia.com>
Tested-by: Mark Zhang <markz@nvidia.com>
Tested-and-acked-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
When the mdio-gpio driver is probed via device trees, the platform
device id is set as -1, However the pdev->id is re-used as bus-id for
while creating mdio gpio bus.
So
For device tree case the mdio-gpio bus name appears as "gpio-ffffffff"
where as
for non-device tree case the bus name appears as "gpio-<bus-num>"
Which means the bus_id is fixed in device tree case, so we can't have
two mdio gpio buses via device trees. Assigning a logical bus number
via device tree solves the problem and the bus name is much consistent
with non-device tree bus name.
Without this patch
1. we can't support two mdio-gpio buses via device trees.
2. we should always pass gpio-ffffffff as bus name to phy_connect, very
different to non-device tree bus name.
So, setting up the bus_id via aliases from device tree is the right
solution and other drivers do similar thing.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
When booting through a device tree, the kernel cpu logical id map can be
initialized using device tree data passed by FW or through an embedded blob.
This patch adds a function that parses device tree "cpu" nodes and
retrieves the corresponding CPUs hardware identifiers (MPIDR).
It sets the possible cpus and the cpu logical map values according to
the number of CPUs defined in the device tree and respective properties.
The device tree HW identifiers are considered valid if all CPU nodes contain
a "reg" property, there are no duplicate "reg" entries and the DT defines a
CPU node whose "reg" property matches the MPIDR[23:0] of the boot CPU.
The primary CPU is assigned cpu logical number 0 to keep the current convention
valid.
Current bindings documentation is included in the patch:
Documentation/devicetree/bindings/arm/cpus.txt
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Add i2c driver to enable access to devices behind CBUS on Nokia Internet
Tablets.
The patch also adds CBUS I2C configuration for N8x0 which is one of the
users of this driver.
Acked-by: Felipe Balbi <balbi@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
This patch adds device tree support for charging algorithm driver
Signed-off-by: Rajanikanth H.V <rajanikanth.hv@stericsson.com>
Signed-off-by: Anton Vorontsov <anton.vorontsov@linaro.org>
This patch adds device tree support for ab8500-charger driver
Signed-off-by: Rajanikanth H.V <rajanikanth.hv@stericsson.com>
Signed-off-by: Anton Vorontsov <anton.vorontsov@linaro.org>
This patch adds device tree support for battery-temperature-monitor driver
Signed-off-by: Rajanikanth H.V <rajanikanth.hv@stericsson.com>
Signed-off-by: Anton Vorontsov <anton.vorontsov@linaro.org>
- This patch adds device tree support for fuelgauge driver
- optimize bm devices platform_data usage and of_probe(...)
Note: of_probe() routine for battery managed devices is made
common across all bm drivers.
- test status:
- interrupt numbers assigned differs between legacy and FDT mode.
Signed-off-by: Rajanikanth H.V <rajanikanth.hv@stericsson.com>
Signed-off-by: Anton Vorontsov <anton.vorontsov@linaro.org>
This patch extends the driver with any necessary SoC-specific
definitions to support EXYNOS4X12 SoCs.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Based on AT91 PIT DT patch from Jean-Christophe PLAGNIOL-VILLARD.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
SPEAr platform provides a provision to control chipselects of ARM PL022
Prime Cell spi controller through its system registers, which otherwise
remains under PL022 control which some protocols do not want.
This commit intends to provide the spi chipselect control in software over
gpiolib interface. spi chip drivers can use the exported gpiolib interface to
define their chipselect through DT or platform data.
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Reviewed-by: Vipin Kumar <vipin.kumar@st.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This hooks the Integrator/CP into the SoC bus when booting from
device tree, by mapping the CP controller registers first,
then registering the SoC device, and then populating the device
tree with the SoC device as parent.
Cc: Lee Jones <lee.jones@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Tegra RTC maintains seconds and milliseconds counters, and five alarm
registers. The alarms and other interrupts may wake the system from
low-power state.
Define a DT binding for this HW module, and add the module into the Tegra
device tree files.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The Tegra timer provides a number of 29-bit timer channels, a single
32-bit free running counter, and in the Tegra30 variant, 5 watchdog modules.
The first two channels may also trigger a legacy watchdog reset.
Define a DT binding for this HW module, and add the module into the Tegra
device tree files.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Use a better name for the USB PHY clock.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The registers in the GRLIB port of the controller are 32-bit and in big endian
byte order. The PRELOW and PREHIGH registers are merged into one register. The
subsequent registers have their offset decreased accordingly. Hence the register
access needs to be handled in a non-standard manner using custom getreg and
setreg functions.
Add setreg and getreg functions for different register widths and let oc_setreg
and oc_getreg use function pointers to call the appropriate functions.
A type is added as the data of the of match table entries. A new entry with a
different compatible string is added to the table. The type of that entry
triggers usage of the custom grlib functions by setting the setreg and getreg
function pointers.
Signed-off-by: Andreas Larsson <andreas@gaisler.com>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
There are also a few imx6 improvement patches in there.
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Merge tag 'imx-dt-3.8' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt
From Shawn Guo <shawn.guo@linaro.org>:
It's based on imx/multiplatform branch. Most of them are dts changes.
There are also a few imx6 improvement patches in there.
* tag 'imx-dt-3.8' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: imx6q: select ARM and PL310 errata
ARM: imx6q: print silicon version on boot
ARM i.MX dts: Consistently add labels to devicenodes
ARM: dts: imx6q-sabresd: add volume up/down gpio keys
ARM: dts: imx53: pinctl update
ARM: imx: enable cpufreq for imx6q
ARM: dts: imx6q: enable snvs lp rtc
ARM: dts: imx6q-sabreauto: Add basic support
ARM: imx6q: let users input debug uart port number
ARM: dts: imx53-qsb: Make DA9053 regulator functional
ARM: dts: imx53-qsb: Use pinctrl for gpio-led
ARM i.MX dtsi: Add default bus-width property for esdhc controller
Signed-off-by: Arnd Bregmann <arnd@arndb.de>
From Michal Simek <michal.simek@xilinx.com>:
These are based on previous patches (arm-soc zynq/cleanup branch).
The branch is still based on rc3 but I have also tried to merged it
with the v3.7-rc5 and there is no issue.
* 'arm-next' of git://git.xilinx.com/linux-xlnx:
ARM: zynq: add clk binding support to the ttc
ARM: zynq: use zynq clk bindings
clk: Add support for fundamental zynq clks
ARM: zynq: dts: split up device tree
ARM: zynq: Allow UART1 to be used as DEBUG_LL console.
ARM: zynq: dts: add description of the second uart
ARM: zynq: move arm-specific sys_timer out of ttc
zynq: move static peripheral mappings
zynq: remove use of CLKDEV_LOOKUP
zynq: use pl310 device tree bindings
zynq: use GIC device tree bindings
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'imx-dt' of git://git.pengutronix.de/git/imx/linux-2.6 into next/dt
From Sascha Hauer <s.hauer@pengutronix.de>:
ARM i.MX dt updates for 3.8
* tag 'imx-dt' of git://git.pengutronix.de/git/imx/linux-2.6:
Add device tree file for the armadeus apf27
ARM i.MX: Add Ka-Ro TX25 devicetree
ARM i.MX25: Add devicetree
ARM i.MX25: Add devicetree support
ARM i.MX25: Add missing clock gates
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
based on imx-multiplatform branch.
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Merge tag 'imx-soc' of git://git.pengutronix.de/git/imx/linux-2.6 into next/soc
From Sascha Hauer <s.hauer@pengutronix.de>:
ARM i.MX SoC updates
based on imx-multiplatform branch.
* tag 'imx-soc' of git://git.pengutronix.de/git/imx/linux-2.6:
ARM i.MX51 babbage: Add display support
ARM i.MX6: Add IPU support
ARM i.MX51: Add IPU support
ARM i.MX53: Add IPU support
ARM i.MX5: switch IPU clk support to devicetree bindings
ARM i.MX6: fix ldb_di_sel mux
ARM i.MX51: setup MIPI during startup
mx2_camera: Fix regression caused by clock conversion
ARM: clk-imx27: Add missing clock for mx2-camera
ARM i.MX27: Fix low reference clock path
ARM: dts: imx27-3ds: Remove local watchdog inclusion
watchdog: Support imx watchdog on SOC_IMX53
ARM: mach-imx: Support for DryIce RTC in i.MX53
ARM : i.MX27 : split code for allocation of ressources of camera and eMMA
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Tested on an at91sam9260 board (evk-pro3)
Signed-off-by: Fabio Porcedda <fabio.porcedda@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Only we meet the following conditions, we can enable the DMA support for
auart:
(1) We enable the DMA support in the dts file, such as
arch/arm/boot/dts/imx28.dtsi.
(2) We enable the hardware flow control.
(3) We use the mx28, not the mx23. Due to hardware bug(see errata: 2836),
we can not add the DMA support to mx23.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This patch adds support for pin configuration using pinctrl subsystem
to the i2c-s3c2410 driver.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
This patch contains a new network driver for the network unit of the
ARM Marvell Armada 370 and the Armada XP. Both SoCs use the PJ4B
processor, a Marvell-developed ARM core that implements the ARMv7
instruction set.
Compared to previous ARM Marvell SoCs (Kirkwood, Orion, Discovery),
the network unit in Armada 370 and Armada XP is highly different. This
is the reason why this new 'mvneta' driver is needed, while the older
ARM Marvell SoCs use the 'mv643xx_eth' driver.
Here is an overview of the most important hardware changes that
require a new, specific, driver for the network unit of Armada 370/XP:
- The new network unit has a completely different design and layout
for the RX and TX descriptors. They are now organized as a simple
array (each RX and TX queue has base address and size of this
array) rather than a linked list as in the old SoCs.
- The new network unit has a different RXQ and TXQ management: this
management is done using special read/write counter registers,
while in the Old SocS, it was done using the Ownership bit in RX
and TX descriptors.
- The new network unit has different interrupt registers
- The new network unit way of cleaning of interrupts is not done by
writing to the cause register, but by updating per-queue counters
- The new network unit has different GMAC registers (link, speed,
duplex configuration) and different WRR registers.
- The new network unit has lots of new units like PnC (Parser and
Classifier), PMT, BM (Memory Buffer Management), xPON, and more.
The driver proposed in the current patch only handles the basic
features. Additional hardware features will progressively be supported
as needed.
This code has originally been written by Rami Rosen
<rosenr@marvell.com>, and then reviewed and cleaned up by Thomas
Petazzoni <thomas.petazzoni@free-electrons.com>.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: David S. Miller <davem@davemloft.net>
This patch adds a separate driver for the MDIO interface of the
Marvell Ethernet controllers. There are two reasons to have a separate
driver rather than including it inside the MAC driver itself:
*) The MDIO interface is shared by all Ethernet ports, so a driver
must guarantee non-concurrent accesses to this MDIO interface. The
most logical way is to have a separate driver that handles this
single MDIO interface, used by all Ethernet ports.
*) The MDIO interface is the same between the existing mv643xx_eth
driver and the new mvneta driver. Even though it is for now only
used by the mvneta driver, it will in the future be used by the
mv643xx_eth driver as well.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: David S. Miller <davem@davemloft.net>
linux,mtd-name allow to specify the mtd name for retro capability with
physmap-flash drivers as boot loader pass the mtd partition via the old
device name physmap-flash.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Allow the i2c-mux-gpio to be used by a device tree enabled device. The
bindings are inspired by the one found in the i2c-mux-pinctrl driver.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Peter Korsgaard <peter.korsgaard@barco.com>
[wsa: fixed some whitespace]
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
mx6qsabreauto is a board based on mx6q SoC with the following features:
- 2GB of DDR3
- 2 USB ports
- 1 HDMI output port
- SPI NOR
- 2 LVDS LCD ports
- Gigabit Ethernet
- Camera
- eMMC and SD card slot
- Multichannel Audio
- CAN
- SATA
- NAND
- PCIE
- Video Input
Add very basic support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
convert at91sam9g20ek with wm8731 to device tree support
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Enable SLINK4 and connected device in Tegra30 based
platform Cardhu.
Setting maximum spi frequency to 25MHz.
SPI serial flash is connected on CS1 of SLINK4 on
cardhu platform.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
[swarren: swapped reg/compatible order to be consistent]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This driver supports GRCAN and CRHCAN CAN controllers available in the GRLIB
VHDL IP core library.
Signed-off-by: Andreas Larsson <andreas@gaisler.com>
Acked-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Enhance the driver to support partition subnodes inside the nand
device bindings to describe partions on the nand device.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
various .dts files, and timer related changes to allow
configuring the timer via device tree.
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Merge tag 'omap-for-v3.8/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
From Tony Lindgren <tony@atomide.com>:
Device tree related changes for omaps updating the
various .dts files, and timer related changes to allow
configuring the timer via device tree.
* tag 'omap-for-v3.8/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (48 commits)
usb: musb: dsps: dt binding - add resources, example
ARM: dts: omap4-sdp: Add pinmux configuration for HDMI
ARM: dts: omap4-panda: Add pinmux configuration for HDMI
ARM: dts: Makefile: Add the am335x-evmsk target in dtbs list
ARM: dts: AM33XX: Add usbss node
ARM: dts: AM33XX: Add push-buttons device tree data to am335x-evmsk
ARM: dts: AM33XX: Add pinmux configuration for gpio-keys to EVMSK
ARM: dts: AM33XX: Add user-leds device tree data to am335x-evmsk
ARM: dts: AM33XX: Add pinmux configuration for gpio-leds to EVMSK
ARM: dts: AM33XX: Add user-leds device tree data to am335x-bone
ARM: dts: AM33XX: Add pinmux configuration for user-leds to BONE
ARM: dts: AM33XX: Add volume-keys device tree data to am335x-evm
ARM: dts: AM33XX: Add pinmux configuration for volume-keys to EVM
ARM: dts: AM33XX: Add matrix keypad device tree data to am335x-evm
ARM: dts: AM33XX: Add pinmux configuration for matrix keypad to EVM
ARM: dts: omap5-evm: LPDDR2 memory device details for EVM
ARM: dts: omap5: EMIF device tree data for OMAP5 boards
ARM: dts: omap5-evm: Fix size of memory defined for EVM
ARM: OMAP2+: Add device-tree support for 32kHz counter
ARM: OMAP: Add DT support for timer driver
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Filenames of devictree binding documentation seems to be arbitrary and
for me it is unneeded hazzle to find the corresponding documentation for
a specific driver.
Naming the description the same as the driver is a lot easier and makes
sense to me since the driver defines the binding it understands.
Also, remove a reference in one source to the binding documentation, since path
information easily gets stale.
Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
Cc: Rob Herring <robherring2@gmail.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
The flctl can now be probed via device tree setup in addition to the
existing platform data way.
SoC specific setup data is set in the .data member of the OF match, so
kept within the driver itself, while board/user specific setup - like
partitioning - is taken from the device tree.
Actual configuration is added for the SoC sh7372.
Signed-off-by: Bastian Hecht <hechtb@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Do not use the platform_data to pass resource and be smart in the drivers.
Just pass it via resource
Switch to devm_request_and_ioremap at the sametime
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-By: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Add a device tree version of the Denali NAND driver. Based
on an original patch from Jamie Iles to add a MMIO version
of this driver.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
This driver is based on the thermal management framework in thermal_sys.c. A
thermal zone device is created with the trip points to which cooling devices
can be bound, the current cooling device is cpufreq, e.g. CPU frequency is
clipped down to cool the CPU, and other cooling devices can be added and bound
to the trip points dynamically. The platform specific PRCMU interrupts are
used to active thermal update when trip points are reached.
Signed-off-by: hongbo.zhang <hongbo.zhang@linaro.com>
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Francesco Lavra <francescolavra.fl@gmail.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Instead of having a host of different register offsets in the device tree,
this patch simplifies the CPSW code by letting the driver set the proper
register offsets automatically, based on the CPSW version.
Signed-off-by: Richard Cochran <richardcochran@gmail.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Provide simplified models for the necessary clocks on the zynq-7000
platform. Currently, the PLLs, the CPU clock network, and the basic
peripheral clock networks (for SDIO, SMC, SPI, QSPI, UART) are modelled.
OF bindings are also provided and documented.
Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
A selection of voltage or current values (AKA states) should always
be specified when using a GPIO regulator. If there are no switchable
states then the fixed regulators should be used instead.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
0384e90b8 ("spi/mcspi: allow configuration of pin directions") did what
it claimed to do the wrong way around. D0/D1 is configured as output by
*clearing* the bits in the conf registers, hence also breaking the
former default behaviour.
Fix this before that change is merged to mainline.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
NVIDIA's Tegra20 have the SPI (SFLASH) controller to
interface with spi flash device which is used for system
boot. Add the spi driver for this controller.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Wrong description in binding document.
Doc use "gpio-enable", but code use "enable-gpio"
In drivers/regulator/gpio-regulator.c
config->enable_gpio = of_get_named_gpio(np, "enable-gpio", 0);
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Patches from Roland Stigge <stigge@antcom.de>:
Platform topic branch for lpc32xx
* 'lpc32xx/core' of git://git.antcom.de/linux-2.6:
ARM: LPC32xx: Add the motor PWM clock
ARM: LPC32xx: Cleanup irq.c
ARM: LPC32xx: Relocate calls to irq_set_chained_handler()
ARM: LPC32xx: Remove superfluous irq_alloc_descs()
Includes an update to v3.7-rc4
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This adds a i.MX25 dtsi file along with the i.MX25 clock tree
documentation. The devicetree should be fairly complete for:
- uart
- fec
- i2c
- spi
- pwm
- nand
- gpio
- wdog
- esdhc
- flexcan
The more exotic devices currently miss clock bindings.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
We have here the usual set of cleanups for the MUSB driver; a
big set of patches converting platform_device_del() and
platform_device_put() into platform_device_unregister().
Another big set was applied converting to module_platform_driver()
macro in order to reduce some boilerplate code from all glue
layers.
Other than that, we had a series fixing one known silicon errata
where we couldn't read a few registers. In order to fix that
we're now using shadow variables for reads and only writing
to the registers which are known to break functionality when
read.
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Merge tag 'musb-for-v3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next
USB musb merge from Felipe:
"usb: musb: patches for v3.8 merge window
We have here the usual set of cleanups for the MUSB driver; a
big set of patches converting platform_device_del() and
platform_device_put() into platform_device_unregister().
Another big set was applied converting to module_platform_driver()
macro in order to reduce some boilerplate code from all glue
layers.
Other than that, we had a series fixing one known silicon errata
where we couldn't read a few registers. In order to fix that
we're now using shadow variables for reads and only writing
to the registers which are known to break functionality when
read."
Here we add the required documentation for the STMPE Multi-Functional
Device (MFD) Device Tree bindings. It describes all of the bindings
currently supported by the driver.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
pinctrl subsystem needs gpio chip base to prepare set of gpio
pin ranges, which a given pinctrl driver can handle. This is
important to handle pinctrl gpio request calls in order to
program a given pin properly for gpio operation.
As gpio base is allocated dynamically during gpiochip
registration, presently there exists no clean way to pass this
information to the pinctrl subsystem.
After few discussions from [1], it was concluded that may be
gpio controller reporting the pin range it supports, is a
better way than pinctrl subsystem directly registering it.
[1] http://comments.gmane.org/gmane.linux.ports.arm.kernel/184816
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
[Edited documentation a bit]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The used vendor prefix corresponds to the stock symbol (ONNN) for ON
Semiconductor Corp.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Conflicts:
drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
Minor conflict between the BCM_CNIC define removal in net-next
and a bug fix added to net. Based upon a conflict resolution
patch posted by Stephen Rothwell.
Signed-off-by: David S. Miller <davem@davemloft.net>
remove linux specific references, enumerates all supported
regulators
Signed-off-by: Qing Xu <qingx@marvell.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
DT bindings normally use '-' (hyphens) instead of '_' (underscore),
driver has it the proper way, but binding documentation does not
reflect it, fix it.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
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Merge tag 'v3.7-rc4' into next to sync up Wacom bits
Linux 3.7-rc4
OMAP2+ family of devices are now obtaining resources via DT, earlier
it was obtained from hwmod. Update binding document accrodingly, while
at it add example.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Add atmel-ssc for device tree support
Match "atmel,at91rm9200-ssc" for using pdc for data transfer
Match "atmel,at91sam9g45-ssc" for using dma for data transfer
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Tested-by: Joachim Eastwood <manabian@gmail.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: netdev@vger.kernel.org
Signed-off-by: David S. Miller <davem@davemloft.net>
From Michal Simek:
* 'arm-next' of git://git.xilinx.com/linux-xlnx:
zynq: move static peripheral mappings
zynq: remove use of CLKDEV_LOOKUP
zynq: use pl310 device tree bindings
zynq: use GIC device tree bindings
+ Linux 3.7-rc3
From Lee Jones:
* 'ste-dt-for-next' of git://git.linaro.org/people/ljones/linux-3.0-ux500: (31 commits)
ARM: ux500: Convert DT_MACHINE_START to use SMP operations
ARM: ux500: CONFIG: Enable GPIO Regulators
ARM: ux500: Change the type of interrupt to something compatible
ARM: ux500: Add node for the MMC GPIO regulator
ARM: ux500: List DT compatibility using platform names rather than by board
ARM: ux500: Remove duplicate DT_MACHINE_START - make u8500 for generic
ARM: ux500: Rename references to the ccu9540 dev board accordingly
ARM: ux500: Enable all MMC devices on the u9540 when booting with DT
ARM: ux500: Enable SDI4 port on the u9540 when booting with Device Tree
ARM: ux500: Add UART support to the u9540 Device Tree
ARM: ux500: Add support for ST-Ericsson's u9540 SoC
ARM: ux500: Add skeleton DTS file for the u9540
ARM: ux500: Remove unused board compatible string
ARM: ux500: Supply the STMPE keypad Device Tree node to the STUIB DT
ARM: ux500: Apply a Device Tree node for the STMPE MFD
ARM: ux500: Stop informing the regulator subsystem that we have full constraints
ARM: ux500: Add all bu21013 touch screen components to supported Device Trees
ARM: ux500: Stop calling the UIB init function when using Device Tree
ARM: ux500: Create a new Device Tree include file for boards supporting STUIBs
Documentation: Detail permitted DT properties for the BU21013 Touch Screen
...
The way the VE motherboard Device Trees were constructed
enforced naming and structure of daughterboard files. This
patch makes it possible to simply include the motherboard
description anywhere in the main Device Tree and retires
the "arm,v2m-timer" alias - any of the motherboard SP804
timers will be used instead.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
This is a platform driver for Versatile Express' "system
register" block. It's a random collection of registers providing
the following functionality:
- low level platform functions like board ID access; in order to
use those, the driver must be initialized early, either statically
or based on the DT
- config bus bridge via "system control" interface; as the response
from the controller does not generate interrupt (yet), the status
register is periodically polled using a timer
- pseudo GPIO lines providing MMC card status and Flash WP#
signal control
- LED interface for a set of 8 LEDs on the motherboard, with
"heartbeat", "mmc0" and "cpu0" to "cpu5" as default triggers
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Versatile Express platform has an elaborated configuration system,
consisting of microcontrollers residing on the mother- and
daughterboards known as Motherboard/Daughterboard Configuration
Controller (MCC and DCC). The controllers are responsible for
the platform initialization (reset generation, flash programming,
FPGA bitfiles loading etc.) but also control clock generators,
voltage regulators, gather environmental data like temperature,
power consumption etc. Even the video output switch (FPGA) is
controlled that way.
Those devices are _not_ visible in the main address space and
the usual communication channel uses some kind of a bridge in
the peripheral block sending commands (requests) to the
controllers and receiving responses. It can take up to
500 microseconds for a transaction to be completed, therefore
it is important to provide a non-blocking interface to it.
This patch adds an abstraction of this infrastructure. Bridge
drivers can register themselves with the framework. Then,
a driver of a device can request an abstract "function" - the
request will be redirected to a bridge referred by thedd
"arm,vexpress,config-bridge" property of the device tree node.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
A very simple binding, the only property is the phandle to the PWM.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
This patch adds a way to configure the CPTS input clock scaling factors
via the device tree.
Signed-off-by: Richard Cochran <richardcochran@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Because time stamping on both external ports of the switch simultaneously
is positively useless from the application's point of view, this patch
provides a DT configuration method to choose the active port.
Signed-off-by: Richard Cochran <richardcochran@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch fixes the cpsw driver to operate correctly with both the
dm814x and the am335x versions of the switch hardware.
Signed-off-by: Richard Cochran <richardcochran@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch updates pwm-vt8500.c to support devicetree probing and
make use of the common clock subsystem.
A binding document describing the PWM controller found on
arch-vt8500 is also included.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Here we apply required documentation for the Rohm BU21013 Touch
Screen driver which describe available properties and how to use
them.
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: linux-input@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Separate out common dts pieces from highbank dts and add support for
Calxeda ECX-2000 (Midway) SOC.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tegra20/Tegra30 supports the spi interface through its SLINK
controller. Add spi driver for SLINK controller.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Merge tag 'v3.7-rc3' into next to sync up with recent USB and MFD changes
