Commit Graph

1891 Commits

Author SHA1 Message Date
Thomas Gleixner
2025cf9e19 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms and conditions of the gnu general public license
  version 2 as published by the free software foundation this program
  is distributed in the hope it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 263 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141901.208660670@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-05 17:36:37 +02:00
Thomas Gleixner
97fb5e8d9b treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 284
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 and
  only version 2 as published by the free software foundation this
  program is distributed in the hope that it will be useful but
  without any warranty without even the implied warranty of
  merchantability or fitness for a particular purpose see the gnu
  general public license for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 294 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-05 17:36:37 +02:00
Thomas Gleixner
9c92ab6191 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282
Based on 1 normalized pattern(s):

  this software is licensed under the terms of the gnu general public
  license version 2 as published by the free software foundation and
  may be copied distributed and modified under those terms this
  program is distributed in the hope that it will be useful but
  without any warranty without even the implied warranty of
  merchantability or fitness for a particular purpose see the gnu
  general public license for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 285 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-05 17:36:37 +02:00
David S. Miller
b4b12b0d2f Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
The phylink conflict was between a bug fix by Russell King
to make sure we have a consistent PHY interface mode, and
a change in net-next to pull some code in phylink_resolve()
into the helper functions phylink_mac_link_{up,down}()

On the dp83867 side it's mostly overlapping changes, with
the 'net' side removing a condition that was supposed to
trigger for RGMII but because of how it was coded never
actually could trigger.

Signed-off-by: David S. Miller <davem@davemloft.net>
2019-05-31 10:49:43 -07:00
Thomas Gleixner
25763b3c86 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 206
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of version 2 of the gnu general public license as
  published by the free software foundation

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 107 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Reviewed-by: Steve Winslow <swinslow@gmail.com>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190528171438.615055994@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-30 11:29:53 -07:00
Thomas Gleixner
9952f6918d treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms and conditions of the gnu general public license
  version 2 as published by the free software foundation this program
  is distributed in the hope it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details you should have received a copy of the gnu general
  public license along with this program if not see http www gnu org
  licenses

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 228 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Steve Winslow <swinslow@gmail.com>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-30 11:29:52 -07:00
Thomas Gleixner
af873fcece treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 194
Based on 1 normalized pattern(s):

  license terms gnu general public license gpl version 2

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 161 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Reviewed-by: Steve Winslow <swinslow@gmail.com>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190528170027.447718015@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-30 11:29:22 -07:00
Thomas Gleixner
1802d0beec treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation this program is
  distributed in the hope that it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 655 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-30 11:26:41 -07:00
Thomas Gleixner
c942fddf87 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157
Based on 3 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version this program is distributed in the
  hope that it will be useful but without any warranty without even
  the implied warranty of merchantability or fitness for a particular
  purpose see the gnu general public license for more details

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version [author] [kishon] [vijay] [abraham]
  [i] [kishon]@[ti] [com] this program is distributed in the hope that
  it will be useful but without any warranty without even the implied
  warranty of merchantability or fitness for a particular purpose see
  the gnu general public license for more details

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version [author] [graeme] [gregory]
  [gg]@[slimlogic] [co] [uk] [author] [kishon] [vijay] [abraham] [i]
  [kishon]@[ti] [com] [based] [on] [twl6030]_[usb] [c] [author] [hema]
  [hk] [hemahk]@[ti] [com] this program is distributed in the hope
  that it will be useful but without any warranty without even the
  implied warranty of merchantability or fitness for a particular
  purpose see the gnu general public license for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 1105 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070033.202006027@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-30 11:26:37 -07:00
Thomas Gleixner
2874c5fd28 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 3029 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-30 11:26:32 -07:00
Sibi Sankar
dec9a05a14 dt-bindings: power: Add rpm power domain bindings for msm8998
Add RPM power domain bindings for the msm8998 family of SoC

Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Jeffrey Hugo <jhugo@codeaurora.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
2019-05-29 21:40:43 -05:00
Bjorn Andersson
0cb93b1503 dt-bindings: power: Add rpm power domain bindings for qcs404
Add RPM power domain bindings for the qcs404 family of SoC

Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Jeffrey Hugo <jhugo@codeaurora.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
[sibis: Add supported rpmpd states for qcs404]
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Signed-off-by: Andy Gross <agross@kernel.org>
2019-05-29 21:40:42 -05:00
Thomas Gleixner
74ba9207e1 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 61
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version this program is distributed in the
  hope that it will be useful but without any warranty without even
  the implied warranty of merchantability or fitness for a particular
  purpose see the gnu general public license for more details you
  should have received a copy of the gnu general public license along
  with this program if not write to the free software foundation inc
  675 mass ave cambridge ma 02139 usa

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 441 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Michael Ellerman <mpe@ellerman.id.au> (powerpc)
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190520071858.739733335@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-24 17:36:45 +02:00
Manivannan Sadhasivam
ef98682a4e dt-bindings: reset: Add devicetree binding for BM1880 reset controller
Add devicetree binding for Bitmain BM1880 SoC reset controller.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2019-05-24 16:08:14 +02:00
Leonard Crestez
87def8d0d5 dt-bindings: clock: imx8m: Add GIC clock
This should be defined in the clock tree so that parents are not
shutdown by accident

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-05-23 21:14:40 +08:00
Anson Huang
2b2ebb9acb dt-bindings: clock: imx8mm: Add SNVS clock
Add macro for the SNVS clock of the i.MX8MM.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-05-23 15:29:39 +08:00
Trent Piepho
980066e6d9 dt-bindings: phy: dp83867: Add documentation for disabling clock output
The clock output is generally only used for testing and development and
not used to daisy-chain PHYs.  It's just a source of RF noise afterward.

Add a mux value for "off".  I've added it as another enumeration to the
output property.  In the actual PHY, the mux and the output enable are
independently controllable.  However, it doesn't seem useful to be able
to describe the mux setting when the output is disabled.

Document that PHY's default setting will be left as is if the property
is omitted.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-05-22 17:40:17 -07:00
Anson Huang
4ef69160b3 dt-bindings: clock: imx8mq: Add SNVS clock
Add macro for the SNVS clock of the i.MX8MQ.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-05-22 17:00:52 +08:00
Thierry Reding
8d9a8543be dt-bindings: tegra186-gpio: Remove unused definitions
Now that all users of the old definitions have been updated to use the
Tegra186 specific prefix, remove the unused definitions.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-05-21 16:32:10 +02:00
Thomas Gleixner
1ccea77e2a treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13
Based on 2 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version this program is distributed in the
  hope that it will be useful but without any warranty without even
  the implied warranty of merchantability or fitness for a particular
  purpose see the gnu general public license for more details you
  should have received a copy of the gnu general public license along
  with this program if not see http www gnu org licenses

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version this program is distributed in the
  hope that it will be useful but without any warranty without even
  the implied warranty of merchantability or fitness for a particular
  purpose see the gnu general public license for more details [based]
  [from] [clk] [highbank] [c] you should have received a copy of the
  gnu general public license along with this program if not see http
  www gnu org licenses

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 355 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com>
Reviewed-by: Steve Winslow <swinslow@gmail.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190519154041.837383322@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-21 11:28:45 +02:00
Thomas Gleixner
a636cd6c42 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 4
Based on 1 normalized pattern(s):

  licensed under gplv2 or later

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 118 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com>
Reviewed-by: Steve Winslow <swinslow@gmail.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190519154040.961286471@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-21 11:28:40 +02:00
Thomas Gleixner
1621633323 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 1
Based on 2 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version this program is distributed in the
  hope that it will be useful but without any warranty without even
  the implied warranty of merchantability or fitness for a particular
  purpose see the gnu general public license for more details you
  should have received a copy of the gnu general public license along
  with this program if not write to the free software foundation inc
  51 franklin street fifth floor boston ma 02110 1301 usa

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option [no]_[pad]_[ctrl] any later version this program is
  distributed in the hope that it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details you should have received a copy of the gnu general
  public license along with this program if not write to the free
  software foundation inc 51 franklin street fifth floor boston ma
  02110 1301 usa

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 176 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com>
Reviewed-by: Steve Winslow <swinslow@gmail.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190519154040.652910950@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-21 11:28:39 +02:00
Mark Brown
1c7c3237c0 Linux 5.2-rc1
-----BEGIN PGP SIGNATURE-----
 
 iQFSBAABCAA8FiEEq68RxlopcLEwq+PEeb4+QwBBGIYFAlzh3PgeHHRvcnZhbGRz
 QGxpbnV4LWZvdW5kYXRpb24ub3JnAAoJEHm+PkMAQRiGnhoH/jkl4X66KuOXvGXa
 9pgFzyEa3Mhqs0j+AaJYmRyoRty1CbAfMLEWgr0JbZy56zm0PhtXOxcu56/tfdtw
 f5j8OJLDvld10imHXxUrom9zc546Ff90VTOvWmsYznszTz0rV5HLmKgVIIc7ZN8W
 6hshDOy/rviUcPAVrLKdZffzgQZlASNS7To7IBE9okT4QHEtER7dgzM/Z0VAg9R1
 guCPaN8tje4vq2Lv7+J5T9LOF1RObCbKXNADwXY1rMRK5ao3xS93eDnJ8Vn08utI
 UECIVfnYsA6pGl6v1ErCl9izx9MoTU3Crle7BRzVbrw7furvB2lJ1R4RGwqRbvcB
 HovhmHI=
 =TMir
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQFHBAABCgAxFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAlzih0UTHGJyb29uaWVA
 a2VybmVsLm9yZwAKCRAk1otyXVSH0L7OB/92a50lmgSRgsa9cfrlU5G4cq9qw32Y
 fgZpNqmMW4jjrf/oXgkletQ0jGKH8Ty/VIfoqpzDMsoHpx7tXtFG5D4QcMhO1gP9
 5Az3S0+EaIEqOYABylFrfm13k++10dLueqim4NiFX3O7i1M0R9vnzdeC/74hgcBP
 Ibl1hhCAFnRRXHDT4TLkesa/XEBaWfSH28pemogxywhASkXNkFAw7uefe5Cv+2gt
 L5gRHY2OhSVFrZzEzerG8MoG3DiLnAMRUZ72HNS5+CujNDY7d+FvgUvGxrv5f/pK
 MIKeInJ2+8p7xCbA/OLz/nUWh4Ua9Z4NcJK7BnHXfnz/hSlMgsd921u5
 =qHBg
 -----END PGP SIGNATURE-----

Merge tag 'v5.2-rc1' into asoc-5.3

Linux 5.2-rc1
2019-05-20 11:53:50 +01:00
Jerome Brunet
e63b063ecd clk: meson: fix MPLL 50M binding id typo
MPLL_5OM (the capital letter o) should indeed be MPLL_50M (the number)
Fix this before it gets used.

Fixes: 25db146aa7 ("dt-bindings: clk: meson: add g12a periph clock controller bindings")
Reported-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-05-20 12:05:46 +02:00
Anson Huang
2c61a54599 dt-bindings: clock: imx8mm: Add GPIO clocks
Add macro for the GPIO clocks of the i.MX8MM.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-05-20 11:21:35 +08:00
Linus Torvalds
e8a1d70117 ARM: Device-tree updates
Besides new bindings and additional descriptions of hardware blocks for
 various SoCs and boards, the main new contents here is:
 
 SoCs:
  - Intel Agilex (SoCFPGA)
  - NXP i.MX8MM (Quad Cortex-A53 with media/graphics focus)
 
 New boards:
  - Allwinner:
   + RerVision H3-DVK (H3)
   + Oceanic 5205 5inMFD (H6)
   + Beelink GS2 (H6)
   + Orange Pi 3 (H6)
  - Rockchip:
   + Orange Pi RK3399
   + Nanopi NEO4
   + Veyron-Mighty Chromebook variant
  - Amlogic:
   + SEI Robotics SEI510
  - ST Micro:
   + stm32mp157a discovery1
   + stm32mp157c discovery2
  - NXP:
   + Eckelmann ci4x10 (i.MX6DL)
   + i.MX8MM EVK (i.MX8MM)
   + ZII i.MX7 RPU2 (i.MX7)
   + ZII SPB4 (VF610)
   + Zii Ultra (i.MX8M)
   + TQ TQMa7S (i.MX7Solo)
   + TQ TQMa7D (i.MX7Dual)
   + Kobo Aura (i.MX50)
   + Menlosystems M53 (i.MX53)j
  - Nvidia:
   + Jetson Nano (Tegra T210)
 -----BEGIN PGP SIGNATURE-----
 
 iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAlzc+0QPHG9sb2ZAbGl4
 b20ubmV0AAoJEIwa5zzehBx32MkP/RBivO4AJpznRbqULmStzZL5y24bKzlt/vO8
 6QXr95fTuqJ+0e+oNTVBN4pYMT0yrnMh4PGesEhcu5SEL0fc1kS8UPhkC45FbcLu
 KG+51oLQyiedQrFAG7aT9JdZgtqbfkeGeieJl4LOKHiXy0uNQY0i4VsxrnSeRfuA
 9Geq4sO0hwDUE8OwjZDddeURJmBulshgZtYGZRceKhO3NYRTwOYFcVsijAY2tfCu
 VE4v231bs+gCaDzD90y3HBRCmK1UdUXWQzrud44EV9seJ3yskXFU6YOuKhecXtEk
 jHjLaIZ5zss7cHjlRdkGb8B6TavBuvaQi8hTB7qScvRSWKTiUmAo3vCuyHNJZroV
 rG8g1CbYgyG8/B1KjjU/kvdYdl82z3+K27UZHoAM5lKfEvIyAlWd4gmAri/0qR1A
 LoMDYmvtsIXg7ZMnmfuLJc5luU7zUPjlXMyA/E6wZ6Q5AzDphkpfqir7/9eb8A0p
 bCiyitfy6N0jB9lm51wAKIl/0poMDDEzsH/VpVz6iziDwpoUXoL5ujTwIijQL6Li
 0dLJssBSU0ElX2GOICu5OgpVwK9aZnlMC7eG0Uq49pgvQIz8czQcTE2tv9jtGxmz
 1T0JB2ilvJnDSunnYek3xiAB1gU8I7cdwjtkMvyPho1Gqd6fFKAChvWFbSIkVdjz
 CGqrSXjF
 =lMVy
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM Device-tree updates from Olof Johansson:
 "Besides new bindings and additional descriptions of hardware blocks
  for various SoCs and boards, the main new contents here is:

  SoCs:
   - Intel Agilex (SoCFPGA)
   - NXP i.MX8MM (Quad Cortex-A53 with media/graphics focus)

  New boards:
   - Allwinner:
      + RerVision H3-DVK (H3)
      + Oceanic 5205 5inMFD (H6)
      + Beelink GS2 (H6)
      + Orange Pi 3 (H6)
   - Rockchip:
      + Orange Pi RK3399
      + Nanopi NEO4
      + Veyron-Mighty Chromebook variant
   - Amlogic:
      + SEI Robotics SEI510
   - ST Micro:
      + stm32mp157a discovery1
      + stm32mp157c discovery2
   - NXP:
      + Eckelmann ci4x10 (i.MX6DL)
      + i.MX8MM EVK (i.MX8MM)
      + ZII i.MX7 RPU2 (i.MX7)
      + ZII SPB4 (VF610)
      + Zii Ultra (i.MX8M)
      + TQ TQMa7S (i.MX7Solo)
      + TQ TQMa7D (i.MX7Dual)
      + Kobo Aura (i.MX50)
      + Menlosystems M53 (i.MX53)j
   - Nvidia:
      + Jetson Nano (Tegra T210)"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (593 commits)
  arm64: dts: bitmain: Add UART pinctrl support for Sophon Edge
  arm64: dts: bitmain: Add pinctrl support for BM1880 SoC
  arm64: dts: bitmain: Add GPIO Line names for Sophon Edge board
  arm64: dts: bitmain: Add GPIO support for BM1880 SoC
  ARM: dts: gemini: Indent DIR-685 partition table
  dt-bindings: hwmon (pwm-fan) Remove dead "cooling-*-state" properties
  ARM: dts: qcom-apq8064: Set 'cxo_board' as ref clock of the DSI PHY
  arm64: dts: msm8998: thermal: Restrict thermal zone name length to under 20
  arm64: dts: msm8998: thermal: Fix number of supported sensors
  arm64: dts: msm8998-mtp: thermal: Remove skin and battery thermal zones
  arm64: dts: exynos: Move fixed-clocks out of soc
  arm64: dts: exynos: Move pmu and timer nodes out of soc
  ARM: dts: s5pv210: Fix camera clock provider on Goni board
  ARM: dts: exynos: Properly override node to use MDMA0 on Universal C210
  ARM: dts: exynos: Move fixed-clocks out of soc on Exynos3250
  ARM: dts: exynos: Remove unneeded address/size cells from fixed-clock on Exynos3250
  ARM: dts: exynos: Move pmu and timer nodes out of soc
  arm64: dts: rockchip: fix IO domain voltage setting of APIO5 on rockpro64
  arm64: dts: db820c: Add sound card support
  arm64: dts: apq8096-db820c: Add HDMI display support
  ...
2019-05-16 08:38:17 -07:00
Linus Torvalds
a455eda33f Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal
Pull thermal soc updates from Eduardo Valentin:

 - thermal core has a new devm_* API for registering cooling devices. I
   took the entire series, that is why you see changes on drivers/hwmon
   in this pull (Guenter Roeck)

 - rockchip thermal driver gains support to PX30 SoC (Elaine Zhang)

 - the generic-adc thermal driver now considers the lookup table DT
   property as optional (Jean-Francois Dagenais)

 - Refactoring of tsens thermal driver (Amit Kucheria)

 - Cleanups on cpu cooling driver (Daniel Lezcano)

 - broadcom thermal driver dropped support to ACPI (Srinath Mannam)

 - tegra thermal driver gains support to OC hw throttle and GPU throtle
   (Wei Ni)

 - Fixes in several thermal drivers.

* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal: (59 commits)
  hwmon: (pwm-fan) Use devm_thermal_of_cooling_device_register
  hwmon: (npcm750-pwm-fan) Use devm_thermal_of_cooling_device_register
  hwmon: (mlxreg-fan) Use devm_thermal_of_cooling_device_register
  hwmon: (gpio-fan) Use devm_thermal_of_cooling_device_register
  hwmon: (aspeed-pwm-tacho) Use devm_thermal_of_cooling_device_register
  thermal: rcar_gen3_thermal: Fix to show correct trip points number
  thermal: rcar_thermal: update calculation formula for R-Car Gen3 SoCs
  thermal: cpu_cooling: Actually trace CPU load in thermal_power_cpu_get_power
  thermal: rockchip: Support the PX30 SoC in thermal driver
  dt-bindings: rockchip-thermal: Support the PX30 SoC compatible
  thermal: rockchip: fix up the tsadc pinctrl setting error
  thermal: broadcom: Remove ACPI support
  thermal: Fix build error of missing devm_ioremap_resource on UM
  thermal/drivers/cpu_cooling: Remove pointless field
  thermal/drivers/cpu_cooling: Add Software Package Data Exchange (SPDX)
  thermal/drivers/cpu_cooling: Fixup the header and copyright
  thermal/drivers/cpu_cooling: Remove pointless test in power2state()
  thermal: rcar_gen3_thermal: disable interrupt in .remove
  thermal: rcar_gen3_thermal: fix interrupt type
  thermal: Introduce devm_thermal_of_cooling_device_register
  ...
2019-05-16 07:56:57 -07:00
Jerome Brunet
e35f5ad6a9
ASoC: meson: add tohdmitx DT bindings
Add the bindings and the related documentation for the audio hdmitx
control glue of the Amlogic g12a SoC family

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-05-16 12:13:27 +01:00
Wei Ni
7d8ac6b282 of: Add bindings of gpu hw throttle for Tegra soctherm
Add "nvidia,gpu-throt-level" property to set gpu hw
throttle level.

Signed-off-by: Wei Ni <wni@nvidia.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
2019-05-13 20:35:33 -07:00
Linus Torvalds
ea5aee6d97 We have a couple new features and changes in the core clk framework this time
around because we've finally gotten around to fixing some long standing issues.
 There's still work to do though, so this PR is largely laying down the
 foundation for all the driver changes to come in the next merge window.
 
 The first problem we're alleviating is how parents of clks are specified. With
 the new method, we should see lots of drivers migrate away from the current
 design of string comparisons on the entire clk tree to a more direct method
 where they can use clk_hw pointers or more localized names specified in DT or
 via clkdev. This should reduce our reliance on string comparisons for all the
 topology description logic that we've been using for years and hopefully speed
 some things up while avoiding problems we have with generating clk names.
 
 Beyond that we also got rid of the CLK_IS_BASIC flag because it wasn't really
 helping anyone and we introduced big-endian versions of the basic clk types so
 that we can get rid of clk_{readl,writel}(). Both of these are things that
 driver developers have tried to use over the years that I typically bat away
 during code reviews because they're not useful. It's great to see these two
 things go away so maintainers can save time not worrying about these things.
 
 On the driver side we got the usual collection of new SoC support and
 non-critical fixes and updates to existing code. The big topics that stand out
 are the new driver support for Mediatek MT8183 and MT8516 SoCs, Amlogic Meson8b
 and G12a SoCs, and the SiFive FU540 SoC. The other patches in the driver pile
 are mostly fixes for things that are being used for the first time or additions
 for clks that couldn't be tested before because there wasn't a consumer driver
 that exercised them. Details are below and also in the sub-maintainer tags.
 
 Core:
  - Remove clk_readl() and introduce BE versions of basic clk types
  - Rewrite how clk parents can be specified to allow DT/clkdev lookups
  - Removal of the CLK_IS_BASIC clk flag
  - Framework documentation updates and fixes
 
 New Drivers:
  - Support for STM32F769
  - AT91 sam9x60 PMC support
  - SiFive FU540 PRCI and PLL support
  - Qualcomm QCS404 CDSP clk support
  - Qualcomm QCS404 Turing clk support
  - Mediatek MT8183 clock support
  - Mediatek MT8516 clock support
  - Milbeaut M10V clk controller support
  - Support for Cirrus Logic Lochnagar clks
 
 Updates:
  - Rework AT91 sckc DT bindings
  - Fix slow RC oscillator issue on sama5d3
  - Mark UFS clk as critical on Hi-Silicon hi3660 SoCs
  - Various static analysis fixes/finds and const markings
  - Video Engine (ECLK) support on Aspeed SoCs
  - Xilinx ZynqMP Versal platform support
  - Convert Xilinx ZynqMP driver to be struct oriented
  - Fixes for Rockchip rk3328 and rk3288 SoCs
  - Sub-type for Rockchip SoCs where mux and divider aren't a single register
  - Remove SNVS clock from i.MX7UPL clock driver and bindings
  - Improve i.MX5 clock driver for i.MX50 support
  - Addition of ADC clock definition for Exynos 5410 SoC (Odroid XU)
  - Export a new clock for the MBUS controller on the A13
  - Allwinner H6 fixes to support a finer clocking of the video and VPU engines
  - Add g12a support in the Amlogic axg audio clock controller
  - Add missing PCI USB clock on Rensas RZ/N1
  - Add Z2 (Cortex-A53) clocks on Rensas R-Car E3 and RZ/G2E
  - A new helper DIV64_U64_ROUND_CLOSEST() in <linux/math64.h>
  - VPU and Video Decoder clocks on Amlogic Meson8b
  - Finally remove the wrong ABP Meson8b clock id
  - Add Video Decoder, PCIe PLL, and CPU Clocks on Amlogic G12A
  - Re-expose SAR_ADC_SEL and CTS_OSCIN on Amlogic G12A AO clock controller
  - Un-expose some Amlogic AXG-Audio input clocks IDs
 -----BEGIN PGP SIGNATURE-----
 
 iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAlzUabQRHHNib3lkQGtl
 cm5lbC5vcmcACgkQrQKIl8bklSUMmBAAr0WrvWa3s1Ue+lPfmehcAfeI2NkBPC/E
 uhKD+vHBil/Aha33tFTPtVjsZiaMuUETNGPppEUUrHgu4K3UMJZl0iYql6XNVP77
 OObIM5wqXoJ5Yv1e1G0p7X/Qztx7UxEtPwbXJ/9kNN2t6yzg4y8vD2cmXgV5KzHp
 yRUDFNbH9JEyWFbrPhPjD3Bk1PCwdmXNFQg/uYk79g3c84js9MCbWvIqVEuU3vps
 3/9lsDkhbp/flrSOA7D1eloQ6aPXdkLsFzDkJ+6mCA3zxsW/i2N38ZKVDTYG/5rx
 USh3Z0Vyd0f9pKlQqwe1tyr2PBJrYWTtcPBSDcdr4BI1209xseFe4TaqHw1IRKcB
 uYX0gtNTTcgx+8Znvp9y+hE8DhbVNpZvblZuab+rbfb/Gte2wC5/zvzEAz1EqPap
 43VYdi3JR9iWGsC/r4+5OdVFRgWmXFsn5ysQRLkRgE41fKRn7joGHhPS5xDTI0l/
 1rA/8Oh0GMAcSOQ0aSBtavmMCsyJJTjG7s6MpqiO5u/DHnb4MB1Jd0rEWNIjiVmJ
 cqS8II+EbaLWZgt9r3W7ePhkfpHlLw+c4mwI9lRF7Zo67Rz9lrlt1l9YxPnJHewN
 uTRn2ch5W90Jr289wymDNQZGGvCyr+nxKYlSd+kXjlH6poDn6bxYdKHgJexDYmZR
 NVylbizS6lg=
 =/uso
 -----END PGP SIGNATURE-----

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk framework updates from Stephen Boyd:
 "We have a couple new features and changes in the core clk framework
  this time around because we've finally gotten around to fixing some
  long standing issues. There's still work to do though, so this pull
  request is largely laying down the foundation for all the driver
  changes to come in the next merge window.

  The first problem we're alleviating is how parents of clks are
  specified. With the new method, we should see lots of drivers migrate
  away from the current design of string comparisons on the entire clk
  tree to a more direct method where they can use clk_hw pointers or
  more localized names specified in DT or via clkdev. This should reduce
  our reliance on string comparisons for all the topology description
  logic that we've been using for years and hopefully speed some things
  up while avoiding problems we have with generating clk names.

  Beyond that we also got rid of the CLK_IS_BASIC flag because it wasn't
  really helping anyone and we introduced big-endian versions of the
  basic clk types so that we can get rid of clk_{readl,writel}(). Both
  of these are things that driver developers have tried to use over the
  years that I typically bat away during code reviews because they're
  not useful. It's great to see these two things go away so maintainers
  can save time not worrying about these things.

  On the driver side we got the usual collection of new SoC support and
  non-critical fixes and updates to existing code. The big topics that
  stand out are the new driver support for Mediatek MT8183 and MT8516
  SoCs, Amlogic Meson8b and G12a SoCs, and the SiFive FU540 SoC. The
  other patches in the driver pile are mostly fixes for things that are
  being used for the first time or additions for clks that couldn't be
  tested before because there wasn't a consumer driver that exercised
  them. Details are below and also in the sub-maintainer tags.

  Core:
   - Remove clk_readl() and introduce BE versions of basic clk types
   - Rewrite how clk parents can be specified to allow DT/clkdev lookups
   - Removal of the CLK_IS_BASIC clk flag
   - Framework documentation updates and fixes

  New Drivers:
   - Support for STM32F769
   - AT91 sam9x60 PMC support
   - SiFive FU540 PRCI and PLL support
   - Qualcomm QCS404 CDSP clk support
   - Qualcomm QCS404 Turing clk support
   - Mediatek MT8183 clock support
   - Mediatek MT8516 clock support
   - Milbeaut M10V clk controller support
   - Support for Cirrus Logic Lochnagar clks

  Updates:
   - Rework AT91 sckc DT bindings
   - Fix slow RC oscillator issue on sama5d3
   - Mark UFS clk as critical on Hi-Silicon hi3660 SoCs
   - Various static analysis fixes/finds and const markings
   - Video Engine (ECLK) support on Aspeed SoCs
   - Xilinx ZynqMP Versal platform support
   - Convert Xilinx ZynqMP driver to be struct oriented
   - Fixes for Rockchip rk3328 and rk3288 SoCs
   - Sub-type for Rockchip SoCs where mux and divider aren't a single register
   - Remove SNVS clock from i.MX7UPL clock driver and bindings
   - Improve i.MX5 clock driver for i.MX50 support
   - Addition of ADC clock definition for Exynos 5410 SoC (Odroid XU)
   - Export a new clock for the MBUS controller on the A13
   - Allwinner H6 fixes to support a finer clocking of the video and VPU engines
   - Add g12a support in the Amlogic axg audio clock controller
   - Add missing PCI USB clock on Rensas RZ/N1
   - Add Z2 (Cortex-A53) clocks on Rensas R-Car E3 and RZ/G2E
   - A new helper DIV64_U64_ROUND_CLOSEST() in <linux/math64.h>
   - VPU and Video Decoder clocks on Amlogic Meson8b
   - Finally remove the wrong ABP Meson8b clock id
   - Add Video Decoder, PCIe PLL, and CPU Clocks on Amlogic G12A
   - Re-expose SAR_ADC_SEL and CTS_OSCIN on Amlogic G12A AO clock controller
   - Un-expose some Amlogic AXG-Audio input clocks IDs"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (172 commits)
  clk: Cache core in clk_fetch_parent_index() without names
  clk: imx: correct pfdv2 gate_bit/vld_bit operations
  clk: sifive: add a driver for the SiFive FU540 PRCI IP block
  clk: analogbits: add Wide-Range PLL library
  clk: imx: clk-pllv3: mark expected switch fall-throughs
  clk: imx8mq: Add dsi_ipg_div
  clk: imx: pllv4: add fractional-N pll support
  clk: sunxi-ng: Use the correct style for SPDX License Identifier
  clk: sprd: Use the correct style for SPDX License Identifier
  clk: renesas: Use the correct style for SPDX License Identifier
  clk: qcom: Use the correct style for SPDX License Identifier
  clk: davinci: Use the correct style for SPDX License Identifier
  clk: actions: Use the correct style for SPDX License Identifier
  clk: imx: keep uart clock on during system boot
  clk: imx: correct i.MX7D AV PLL num/denom offset
  dt-bindings: clk: add documentation for the SiFive PRCI driver
  clk: stm32mp1: Add ddrperfm clock
  clk: Remove CLK_IS_BASIC clk flag
  clock: milbeaut: Add Milbeaut M10V clock controller
  dt-bindings: clock: milbeaut: add Milbeaut clock description
  ...
2019-05-09 14:50:09 -07:00
Linus Torvalds
fe460a6df6 Pin control changes for v5.2:
Nex drivers:
 - New driver for Bitmain BM1880 pin controller
 - New driver for Mediatek MT8516
 - New driver for Cirrus Logich Lochnagar PMIC pins
 
 Updates:
 - Incremental development on Renesas SH-PFC
 - Incremental development on Intel pin controller and some
   particular updates for Cedarfork.
 - Pin configuration support in Allwinner SunXi drivers
 - Suspend/resume support in the NXP/Freescale i.MX8MQ driver
 - Support for more packaging of the ST Micro STM32
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABAgAGBQJc0ouWAAoJEEEQszewGV1zGe0P/jo3cOjcU1pZ1KUMWOBPdh4p
 7Ks3sjjDPpJ5JB8Vv9piXhlglZQMixh2PFsmsWYN35CP+4but1BJ9x2NqAOrKEnY
 3IJcaXxjyYLyqMlYTCLNLHcMca1Ku9KcGHMX0/5JKpM84qfrOMQmjzv9RMC9UcFb
 3AAZgDHKGdu6kqs6nm5l62z5bg+GKTzjuOZ+a+YsiOLHRHz2loGdP7egZy6VtmuQ
 L1bFibfJX6Nexmh/TF0iceX82385aPfU8AMbxdhfMUEI3OJqR4gtSEVOxzW1FJaA
 +Ursxeess7QiAyyStOTszccOsJJe6ZjThU25s5kVLPygx0+kv2Z94Vvyb+ii1yU+
 UWk1zbOcYkd1mPAA6NGgzrpLgUUrL8Wzz45OwZKFxLWHjNRB2vDI6p8ABL+TRlXA
 cHOSpszHbAh/oqEZ45WmqFC0S011xmniOSqHuGHxanKAYKQjdaxO/rHtWkrgsEAJ
 NybpV67Ar2UtW2/3VqQHV97FcPzXoUMorn1qFs8aZeFxkqjnEMXP4zCgujLeJNn7
 Aa8Q9pWAOspMaudD96BUNsbjavn8PLRtzkOGRtL/Hfzfnt03SDTHUcrlxrwQr1fq
 dpw1bn2XIOjWwgzyrYXJhQAVOADuRks7wSVAP+/Vg2Gke8XmzAJ4x9tiLKDy7oyE
 DReRSj47xF01ns2AY9Bu
 =ovk5
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "It is pretty calm and chill in pin control for the moment. Just
  incremental development.

  There is an odd patch to the Super-H architecture, it's coming from
  the maintainers so should be fine.

  Summary:

  New drivers:
   - Bitmain BM1880 pin controller
   - Mediatek MT8516
   - Cirrus Logich Lochnagar PMIC pins

  Updates:
   - Incremental development on Renesas SH-PFC
   - Incremental development on Intel pin controller and some particular
     updates for Cedarfork.
   - Pin configuration support in Allwinner SunXi drivers
   - Suspend/resume support in the NXP/Freescale i.MX8MQ driver
   - Support for more packaging of the ST Micro STM32"

* tag 'pinctrl-v5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits)
  pinctrl: mcp23s08: Do not complain about unsupported params
  pinctrl: Rework Kconfig dependency for BM1880 pinctrl driver
  MAINTAINERS: Add entry for BM1880 pinctrl
  pinctrl: Add pinctrl support for BM1880 SoC
  dt-bindings: pinctrl: Add BM1880 pinctrl binding
  pinctrl: stm32: check irq controller availability at probe
  pinctrl: mediatek: Add MT8516 Pinctrl driver
  pinctrl: zte: fix leaked of_node references
  pinctrl: intel: Increase readability of intel_gpio_update_pad_mode()
  pinctrl: intel: Retain HOSTSW_OWN for requested gpio pin
  pinctrl: pistachio: fix leaked of_node references
  pinctrl: sunxi: Support I/O bias voltage setting on H6
  pinctrl: sunxi: Prepare for alternative bias voltage setting methods
  pinctrl: st: fix leaked of_node references
  pinctrl: samsung: fix leaked of_node references
  pinctrl: stm32: align stm32mp157 pin names
  pinctrl: stm32: add package information for stm32mp157c
  pinctrl: stm32: introduce package support
  dt-bindings: pinctrl: stm32: add new entry for package information
  pinctrl: imx8mq: Add suspend/resume ops
  ...
2019-05-08 10:23:54 -07:00
Linus Torvalds
132d68d37d USB/PHY patches for 5.2-rc1
Here is the big set of USB and PHY driver patches for 5.2-rc1
 
 There is the usual set of:
 	- USB gadget updates
 	- PHY driver updates and additions
 	- USB serial driver updates and fixes
 	- typec updates and new chips supported
 	- mtu3 driver updates
 	- xhci driver updates
 	- other tiny driver updates
 
 Nothing really interesting, just constant forward progress.
 
 All of these have been in linux-next for a while with no reported
 issues.  The usb-gadget and usb-serial trees were merged a bit "late",
 but both of them had been in linux-next before they got merged here last
 Friday.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCXNKuwg8cZ3JlZ0Brcm9h
 aC5jb20ACgkQMUfUDdst+ymRUgCfa8Ri7KrCaBR5NHQcLhbdrX90ToQAmgNw7vpo
 fqt0XpNM0CSa9O/gOr79
 =8HFh
 -----END PGP SIGNATURE-----

Merge tag 'usb-5.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb

Pull USB/PHY updates from Greg KH:
 "Here is the big set of USB and PHY driver patches for 5.2-rc1

  There is the usual set of:

   - USB gadget updates

   - PHY driver updates and additions

   - USB serial driver updates and fixes

   - typec updates and new chips supported

   - mtu3 driver updates

   - xhci driver updates

   - other tiny driver updates

  Nothing really interesting, just constant forward progress.

  All of these have been in linux-next for a while with no reported
  issues. The usb-gadget and usb-serial trees were merged a bit "late",
  but both of them had been in linux-next before they got merged here
  last Friday"

* tag 'usb-5.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (206 commits)
  USB: serial: f81232: implement break control
  USB: serial: f81232: add high baud rate support
  USB: serial: f81232: clear overrun flag
  USB: serial: f81232: fix interrupt worker not stop
  usb: dwc3: Rename DWC3_DCTL_LPM_ERRATA
  usb: dwc3: Fix default lpm_nyet_threshold value
  usb: dwc3: debug: Print GET_STATUS(device) tracepoint
  usb: dwc3: Do core validation early on probe
  usb: dwc3: gadget: Set lpm_capable
  usb: gadget: atmel: tie wake lock to running clock
  usb: gadget: atmel: support USB suspend
  usb: gadget: atmel_usba_udc: simplify setting of interrupt-enabled mask
  dwc2: gadget: Fix completed transfer size calculation in DDMA
  usb: dwc2: Set lpm mode parameters depend on HW configuration
  usb: dwc2: Fix channel disable flow
  usb: dwc2: Set actual frame number for completed ISOC transfer
  usb: gadget: do not use __constant_cpu_to_le16
  usb: dwc2: gadget: Increase descriptors count for ISOC's
  usb: introduce usb_ep_type_string() function
  usb: dwc3: move synchronize_irq() out of the spinlock protected block
  ...
2019-05-08 10:03:52 -07:00
Stephen Boyd
ff060019f4 Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and 'clk-spdx' into clk-next
- Support for STM32F769
 - Rework AT91 sckc DT bindings
 - Fix slow RC oscillator issue on sama5d3
 - AT91 sam9x60 PMC support
 - SiFive FU540 PRCI and PLL support

* clk-stm32f4:
  clk: stm32mp1: Add ddrperfm clock
  clk: stm32: Introduce clocks of STM32F769 board

* clk-tegra:
  clk: tegra: divider: Mark Memory Controller clock as read-only
  clk: tegra: emc: Replace BUG() with WARN_ONCE()
  clk: tegra: emc: Fix EMC max-rate clamping
  clk: tegra: emc: Support multiple RAM codes
  clk: tegra: emc: Don't enable EMC clock manually
  clk: tegra124: Remove lock-enable bit from PLLM
  clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider
  clk: tegra: Don't enable already enabled PLLs

* clk-at91:
  clk: at91: Mark struct clk_range as const
  clk: at91: add sam9x60 pmc driver
  dt-bindings: clk: at91: add bindings for SAM9X60 pmc
  clk: at91: add sam9x60 PLL driver
  clk: at91: master: Add sam9x60 support
  clk: at91: usb: Add sam9x60 support
  clk: at91: allow configuring generated PCR layout
  clk: at91: allow configuring peripheral PCR layout
  clk: at91: sckc: handle different RC startup time
  clk: at91: modernize sckc binding
  dt-bindings: clock: at91: new sckc bindings

* clk-sifive-fu540:
  clk: sifive: add a driver for the SiFive FU540 PRCI IP block
  clk: analogbits: add Wide-Range PLL library
  dt-bindings: clk: add documentation for the SiFive PRCI driver

* clk-spdx:
  clk: sunxi-ng: Use the correct style for SPDX License Identifier
  clk: sprd: Use the correct style for SPDX License Identifier
  clk: renesas: Use the correct style for SPDX License Identifier
  clk: qcom: Use the correct style for SPDX License Identifier
  clk: davinci: Use the correct style for SPDX License Identifier
  clk: actions: Use the correct style for SPDX License Identifier
2019-05-07 11:45:29 -07:00
Stephen Boyd
5816b74581 Merge branches 'clk-hisi', 'clk-lochnagar', 'clk-allwinner', 'clk-rockchip' and 'clk-qoriq' into clk-next
- Mark UFS clk as critical on Hi-Silicon hi3660 SoCs
 - Support for Cirrus Logic Lochnagar clks

* clk-hisi:
  clk: hi3660: Mark clk_gate_ufs_subsys as critical

* clk-lochnagar:
  clk: lochnagar: Add support for the Cirrus Logic Lochnagar
  clk: lochnagar: Add initial binding documentation

* clk-allwinner:
  clk: sunxi-ng: sun5i: Export the MBUS clock
  clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclk
  clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rate
  clk: sunxi-ng: h6: Preset hdmi-cec clock parent
  clk: sunxi: Add Kconfig options
  clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset
  clk: sunxi-ng: Allow DE clock to set parent rate

* clk-rockchip:
  clk: rockchip: undo several noc and special clocks as critical on rk3288
  clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type
  clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288
  clk: rockchip: Limit use of USB PHY clock to USB on rk3288
  clk: rockchip: Fix video codec clocks on rk3288
  clk: rockchip: Make rkpwm a critical clock on rk3288
  clk: rockchip: fix wrong clock definitions for rk3328

* clk-qoriq:
  clk: qoriq: increase array size of cmux_to_group
  dt-bindings: qoriq-clock: Add ls1028a chip compatible string
  clk: qoriq: Add ls1028a clock configuration
  clk: qoriq: add more PLL divider clocks support
  dt-bindings: qoriq-clock: add more PLL divider clocks support
2019-05-07 11:45:13 -07:00
Stephen Boyd
7e9c62bdb4 Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-zynq' into clk-next
- Various static analysis fixes/finds
 - Video Engine (ECLK) support on Aspeed SoCs
 - Xilinx ZynqMP Versal platform support
 - Convert Xilinx ZynqMP driver to be struct oriented

* clk-sa:
  clk: mvebu: fix spelling mistake "gatable" -> "gateable"
  clk: ux500: add range to usleep_range
  clk: tegra: Make tegra_clk_super_mux_ops static
  clk: davinci: cfgchip: use PTR_ERR_OR_ZERO in da8xx_cfgchip_register_div4p5

* clk-aspeed:
  clk: Aspeed: Setup video engine clocking

* clk-samsung:
  clk: samsung: exynos5410: Add gate clock for ADC
  clk: samsung: dt-bindings: Add ADC clock ID to Exynos5410
  clk: samsung: dt-bindings: Put CLK_UART3 in order

* clk-ingenic:
  clk: ingenic: jz4725b: Add UDC PHY clock
  dt-bindings: clock: jz4725b-cgu: Add UDC PHY clock

* clk-zynq:
  clk: zynqmp: use structs for clk query responses
  clk: zynqmp: fix check for fractional clock
  clk: zynqmp: do not export zynqmp_clk_register_* functions
  clk: zynqmp: fix kerneldoc of __zynqmp_clock_get_parents
  drivers: clk: Update clock driver to handle clock attribute
  drivers: clk: zynqmp: Allow zero divisor value
2019-05-07 11:44:56 -07:00
Stephen Boyd
f6111b9d79 Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and 'clk-basic-be' into clk-next
- Remove clk_readl() and introduce BE versions of basic clk types

* clk-doc:
  clk: Drop duplicate clk_register() documentation
  clk: Document and simplify clk_core_get_rate_nolock()
  clk: Remove 'flags' member of struct clk_fixed_rate
  clk: nxp: Drop 'flags' on fixed_rate clk macro
  clk: Document __clk_mux_determine_rate()
  clk: Document CLK_MUX_READ_ONLY mux flag
  clk: Document deprecated things
  clk: Collapse gpio clk kerneldoc

* clk-more-critical:
  clk: highbank: Convert to CLK_IS_CRITICAL

* clk-meson: (21 commits)
  clk: meson: axg-audio: add g12a support
  clk: meson: axg-audio: don't register inputs in the onecell data
  clk: meson: axg_audio: replace prefix axg by aud
  dt-bindings: clk: axg-audio: add g12a support
  clk: meson: meson8b: add the video decoder clock trees
  clk: meson: meson8b: add the VPU clock trees
  clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2
  clk: meson: meson8b: use a separate clock table for Meson8m2
  dt-bindings: clock: meson8b: export the video decoder clocks
  clk: meson-g12a: add video decoder clocks
  dt-bindings: clock: meson8b: export the VPU clock
  clk: meson-g12a: add PCIE PLL clocks
  dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN
  clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL
  dt-bindings: clock: meson8b: drop the "ABP" clock definition
  clk: meson: g12a: add cpu clocks
  dt-bindings: clk: g12a-clkc: add VDEC clock IDs
  dt-bindings: clock: axg-audio: unexpose controller inputs
  dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID
  clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id
  ...

* clk-basic-be:
  clk: core: replace clk_{readl,writel} with {readl,writel}
  clk: core: remove powerpc special handling
  powerpc/512x: mark clocks as big endian
  clk: mux: add explicit big endian support
  clk: multiplier: add explicit big endian support
  clk: gate: add explicit big endian support
  clk: fractional-divider: add explicit big endian support
  clk: divider: add explicit big endian support
2019-05-07 11:44:42 -07:00
Stephen Boyd
2ed3b9103a Merge branches 'clk-renesas', 'clk-qcom', 'clk-mtk', 'clk-milbeaut' and 'clk-imx' into clk-next
- Qualcomm QCS404 CDSP clk support
 - Qualcomm QCS404 Turing clk support
 - Mediatek MT8183 clock support
 - Mediatek MT8516 clock support
 - Milbeaut M10V clk controller support

* clk-renesas:
  clk: renesas: rcar-gen3: Remove unused variable
  clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return value
  clk: renesas: r8a77980: Fix RPC-IF module clock's parent
  clk: renesas: rcar-gen3: Rename DRIF clocks
  clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC
  clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC
  clk: renesas: rcar-gen3: Correct parent clock of HS-USB
  clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI
  clk: renesas: r8a774c0: Add Z2 clock
  clk: renesas: r8a77990: Add Z2 clock
  clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents
  math64: New DIV64_U64_ROUND_CLOSEST helper
  clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2
  clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset
  clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor
  clk: renesas: r9a06g032: Add missing PCI USB clock
  clk: renesas: r7s9210: Always use readl()
  clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register()

* clk-qcom:
  clk: qcom: Skip halt checks on gcc_pcie_0_pipe_clk for 8998
  clk: qcom: Add QCS404 TuringCC
  clk: qcom: branch: Add AON clock ops
  dt-bindings: clock: Introduce Qualcomm Turing Clock controller
  clk: qcom: gcc-qcs404: Add CDSP related clocks and resets

* clk-mtk:
  clk: mediatek: add clock driver for MT8516
  dt-bindings: mediatek: apmixedsys: add support for MT8516
  dt-bindings: mediatek: infracfg: add support for MT8516
  dt-bindings: mediatek: topckgen: add support for MT8516
  clk: mediatek: Allow changing PLL rate when it is off
  clk: mediatek: Add MT8183 clock support
  clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data
  clk: mediatek: Add dt-bindings for MT8183 clocks
  dt-bindings: ARM: Mediatek: Document bindings for MT8183
  clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data
  clk: mediatek: Add new clkmux register API
  clk: mediatek: Disable tuner_en before change PLL rate

* clk-milbeaut:
  clock: milbeaut: Add Milbeaut M10V clock controller
  dt-bindings: clock: milbeaut: add Milbeaut clock description

* clk-imx:
  clk: imx: correct pfdv2 gate_bit/vld_bit operations
  clk: imx: clk-pllv3: mark expected switch fall-throughs
  clk: imx8mq: Add dsi_ipg_div
  clk: imx: pllv4: add fractional-N pll support
  clk: imx: keep uart clock on during system boot
  clk: imx: correct i.MX7D AV PLL num/denom offset
  clk: imx6sll: Fix mispelling uart4_serial as serail
  clk: imx: pll14xx: drop unused variable
  clk: imx: rename clk-imx51-imx53.c to clk-imx5.c
  clk: imx5: Fix i.MX50 ESDHC clock registers
  clk: imx5: Fix i.MX50 mainbus clock registers
  clk: imx: Remove unused imx_get_clk_hw_fixed
  dt-bindings: clock: imx7ulp: remove SNVS clock
  clk: imx7ulp: remove snvs clock
2019-05-07 11:44:21 -07:00
Greg Kroah-Hartman
12456e509b Merge 5.1-rc7 into usb-next
We need this to make the usb-gadget branch merge cleaner.  And for
testing to keep from hitting the same issues already fixed.

Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-03 18:03:47 +02:00
Olof Johansson
b45da609a0 i.MX DT bindings update for 5.2:
- Add vendor prefix for TQ Systems GmbH, Rakuten Kobo and Menlo Systems
    GmbH.
  - Add DT schema for SoC i.MX8MM and i.MX50, and board ZII VF610, VF610
    SPB4, i.MX7 RPU2, i.MX7S TQ MBa7, M53 Menlo and Eckelmann ci4x10.
  - Update imx-scu bindings on resource table and general interrupt
    support.
  - Add bindings for i.MX MMDC memory controller.
  - Update i.MX7D ADC bindings to add missing '#io-channel-cells'
    property.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJcvm+bAAoJEFBXWFqHsHzOXNwH/1j1FWhg2wQ62qg/KAGfE2F7
 dppWD6ZP+f59+x9yb2SJAo6NIKMJt1J08vqkEzZGxkm/KWhmKbEseV3aY8VqZ7xJ
 03EhbaFBwyI1uaJe1lNsFlwFU41UeRMahDtxzYh2prTS7fvQHRAAj52HiiFoBR/l
 tjMENxCJD0fkTe9MPAp9kYOxYV7Fm2UuSpAV/8PvbjgR4M7mOg5E/k6eClHs890X
 dp9fy3/NI+Y6u+gRj9zpNR4Vhaw5UWnd6hLbaq9DRbcWTUwrw7qrQcRdV6yOTAMw
 wNKw3fCSUDOamkjOs+XqcBfHuVdxpaMi3/LWD8AwFgTIZCn1A94Kb9JwczY0lKg=
 =lvhK
 -----END PGP SIGNATURE-----

Merge tag 'imx-bindings-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX DT bindings update for 5.2:
 - Add vendor prefix for TQ Systems GmbH, Rakuten Kobo and Menlo Systems
   GmbH.
 - Add DT schema for SoC i.MX8MM and i.MX50, and board ZII VF610, VF610
   SPB4, i.MX7 RPU2, i.MX7S TQ MBa7, M53 Menlo and Eckelmann ci4x10.
 - Update imx-scu bindings on resource table and general interrupt
   support.
 - Add bindings for i.MX MMDC memory controller.
 - Update i.MX7D ADC bindings to add missing '#io-channel-cells'
   property.

* tag 'imx-bindings-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  dt-bindings: iio: imx7d-adc: Add #io-channel-cells to required
  dt-bindings: arm: fsl: Add support for ZII i.MX7 RPU2 board
  dt-bindings: arm: fsl: Add devicetree binding for M53 Menlo board.
  dt-bindings: fsl: scu: add general interrupt support
  dt-bindings: arm: fsl: Add i.MX50 based boards
  dt-bindings: Add vendor prefix for Rakuten Kobo, Inc.
  dt-bindings: arm: add TQ boards
  dt-bindings: add vendor prefix for TQ Systems GmbH
  dt-bindings: arm: fsl: Add support for ZII VF610 SPB4
  dt-bindings: arm: fsl: Add supported ZII VF610 boards to DT schema
  dt-bindings: arm: imx: Add the soc binding for imx8mm
  dt-bindings: arm: fsl: Add devicetree binding for Eckelmann ci4x10
  dt-bindings: memory-controllers: freescale: add MMDC binding doc
  of: Add vendor prefix for Menlo Systems GmbH
  bindings: fsl-imx-sdma: Document fsl,imx8mq-sdma compatbile string
  dt-bindings: firmware: imx-scu: add new resources to scu resource table
  dt-bindings: firmware: imx-scu: remove unused resources from scu resource table

Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-28 12:50:38 -07:00
Olof Johansson
1e67323721 arm64: dts: Amlogic updates for v5.2, round 2
- add display/gfx support for G12a boards
 - enable USB for g12a boards
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAly8ghgACgkQWTcYmtP7
 xmXqyg/9HtVrO5aNLEmGi3l/YySSH7fSp5BNnvTzlT8SpB1vBAKLXWjemVss2XVE
 QEE7d1UyUoXwgE4GoAyguuuj0Ov+JwYRTQb+OZKliALPlHfQQkklN8FKVMnDzEz7
 u1ivVqmoXzwqW32NW3a24AyGLgQXgJi2+ctAZSGNd+pLydwANLCB+Ffc1I4fTmW0
 kwLnqBgyVMxhbgRw6Blj9nh+ZlQOLwktpiMfrOwIpV0WLT3LZdRMrY1M/SnP+4+B
 Pq2BEzBAaHC5cNjQ3TjEj+nckXnrncJ0V6DepT+UIOC8L61rsb/tQAx8ecVVoHcW
 TTsQ3fewNcqIrKLRFpyNpXEAEAzlciwpV8lDczY5fLv5/j0MHiRSwBctj1pcK+CF
 Rsl2NygGZv0SuU0hDsDfEzVGLPjD1VYVGSJezWaaNzhjLw4sDUylBsKOcMNui4fW
 IUT3ahdjtvp03xjlGWAd1NI/MkYuu3RxJ2wR28vPEUGu2JEVpI8PtkR1FVqRIwBU
 Qd20x3bAn76zxMSWrsmDiTAa0+HMqjUbhzyeJxKPV5ON5k7RbmADrQ2rvxx+E4Uj
 FR3S6iulwaXDxIrvKZvTJDX3Myf2EL0bck5/XlKrD/B8tN5dCBgySA+SGHLhIiwZ
 XpCQmP6nLzZayeU4TX7jvAQdbhmR5GYCpO7SsIFTz7fJr6Vb8lM=
 =T6Im
 -----END PGP SIGNATURE-----

Merge tag 'amlogic-dt64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt

arm64: dts: Amlogic updates for v5.2, round 2
- add display/gfx support for G12a boards
- enable USB for g12a boards

* tag 'amlogic-dt64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (26 commits)
  arm64: dts: meson-g12a-u200: Add support for Video Display
  arm64: dts: meson-g12a-sei510: Add support for Video Display
  arm64: dts: meson-g12a-x96-max: Add support for Video Display
  arm64: dts: meson-g12a: Add AO-CEC nodes
  arm64: dts: meson-g12a: Add VPU and HDMI related nodes
  arm64: dts: meson-g12a-x96-max: Enable USB
  arm64: dts: meson-g12a-u200: Enable USB
  arm64: dts: meson-g12a-sei510: Enable USB
  arm64: dts: meson-g12a-sei510: Add ADC Key and BT support
  arm64: dts: meson-g12a-u200: add regulators
  arm64: dts: meson: g12a: Add mali-g31 gpu node
  arm64: dts: meson: g12a: Add G12A USB nodes
  arm64: dts: meson: g12a: Add SAR ADC node
  dt-bindings: power: amlogic, meson-gx-pwrc: Add G12A compatible
  arm64: dts: meson-gxm: Add Mali-T820 node
  dt-bindings: gpu: mali-midgard: Add resets property
  dt-bindings: clock: meson8b: export the video decoder clocks
  dt-bindings: clock: meson8b: export the VPU clock
  dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN
  dt-bindings: clock: meson8b: drop the "ABP" clock definition
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-28 12:50:02 -07:00
Olof Johansson
ea1b42170f Renesas ARM Based SoC DT Bindings Updates for v5.2
* R-Car M3-N (r8a77965) SoC
   - Remove non-existent A3IR power domain
 
 * Add vendor prefix for Silicon Linux
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAly521wACgkQ189kaWo3
 T771vhAAjLwe/q0/d0bLpWOmIPieWcXrtp6yhpSnV5adGWvdL3NqCeNb4P/MMEwm
 wpGSgPb2WfDpSOTc9rqId9J/QzCvXUyuTdl63tFIUxQbA3lyow+YtpgGKic1zHA1
 baAgsypQIhnMal27ggKcDQaViJR+mXDVYnk/l8059vNKT7RbWAOspCqZ3Bj2caDG
 CJcIVDOqUG/P+4Ybpj0WSsoB/wEsuP1BGdZJAZ3EhrLP+QMWSHnWaJC+tHLq7IMo
 8xgOnqeEfh3qNLnFrAcNM8NID11PQm6xRT4xIXhE9lqXlwISxk7+6z9NlStlEA9S
 JTeEE1bqov2b+MXkLVV6DOa0y54YVSk+T4Ap+al0aX5O+IjNXY8GZyFMIb4VuvJW
 m34vRUxnTUbL5q/DCwwQ0uD/DZWDLKkF/KOru0I+LGDV+oA+5rawXqykM66rnZ3V
 5qzdNkizVTGV2GHfgaoZRksiZ0RZJOzqgRAIsXzgFcaxEn5o9uVe2UVneb5+pYtr
 6OP5J7ksEBU/VVAThpoX0mVWhjM/IWph/DDSSslotGwLYeUzSjqHixopOclXHukV
 6JiUKnOe/Q1IuIIRy+xoDrK7wmzC15rKqkNmK4nWJP+WmmCtXlkn2Nsqybq2tiF0
 R2KhjAGszN0/SBw6/3PhyEc3pW0m01BL2jzKJ2nTTMJeUu3RgkY=
 =8e0v
 -----END PGP SIGNATURE-----

Merge tag 'renesas-dt-bindings-for-v5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/dt

Renesas ARM Based SoC DT Bindings Updates for v5.2

* R-Car M3-N (r8a77965) SoC
  - Remove non-existent A3IR power domain

* Add vendor prefix for Silicon Linux

* tag 'renesas-dt-bindings-for-v5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  dt-bindings: power: r8a77965: Remove non-existent A3IR power domain
  dt-bindings: Add vendor prefix for Silicon Linux.

Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-28 12:46:39 -07:00
Olof Johansson
7996313656 Add am335x pinmux defines and start using them
This series of changes adds a new pinmux instance defines for am335x,
 and a new AM33XX_PADCONF macro. And then the rest of the series updates
 the dts files to use it.
 
 The reasons for doing this is the pinmux configuration has been hard to
 use and read. And we need to do this for eventually for moving to use
 values.
 
 This change is done one machine at a time, and can be easily reverted
 as needed in case of unexpected trouble. The old macro is still working,
 and we're planning to keep it around until we eventually change to use
 -----BEGIN PGP SIGNATURE-----
 
 iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAly18IoRHHRvbnlAYXRv
 bWlkZS5jb20ACgkQG9Q+yVyrpXPwQA//ajq5abErjoCtPQrf/4bv9NdZQcBkRaHa
 k4pZ8hgWvLQYzNDZirQhe174UUCUUIdc7yppRYzgjqYmWLvNHSs4ax9SeBKn1bHd
 40gZMzmJeHByRNjK1WHHUBLXtuMRIbOk7k4Lcgqi3en1a9jHnJaq0h/Xde69nrWz
 rjcewWEbZeqYvIRZJDv17vbY3DY6gebP3DQzKLEX89vTfMJF0vgTm6YVskhW1Jtx
 3Coj/M5e3//gDRBD8bpLdOac1irQe2+MMFMh4GH9ctF9/ZK45cXKz3p8j+em0YgJ
 yYXimAFqVY0lQuFNC6L/PfsQ8YDSuVTHqTS6vajZvqoDB4wMsYjw8ivag5S0NpqV
 baaft1SyQ1x7YeuKny/jSZ+1vYIe2Omms45Dc3JYLX2EltLDDEzriPpohIcqetOp
 XJfxAEFbAU9Mk1tMSS8hvpoj9ezodQz3tYS8Mwc15Dg2SDfT7yya1kDowOpVa9sn
 MKvFZ5jIfYdq3es/vDm9sa0qunmQBX1iM5Jzp1u+GUYa5p7kTcojCd++FoR7/do5
 R2V96N8NaxUTATCEpMCxCJsSYeQrc4ZmnUWBHRVntQJrPxolTwRpH3yEWMBFN4l1
 7XU56mEkDzXQMnHJbrzOyNWa/iAmYqUJXU9WbvrmMOv3ZMro7NqIl5mD46XkBBBK
 8BzayzP1QRg=
 =QimO
 -----END PGP SIGNATURE-----

Merge tag 'omap-for-v5.2/dt-am3-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt

Add am335x pinmux defines and start using them

This series of changes adds a new pinmux instance defines for am335x,
and a new AM33XX_PADCONF macro. And then the rest of the series updates
the dts files to use it.

The reasons for doing this is the pinmux configuration has been hard to
use and read. And we need to do this for eventually for moving to use
values.

This change is done one machine at a time, and can be easily reverted
as needed in case of unexpected trouble. The old macro is still working,
and we're planning to keep it around until we eventually change to use

* tag 'omap-for-v5.2/dt-am3-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (38 commits)
  ARM: dts: am335x: wega: Replaced register offsets with defines
  ARM: dts: am335x: sl50: Replaced register offsets with defines
  ARM: dts: am335x: shc: Replaced register offsets with defines
  ARM: dts: am335x: sbc-t335: Replaced register offsets with defines
  ARM: dts: am335x: sancloud-bbe: Replaced register offsets with defines
  ARM: dts: am335x: phycore-som: Replaced register offsets with defines
  ARM: dts: am335x: pepper: Replaced register offsets with defines
  ARM: dts: am335x: pdu001: Replaced register offsets with defines
  ARM: dts: am335x: pcm-953: Replaced register offsets with defines
  ARM: dts: am335x: osd335x-common: Replaced register offsets with defines
  ARM: dts: am335x: osd3358-sm-red: Replaced register offsets with defines
  ARM: dts: am335x: nano: Replaced register offsets with defines
  ARM: dts: am335x: moxa-uc-8100-me-t: Replaced register offsets with defines
  ARM: dts: am335x: moxa-uc-2101: Replaced register offsets with defines
  ARM: dts: am335x: moxa-uc-2100-common: Replaced register offsets with defines
  ARM: dts: am335x: lxm: Replaced register offsets with defines
  ARM: dts: am335x: igep0033: Replaced register offsets with defines
  ARM: dts: am335x: icev2: Replaced register offsets with defines
  ARM: dts: am335x: evmsk: Replaced register offsets with defines
  ARM: dts: am335x: evm: Replaced register offsets with defines
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-28 12:38:35 -07:00
Fabien Parent
699480d062 dt-bindings: mediatek: apmixedsys: add support for MT8516
Add binding documentation of apmixedsys for MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-25 14:35:29 -07:00
Fabien Parent
eb2814bc60 dt-bindings: mediatek: infracfg: add support for MT8516
Add binding documentation of infracfg for MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-25 14:34:34 -07:00
Fabien Parent
67ea15169b dt-bindings: mediatek: topckgen: add support for MT8516
Add binding documentation of topckgen for MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-25 14:32:51 -07:00
Gabriel Fernandez
936289f047 clk: stm32: Introduce clocks of STM32F769 board
STM32F769 clocks are derived from STM32746 clocks.
main differences are:
- new source clock for SAI1 and SAI2 (HSI or HSE)
- Add DFSDM & DSI clocks

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-25 11:46:36 -07:00
Alexandre Torgue
966d9b928f dt-bindings: pinctrl: stm32: add new entry for package information
Add "st,package" entry. Possibles values are:
-STM32MP_PKG_AA for LFBGA448 (18*18) package
-STM32MP_PKG_AB for LFBGA354 (16*16) package
-STM32MP_PKG_AC for TFBGA361 (12*12) package
-STM32MP_PKG_AD for TFBGA257 (10*10) package

Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 10:46:37 +02:00
Greg Kroah-Hartman
817de6b859 Merge 5.1-rc6 into staging-next
We want the fixes in here as well as this resolves an iio driver merge
issue.

Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-04-21 23:18:44 +02:00
Kishon Vijay Abraham I
4e0ae876f7 dt-bindings: phy: ti: Add dt binding documentation for SERDES in AM654x SoC
AM654x has two SERDES instances. Each instance has three input clocks
(left input, externel reference clock and right input) and two output
clocks (left output and right output) in addition to a PLL mux clock
which the SERDES uses for Clock Multiplier Unit (CMU refclock).
The PLL mux clock can select from one of the three input clocks.
The right output can select between left input and external reference
clock while the left output can select between the right input and
external reference clock.

The left and right input reference clock of SERDES0 and SERDES1
respectively are connected to the SoC clock. In the case of two lane
SERDES personality card, the left input of SERDES1 is connected to
the right output of SERDES0 in a chained fashion.

See section "Reference Clock Distribution" of AM65x Sitara Processors
TRM (SPRUID7 – April 2018) for more details.

Add dt-binding documentation in order to represent all these different
configurations in device tree.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17 14:13:18 +05:30
Kevin Hilman
55fbc7287e Merge branch 'reset/meson-g12a' of git://git.pengutronix.de/pza/linux into v5.2/dt64
* 'reset/meson-g12a' of git://git.pengutronix.de/pza/linux:
  dt-bindings: reset: meson-g12a: Add missing USB2 PHY resets
2019-04-15 15:43:03 -07:00
Paul Cercueil
93dc07f8b0 dt-bindings: clock: jz4725b-cgu: Add UDC PHY clock
Add macro for the UDC PHY clock of the JZ4725B.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-11 13:40:58 -07:00
Bjorn Andersson
5f19c6e936 dt-bindings: clock: Introduce Qualcomm Turing Clock controller
Add devicetree binding for the turing clock controller found in QCS404.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-11 13:34:10 -07:00
Bjorn Andersson
8bc7a04bb7 clk: qcom: gcc-qcs404: Add CDSP related clocks and resets
Add the clocks and resets need in order to control the Turing
remoteproc.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-11 13:32:20 -07:00
Weiyi Lu
d90240bc07 clk: mediatek: Add dt-bindings for MT8183 clocks
Add MT8183 clock dt-bindings, include topckgen, apmixedsys,
infracfg, mcucfg and subsystem clocks.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-11 13:15:39 -07:00
Maxime Ripard
c77cebac96
clk: sunxi-ng: sun5i: Export the MBUS clock
The MBUS clock is used by the MBUS controller, so let's export it so that
we can use it in our DT node.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-10 16:33:01 +02:00
Paul Walmsley
6ec4bae178
dt-bindings: clock: sifive: add FU540-C000 PRCI clock constants
Add preprocessor macros for the important PRCI output clocks
that are needed by both the FU540 PRCI driver and DT data.
Details are available in the FU540 manual in Chapter 7 of

    https://static.dev.sifive.com/FU540-C000-v1.0.pdf

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-04-09 20:36:40 -07:00
Christina Quast
f1ff9be765 ARM: dts: am33xx: Added AM33XX_PADCONF macro
AM33XX_PADCONF takes three instead of two parameters, to make
future changes to #pinctrl-cells easier.

For old boards which are not mainlined, we left the AM33XX_IOPAD
macro.

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-08 10:01:51 -07:00
Christina Quast
7ebd1ea798 ARM: dts: am33xx: Added macros for numeric pinmux addresses
The values are extraced from the "AM335x SitaraTM Processors Technical
Reference Manual", Section 9.3.1 CONTROL_MODULE Registers, based on the
file autogenerated by TI PinMux.

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-08 10:01:50 -07:00
Jerome Brunet
8554926b3f dt-bindings: clk: axg-audio: add g12a support
Add a new compatible string and additional clock ids for audio clock
controller of the g12a SoC family.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190329160649.31603-2-jbrunet@baylibre.com
2019-04-08 09:57:13 +02:00
Patrick Havelange
023e41632e dt-bindings: iio/temperature: Add thermocouple types (and doc)
This patch introduces common thermocouple types used by various
temperature sensors. Also a brief documentation explaining this
"thermocouple-type" property.

Signed-off-by: Patrick Havelange <patrick.havelange@essensium.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2019-04-04 20:21:01 +01:00
Martin Blumenstingl
77a725ff7a dt-bindings: clock: meson8b: export the video decoder clocks
Export the four video decoder clocks so they can be used by the video
decoder driver:
- VDEC_1
- VDEC_HCODEC
- VDEC_2
- VDEC_HEVC

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190324151423.19063-2-martin.blumenstingl@googlemail.com
2019-04-01 10:45:11 +02:00
Martin Blumenstingl
ba1ce88efa dt-bindings: clock: meson8b: export the VPU clock
The VPU clock is an input the the "VPU" (Video Processing Unit), which is
one of the components of the display controller.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190324151104.18397-2-martin.blumenstingl@googlemail.com
2019-04-01 10:45:11 +02:00
Neil Armstrong
133bb341b9 dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN
When submitted v2 of the G12A AO-CLK IDs, the CLKID_AO_CTS_OSCIN was moved
to the internal non-exported bindings, but this clock is necessary for
the second AO-CEC-B module since it embeds the 32768Hz dual-divider
clock generator unlike the AO-CEC-A module.

Export it back to the public bindings.

Fixes: be3d960b0a ("dt-bindings: clk: add G12A AO Clock and Reset Bindings")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20190321092010.14382-1-narmstrong@baylibre.com
2019-04-01 10:45:11 +02:00
Martin Blumenstingl
23e9ae2826 dt-bindings: clock: meson8b: drop the "ABP" clock definition
Commit 8e1dd17c8b ("dt-bindings: clock: meson8b: export the CPU post
dividers") added a new clock ID "CLKID_ABP" which contains a typo. This
was fixed by adding a new (typo-free) #define CLKID_APB in
commit 40d08f774c ("dt-bindings: clock: meson8b: add APB clock
definition").
Now that the new #define is used by the driver we can remove the old
one (because the old one is not used anywhere).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190319214123.27219-2-martin.blumenstingl@googlemail.com
2019-04-01 10:45:11 +02:00
Maxime Jourdan
1947890795 dt-bindings: clk: g12a-clkc: add VDEC clock IDs
Expose the three clocks related to the video decoder.

Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190319101138.27520-2-mjourdan@baylibre.com
2019-04-01 10:45:11 +02:00
Jerome Brunet
e4c1e95fac dt-bindings: clock: axg-audio: unexpose controller inputs
Remove the bindings ID of the clock input of the controller. These
clocks are purely internal to the controller, exposing them was a
mistake. Actually, these should not even be in the provider and have
IDs to begin with.

Unexpose these IDs before:
 * someone starts using them (even if there no valid reason to do so)
 * the actual clocks are removed. The fact that they exist is just the
   result of an ugly hack. This will be resolved in CCF when we can
   reference DT directly in parent table.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Maxime Jourdan <mjourdan@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190213095835.17448-1-jbrunet@baylibre.com
2019-04-01 10:45:11 +02:00
Neil Armstrong
a6256b3a92 dt-bindings: reset: meson-g12a: Add missing USB2 PHY resets
The G12A Documentation lacked these 2 reset lines, but they are present and
used for each USB 2 PHYs.

Add them to the dt-bindings for the upcoming USB support.

Fixes: dbfc54534d ("dt-bindings: reset: meson: add g12a bindings")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2019-03-25 16:22:10 +01:00
Krzysztof Kozlowski
c52c6857de clk: samsung: dt-bindings: Add ADC clock ID to Exynos5410
Add ID for TSADC clock to Exynos5410.  Choose the same value of ID as in
Exynos5420 to make it simpler/compatible in future (although clock
driver code is not shared).

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-03-22 12:41:57 +01:00
Krzysztof Kozlowski
9d8e8f045a clk: samsung: dt-bindings: Put CLK_UART3 in order
Order the CLK_UART3 by ID.  No change in functionality.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-03-22 12:41:57 +01:00
Anson Huang
d058fb60d5 dt-bindings: clock: imx7ulp: remove SNVS clock
Since i.MX7ULP B0 chip, SNVS module is moved into M4
domain, so remove it from Linux clock table.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-20 16:00:03 +08:00
Neil Armstrong
17750f5218 dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID
Add a clock ID for the reference clock feeding the USB3+PCIe Combo PHY.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20190307141455.23879-3-narmstrong@baylibre.com
2019-03-19 21:11:25 +01:00
Neil Armstrong
dc6276f576 clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id
When submitted v2 of the G12A AO-CLK IDs, the SAR_ADC_SEL ID was moved
to the internal non-exported bindings, but this clock is necessary and
mandatory for the SAR ADC bindings.

Export it back to the public bindings.

Fixes: be3d960b0a ("dt-bindings: clk: add G12A AO Clock and Reset Bindings")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20190304105358.4987-1-narmstrong@baylibre.com
2019-03-19 21:10:21 +01:00
Neil Armstrong
58b5c8acba clk: meson-g12a: add cpu clock bindings
Add Amlogic G12A Family CPU clocks bindings, only export CPU_CLK since
it should be the only ID used.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20190304131129.7762-2-narmstrong@baylibre.com
2019-03-19 21:08:03 +01:00
Anson Huang
0f8e231712 dt-bindings: firmware: imx-scu: add new resources to scu resource table
Add new resources as below according to latest system
controller firmware for new features:

	IMX_SC_R_PERF
	IMX_SC_R_OCRAM
	IMX_SC_R_DMA_5_CH0
	IMX_SC_R_DMA_5_CH1
	IMX_SC_R_DMA_5_CH2
	IMX_SC_R_DMA_5_CH3
	IMX_SC_R_ATTESTATION

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-19 16:46:37 +08:00
Anson Huang
9613163a28 dt-bindings: firmware: imx-scu: remove unused resources from scu resource table
Removes below resources which were defined during
pre-silicon phase and the real silicons do NOT have
them, they have never been used, latest system
controller firmware also removed them:

	IMX_SC_R_DC_0_CAPTURE0
	IMX_SC_R_DC_0_CAPTURE1
	IMX_SC_R_DC_0_INTEGRAL0
	IMX_SC_R_DC_0_INTEGRAL1
	IMX_SC_R_DC_0_FRAC1
	IMX_SC_R_DC_1_CAPTURE0
	IMX_SC_R_DC_1_CAPTURE1
	IMX_SC_R_DC_1_INTEGRAL0
	IMX_SC_R_DC_1_INTEGRAL1
	IMX_SC_R_DC_1_FRAC1
	IMX_SC_R_GPU_3_PID0
	IMX_SC_R_M4_0_SIM
	IMX_SC_R_M4_0_WDOG
	IMX_SC_R_M4_1_SIM
	IMX_SC_R_M4_1_WDOG

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-19 16:46:36 +08:00
Jolly Shah
31a2d5113e include: dt-binding: clock: Rename zynqmp header file
Rename file name of ZynqMP clk dt-bindings to align with
file name of reset and power dt-bindings.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-03-18 13:41:17 +01:00
Geert Uytterhoeven
3961d355df dt-bindings: power: r8a77965: Remove non-existent A3IR power domain
The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018)
removed the A3IR power domain on R-Car M3-N, as this SoC does not have
an Image Processing Unit (IMP-X5).

As of commit d8c6557bc9 ("arm64: dts: renesas: r8a77965: Remove
non-existent IPMMU-IR"), this definition is no longer used from DT, and
thus can be removed.

Fixes: a527709b78 ("soc: renesas: rcar-sysc: Add R-Car M3-N support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-18 10:33:58 +01:00
Linus Torvalds
dc2535be1f We have a fairly balanced mix of clk driver updates and clk framework
updates this time around. It's the usual pile of new drivers for new
 hardware out there and the normal small fixes and updates, but then we
 have some core framework changes too.
 
 In the core framework, we introduce support for a clk_get_optional() API
 to get clks that may not always be populated and a way to devm manage clkdev
 lookups registered by provider drivers. We also do some refactoring to simplify
 the interface between clkdev and the common clk framework so we can reuse the DT
 parsing and clk_get() path in provider drivers in the future. This work will
 continue in the next few cycles while we convert how providers specify clk
 parents.
 
 On the driver side, the biggest part of the dirstat is the Amlogic clk driver
 that got support for the G12A SoC. It dominates with almost half the overall
 diff, while the second largest part of the diff is in the i.MX clk driver
 that gained support for imx8mm SoCs. After that, we have the Actions Semiconductor
 and Qualcomm drivers rounding out the big part of the dirstat because they both
 got new hardware support for SoCs. The rest is just various updates and non-critical
 fixes for existing drivers.
 
 Core:
  - Convert a few clk bindings to JSON schema format
  - Add a {devm_}clk_get_optional() API
  - Add devm_clk_hw_register_clkdev() API to manage clkdev lookups
  - Start rewriting clk parent registration and supporting device links
    by moving around code that supports clk_get() and DT parsing of the
    'clocks' property
 
 New Drivers:
  - Add Qualcomm MSM8998 RPM managed clks
  - IPA clk support on Qualcomm RPMh clk controllers
  - Actions Semi S500 SoC clk support
  - Support for fixed rate clks populated from an MMIO register
  - Add RPC (QSPI/HyperFLASH) clocks on Renesas R-Car V3H
  - Add TMU (timer) clocks on Renesas RZ/G2E
  - Add Amlogic G12A Always-On Clock Controller
  - Add 32k clock generation for Amlogic AXG
  - Add support for the Mali GPU clocks on Amlogic Meson8
  - Add Amlogic G12A EE clock controller driver
  - Add missing CANFD clocks on Renesas RZ/G2M and RZ/G2E
  - Add i.MX8MM SoC clk driver support
 
 Removed Drivers:
  - Remove clps711x driver as the board support is gone
 
 Updates:
  - 3rd ECO fix for Mediatek MT2712 SoCs
  - Updates for Qualcomm MSM8998 GCC clks
  - Random static analysis fixes for clk drivers
  - Support for sleeping gpios in the clk-gpio type
  - Minor fixes for STM32MP1 clk driver (parents, critical flag, etc.)
  - Split LCDC into two clks on the Marvell MMP2 SoC
  - Various DT of_node refcount fixes
  - Get rid of CLK_IS_BASIC from TI code (yay!)
  - TI Autoidle clk support
  - Fix Amlogic Meson8 APB clock ID name
  - Claim input clocks through DT for Amlogic AXG and GXBB
  - Correct the DU (display unit) parent clock on Renesas RZ/G2E
  - Exynos5433 IMEM CMU crypto clk support (SlimSS)
  - Fix for the PLL-MIPI on the Allwinner A23
  - Fix Rockchip rk3328 PLL rate calculation
  - Add SET_RATE_PARENT flag on display clk of Rockhip rk3066
  - i.MX SCU clk driver clk_set_parent() and cpufreq support
 -----BEGIN PGP SIGNATURE-----
 
 iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAlyIK9URHHNib3lkQGtl
 cm5lbC5vcmcACgkQrQKIl8bklSUtIA//SRHcUJBuF7bgLs0GWDL/C0WwQf90bgLn
 83jMUX9MCIS+/RBEUi/Xf9psGVaW3YPEAiRcYUeI1YIZhCrdZHp2YGClKOpXaXth
 vgM7Je+6Say+7ru6J9eHqhbEgx2e+HqT4shxK5I5J0SqMFgdugim4pthk+Lr/WL0
 bMdNHTERZUFrIId10RxuCH7D72nhkwiRkwNDfWjASKoH3spXLKC1vl/wbS5QDE1O
 eXA9OwkonSyrBKX7zMeQiks6f7HWoJO7ei05Twv4CD9UEeS17KmB6mkbmT3GPAuq
 dWbLOnt7I80fMnthKLIR0IWtJuCvPv3jXgP+Fin+e4wutNCnuduHIVc2XeQYmDaX
 rbo/20q4DarL2AaakuowXA7UJ75zYfxPkwgpwcYZ/QW9yzT6QMfynAYekjJGTdt3
 6VootYAwYIsh1VMGZIQLs23AaNYayDy0QWx/prxnEi95lK/+zjqVySPYC/rWe7XQ
 rUrO6YY0YxRdf5uVHneIfIJGs5F/Q8DgdLXp4tf2Ud2YF1bZ0UQOUKehxwM0rxRX
 F9P6iP6mHUuUPMa9rDlwSmgQXDdqH7E5IbXdSPjEFBogBfmhJfVKAo1EyaZgUytZ
 Y42qG/P3fGGfegfWTRAoaDRJn/+HfEmtREdgQ8JO14xlZwRDb/M43IEiQP4zGwlc
 f/OuWu3O9xA=
 =D4Bv
 -----END PGP SIGNATURE-----

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk subsystem updates from Stephen Boyd:
 "We have a fairly balanced mix of clk driver updates and clk framework
  updates this time around. It's the usual pile of new drivers for new
  hardware out there and the normal small fixes and updates, but then we
  have some core framework changes too.

  In the core framework, we introduce support for a clk_get_optional()
  API to get clks that may not always be populated and a way to devm
  manage clkdev lookups registered by provider drivers. We also do some
  refactoring to simplify the interface between clkdev and the common
  clk framework so we can reuse the DT parsing and clk_get() path in
  provider drivers in the future. This work will continue in the next
  few cycles while we convert how providers specify clk parents.

  On the driver side, the biggest part of the dirstat is the Amlogic clk
  driver that got support for the G12A SoC. It dominates with almost
  half the overall diff, while the second largest part of the diff is in
  the i.MX clk driver that gained support for imx8mm SoCs. After that,
  we have the Actions Semiconductor and Qualcomm drivers rounding out
  the big part of the dirstat because they both got new hardware support
  for SoCs. The rest is just various updates and non-critical fixes for
  existing drivers.

  Core:
   - Convert a few clk bindings to JSON schema format
   - Add a {devm_}clk_get_optional() API
   - Add devm_clk_hw_register_clkdev() API to manage clkdev lookups
   - Start rewriting clk parent registration and supporting device links
     by moving around code that supports clk_get() and DT parsing of the
     'clocks' property

  New Drivers:
   - Add Qualcomm MSM8998 RPM managed clks
   - IPA clk support on Qualcomm RPMh clk controllers
   - Actions Semi S500 SoC clk support
   - Support for fixed rate clks populated from an MMIO register
   - Add RPC (QSPI/HyperFLASH) clocks on Renesas R-Car V3H
   - Add TMU (timer) clocks on Renesas RZ/G2E
   - Add Amlogic G12A Always-On Clock Controller
   - Add 32k clock generation for Amlogic AXG
   - Add support for the Mali GPU clocks on Amlogic Meson8
   - Add Amlogic G12A EE clock controller driver
   - Add missing CANFD clocks on Renesas RZ/G2M and RZ/G2E
   - Add i.MX8MM SoC clk driver support

  Removed Drivers:
   - Remove clps711x driver as the board support is gone

  Updates:
   - 3rd ECO fix for Mediatek MT2712 SoCs
   - Updates for Qualcomm MSM8998 GCC clks
   - Random static analysis fixes for clk drivers
   - Support for sleeping gpios in the clk-gpio type
   - Minor fixes for STM32MP1 clk driver (parents, critical flag, etc.)
   - Split LCDC into two clks on the Marvell MMP2 SoC
   - Various DT of_node refcount fixes
   - Get rid of CLK_IS_BASIC from TI code (yay!)
   - TI Autoidle clk support
   - Fix Amlogic Meson8 APB clock ID name
   - Claim input clocks through DT for Amlogic AXG and GXBB
   - Correct the DU (display unit) parent clock on Renesas RZ/G2E
   - Exynos5433 IMEM CMU crypto clk support (SlimSS)
   - Fix for the PLL-MIPI on the Allwinner A23
   - Fix Rockchip rk3328 PLL rate calculation
   - Add SET_RATE_PARENT flag on display clk of Rockhip rk3066
   - i.MX SCU clk driver clk_set_parent() and cpufreq support"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (150 commits)
  dt-bindings: clock: imx8mq: Fix numbering overlaps and gaps
  clk: ti: clkctrl: Fix clkdm_name regression for TI_CLK_CLKCTRL_COMPAT
  clk: fixup default index for of_clk_get_by_name()
  clk: Move of_clk_*() APIs into clk.c from clkdev.c
  clk: Inform the core about consumer devices
  clk: Introduce of_clk_get_hw_from_clkspec()
  clk: core: clarify the check for runtime PM
  clk: Combine __clk_get() and __clk_create_clk()
  clk: imx8mq: add GPIO clocks to clock tree
  clk: mediatek: correct cpu clock name for MT8173 SoC
  clk: imx: Refactor entire sccg pll clk
  clk: imx: scu: add cpu frequency scaling support
  clk: mediatek: Mark bus and DRAM related clocks as critical
  clk: mediatek: Add flags to mtk_gate
  clk: mediatek: Add MUX_FLAGS macro
  clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks
  clk: ingenic: Remove set but not used variable 'enable'
  clk: at91: programmable: remove unneeded register read
  clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel
  clk: mediatek: add MUX_GATE_FLAGS_2
  ...
2019-03-14 08:46:17 -07:00
Abel Vesa
010d5166bb dt-bindings: clock: imx8mq: Fix numbering overlaps and gaps
IMX8MQ_CLK_USB_PHY_REF changes from 163 to 153, this way removing the gap.
All the following clock ids are now decreased by 10 to keep the numbering
right. Doing this, the IMX8MQ_CLK_CSI2_CORE is not overlapped with
IMX8MQ_CLK_GPT1 anymore. IMX8MQ_CLK_GPT1_ROOT changes from 193 to 183 and
all the following ids are updated accordingly.

Reported-by: Patrick Wildt <patrick@blueri.se>
Fixes: 1cf3817b ("dt-bindings: Add binding for i.MX8MQ CCM")
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-03-12 13:40:10 -07:00
Linus Torvalds
cf0240a755 This is the bulk of pin control changes for the v5.1 kernel cycle.
No core changes.
 
 New drivers:
 
 - NXP (ex Freescale) i.MX 8QM driver.
 
 - NXP (ex Freescale) i.MX 8MM driver.
 
 - AT91 SAM9X60 subdriver.
 
 Improvements:
 
 - Support for external interrups (EINT) on Mediatek virtual GPIOs.
 
 - Make BCM2835 pin config fully generic.
 
 - Lots of Renesas SH-PFC incremental improvements.
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABAgAGBQJchil8AAoJEEEQszewGV1zTCcP/AurT3InBO4nVdN9UMuoDL7P
 gx3SALULapc4+M1NUoRw+w+z5fvjd0gGdPXZeyhX1E9kXxLmWBmBf6tl0MO2YYPC
 UWbSnBaWIOOli0f4k+GKVF8LKqD0z0e/YqX4mG7UI3OLJzcJgm7OL9uXN3Gh7tIP
 Pa6CGbv0aRDkZpWUD2ZTpSPCRYGT57roVq//d7V7s+0lveS97pQuMv43YlS5L2my
 JOOhHNG33bgi4lS/ZOP81G16oOrVaoupXuX7E+AvgG6vxr5965Fi+qoGLkxIuYOm
 jtrzuNY98eL2m9b505VYdNmD7ouBhG6CKFb4njpOvjkkqNUXOaGV53wlEuEYRUNz
 bsp0596+dlOcW7wl11r6YI4Kyn2wQJFql1AwS8A4dEtbuboGrDy16N3adr1SkIGZ
 4ESN8xydcC7CAgUGXks+AgDj9vYwOs4apylJDW5tMk4K0LIsEYsDkbNeS9hwDYIH
 ZlbQe9N2loB6qQbX3c3D3/sIhKj2VB4elONSwOW10M8OJdJwp8h44UyMZ3TIEHIT
 7Gu9pw5vobXbccKCSjqkYYflaHMmjwZUtLqDZws818sbe/xgDxONbRqloZCLV39Y
 kmwRGbbE5WtNAM0X+ABwMG3Lm77wxCFKCjJwLHH79qqt4kSBynEKXQ4D/coG/Hln
 6idanzKEPiIBJ+6QLdbQ
 =EfXK
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v5.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is a calm cycle, not much happened this time around: not even
  much incremental development. Some three new drivers, that is all.

  No core changes.

  New drivers:

   - NXP (ex Freescale) i.MX 8QM driver.

   - NXP (ex Freescale) i.MX 8MM driver.

   - AT91 SAM9X60 subdriver.

  Improvements:

   - Support for external interrups (EINT) on Mediatek virtual GPIOs.

   - Make BCM2835 pin config fully generic.

   - Lots of Renesas SH-PFC incremental improvements"

* tag 'pinctrl-v5.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (70 commits)
  pinctrl: imx: fix scu link errors
  dt-bindings: pinctrl: Document the i.MX50 IOMUXC binding
  pinctrl: qcom: spmi-gpio: Reorder debug print
  pinctrl: nomadik: fix possible object reference leak
  pinctrl: stm32: return error upon hwspinlock failure
  pinctrl: stm32: fix memory leak issue
  pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions
  pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions
  pinctrl: sh-pfc: Validate fixed-size field widths at build time
  pinctrl: sh-pfc: sh73a0: Fix fsic_spdif pin groups
  pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group
  pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group
  pinctrl: sh-pfc: emev2: Add missing pinmux functions
  pinctrl: sunxi: Support I/O bias voltage setting on A80
  pinctrl: ingenic: Add LCD pins for the JZ4725B SoC
  pinctrl: samsung: Remove legacy API for handling external wakeup interrupts mask
  pinctrl: bcm2835: Direct GPIO config changes to generic pinctrl
  pinctrl: bcm2835: declare pin config as generic
  pinctrl: qcom: qcs404: Drop unused UFS_RESET macro
  dt-bindings: add documentation for slew rate
  ...
2019-03-11 11:12:50 -07:00
Stephen Boyd
fea0b0850a Merge branches 'clk-typo', 'clk-json-schema', 'clk-mtk-2712-eco' and 'clk-rockchip' into clk-next
- Convert a few clk bindings to JSON schema format
 - 3rd ECO fix for Mediatek MT2712 SoCs

* clk-typo:
  clk: samsung: fix typo

* clk-json-schema:
  dt-bindings: clock: Convert fixed-factor-clock to json-schema
  dt-bindings: clock: Convert fixed-clock binding to json-schema

* clk-mtk-2712-eco:
  clk: mediatek: update clock driver of MT2712
  dt-bindings: clock: add clock for MT2712

* clk-rockchip:
  clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks
  clk: rockchip: fix frac settings of GPLL clock for rk3328
2019-03-08 10:34:22 -08:00
Stephen Boyd
efb1e0b071 Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk-crit' and 'clk-mtk' into clk-next
* clk-ingenic:
  clk: ingenic: Remove set but not used variable 'enable'
  clk: ingenic: Fix doc of ingenic_cgu_div_info
  clk: ingenic: Fix round_rate misbehaving with non-integer dividers
  clk: ingenic: jz4740: Fix gating of UDC clock

* clk-mtk-mux:
  clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel
  clk: mediatek: add MUX_GATE_FLAGS_2

* clk-qcom-sdm845-pcie:
  clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks

* clk-mtk-crit:
  clk: mediatek: Mark bus and DRAM related clocks as critical
  clk: mediatek: Add flags to mtk_gate
  clk: mediatek: Add MUX_FLAGS macro

* clk-mtk:
  clk: mediatek: correct cpu clock name for MT8173 SoC
2019-03-08 10:29:30 -08:00
Stephen Boyd
75f486c015 Merge branches 'clk-qcom-msm8998', 'clk-fractional-parent', 'clk-x86-mv' and 'clk-SA-fixes' into clk-next
- Updates for qcom MSM8998 GCC clks
 - qcom MSM8998 RPM managed clks
 - Random static analysis fixes for clk drivers

* clk-qcom-msm8998:
  clk: qcom: Make common clk_hw registrations
  clk: qcom: smd: Add support for MSM8998 rpm clocks
  clk: qcom: Skip halt checks on gcc_usb3_phy_pipe_clk for 8998
  clk: qcom: Add missing freq for usb30_master_clk on 8998
  clk: qcom: Add CLK_SET_RATE_PARENT for 8998 branch clocks

* clk-fractional-parent:
  clk: fractional-divider: check parent rate only if flag is set

* clk-x86-mv:
  clk: x86: Move clk-lpss.h to platform_data/x86

* clk-SA-fixes:
  clk: mediatek: fix platform_no_drv_owner.cocci warnings
  clk: tegra: dfll: Fix debugfs_simple_attr.cocci warnings
  clk: qoriq: Improve an error message
2019-03-08 10:29:15 -08:00
Stephen Boyd
461ea6ab2c Merge branches 'clk-qcom-rpmh', 'clk-gpio-sleep', 'clk-stm32mp1', 'clk-qcom-qcs404' and 'clk-actions-s500' into clk-next
- IPA clk support on Qualcomm RPMh clk controllers
 - Support sleeping gpios in clk-gpio type
 - Minor fixes for STM32MP1 clk driver (parents, critical flag, etc.)
 - Actions Semi S500 SoC clk support

* clk-qcom-rpmh:
  clk: qcom: clk-rpmh: Add IPA clock support

* clk-gpio-sleep:
  clk: clk-gpio: add support for sleeping GPIOs in gpio-gate-clk

* clk-stm32mp1:
  dt-bindings: clock: remove unused definition for stm32mp1
  clk: stm32mp1: fix bit width of hse_rtc divider
  clk: stm32mp1: remove unnecessary CLK_DIVIDER_ALLOW_ZERO flag
  clk: stm32mp1: fix HSI divider flag
  clk: stm32mp1: fix mcu divider table
  clk: stm32mp1: set ck_csi as critical clock
  clk: stm32mp1: add CLK_SET_RATE_NO_REPARENT to Kernel clocks
  clk: stm32mp1: parent clocks update

* clk-qcom-qcs404:
  clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock
  clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs
  clk: qcom: remove empty lines in clk-rcg.h

* clk-actions-s500:
  clk: actions: Add clock driver for S500 SoC
  dt-bindings: clock: Add DT bindings for Actions Semi S500 CMU
  clk: actions: Add configurable PLL delay
2019-03-08 10:27:52 -08:00
Stephen Boyd
e7faa095cb Merge branches 'clk-imx', 'clk-samsung', 'clk-ti', 'clk-uniphier-gear' and 'clk-mmp2-lcdc' into clk-next
- Split LCDC into two clks on the Marvell MMP2 SoC

* clk-imx:
  clk: imx8mq: add GPIO clocks to clock tree
  clk: imx: Refactor entire sccg pll clk
  clk: imx: scu: add cpu frequency scaling support
  clk: imx: imx8mm: Mark init function __init
  clk: imx8mq: Add the missing ARM clock
  dt-bindings: imx8mq-clock: Add the missing ARM clock
  clk: imx: imx8mq: Fix the rate propagation for arm pll
  clk: imx8mq: Add support for the CLKO1 clock
  clk: imx8mq: Fix the CLKO2 source select list
  clk: imx8mq: Add missing M4 clocks
  clk: imx: Add clock driver support for imx8mm
  dt-bindings: imx: Add clock binding doc for imx8mm
  clk: imx: Add PLLs driver for imx8mm soc
  clk: imx5: add imx5_SCC2_IPG_GATE
  clk: imx: scu: add set parent support
  clk: imx: scu: add fallback compatible string support
  clk: imx8mq: Make parent names arrays const pointers
  clk: imx: Make parents const pointer in mux wrappers
  clk: imx: Make parent_names const pointer in composite-8m

* clk-samsung:
  clk: samsung: s3c2443: Mark expected switch fall-through
  clk: samsung: exynos5: Fix kfree() of const memory on setting driver_override
  clk: samsung: exynos5: Fix possible NULL pointer exception on platform_device_alloc() failure
  clk: samsung: exynos5433: Add selected IMEM clocks
  clk: samsung: dt-bindings: Document Exynos5433 IMEM CMU
  clk: samsung: exynos5433: Fix name typo in sssx
  clk: samsung: exynos5433: Fix definition of CLK_ACLK_IMEM_{200, 266} clocks
  clk: samsung: dt-bindings: Add Exynos5433 IMEM CMU clock IDs

* clk-ti:
  clk: clk-twl6040: Fix imprecise external abort for pdmclk
  ARM: OMAP2+: hwmod: disable ick autoidling when a hwmod requires that
  clk: ti: check clock type before doing autoidle ops
  clk: ti: add a usecount for autoidle
  clk: ti: generalize the init sequence of clk_hw_omap clocks
  clk: ti: remove usage of CLK_IS_BASIC
  clk: ti: add new API for checking if a provided clock is an OMAP clock
  clk: ti: move clk_hw_omap list handling under generic part of the driver

* clk-uniphier-gear:
  clk: uniphier: Fix update register for CPU-gear

* clk-mmp2-lcdc:
  clk: mmp2: separate LCDC peripheral clk form the display clock
  dt-bindings: marvell,mmp2: Add clock id for the LCDC clock
2019-03-08 10:27:40 -08:00
Stephen Boyd
3f8e7e7247 Merge branches 'clk-optional', 'clk-devm-clkdev-register', 'clk-allwinner', 'clk-meson' and 'clk-renesas' into clk-next
- Add a {devm_}clk_get_optional() API
 - Add devm_clk_hw_register_clkdev() API to manage clkdev lookups

* clk-optional:
  clk: Add (devm_)clk_get_optional() functions
  clk: Add comment about __of_clk_get_by_name() error values

* clk-devm-clkdev-register:
  clk: clk-st: avoid clkdev lookup leak at remove
  clk: clk-max77686: Clean clkdev lookup leak and use devm
  clkdev: add managed clkdev lookup registration

* clk-allwinner:
  clk: sunxi-ng: sun8i-a23: Enable PLL-MIPI LDOs when ungating it

* clk-meson: (22 commits)
  clk: meson: meson8b: fix the naming of the APB clocks
  dt-bindings: clock: meson8b: add APB clock definition
  clk: meson: Add G12A AO Clock + Reset Controller
  dt-bindings: clk: add G12A AO Clock and Reset Bindings
  clk: meson: factorise meson64 peripheral clock controller drivers
  clk: meson: g12a: add peripheral clock controller
  dt-bindings: clk: meson: add g12a periph clock controller bindings
  clk: meson: pll: update driver for the g12a
  clk: meson: rework and clean drivers dependencies
  clk: meson: axg-audio does not require syscon
  clk: meson: use CONFIG_ARCH_MESON to enter meson clk directory
  clk: export some clk_hw function symbols for module drivers
  clk: meson: ao-clkc: claim clock controller input clocks from DT
  clk: meson: axg: claim clock controller input clock from DT
  clk: meson: gxbb: claim clock controller input clock from DT
  clk: meson: meson8b: add the GPU clock tree
  clk: meson: meson8b: use a separate clock table for Meson8
  clk: meson: axg-ao: add 32k generation subtree
  clk: meson: gxbb-ao: replace cec-32k with the dual divider
  clk: meson: add dual divider clock driver
  ...

* clk-renesas:
  clk: renesas: r8a774a1: Fix LAST_DT_CORE_CLK
  clk: renesas: r8a774c0: Fix LAST_DT_CORE_CLK
  clk: renesas: r8a774c0: Add TMU clock
  clk: renesas: r8a77980: Add RPC clocks
  clk: renesas: rcar-gen3: Add RPC clocks
  clk: renesas: rcar-gen3: Add spinlock
  clk: renesas: rcar-gen3: Factor out cpg_reg_modify()
  clk: renesas: r8a774c0: Correct parent clock of DU
  clk: renesas: r8a774a1: Add missing CANFD clock
  clk: renesas: r8a774c0: Add missing CANFD clock
2019-03-08 10:27:21 -08:00
Linus Torvalds
3601fe43e8 This is the bulk of GPIO changes for the v5.1 cycle:
Core changes:
 
 - The big change this time around is the irqchip handling in
   the qualcomm pin controllers, closely coupled with the
   gpiochip. This rework, in a classic fall-between-the-chairs
   fashion has been sidestepped for too long. The Qualcomm
   IRQchips using the SPMI and SSBI transport mechanisms have
   been rewritten to use hierarchical irqchip. This creates
   the base from which I intend to gradually pull support for
   hierarchical irqchips into the gpiolib irqchip helpers to
   cut down on duplicate code. We have too many hacks in the
   kernel because people have been working around the missing
   hierarchical irqchip for years, and once it was there,
   noone understood it for a while. We are now slowly adapting
   to using it. This is why this pull requests include changes
   to MFD, SPMI, IRQchip core and some ARM Device Trees
   pertaining to the Qualcomm chip family. Since Qualcomm have
   so many chips and such large deployments it is paramount
   that this platform gets this right, and now it (hopefully)
   does.
 
 - Core support for pull-up and pull-down configuration, also
   from the device tree. When a simple GPIO chip support a
   "off or on" pull-up or pull-down resistor, we provide a
   way to set this up using machine descriptors or device tree.
   If more elaborate control of pull up/down (such as
   resistance shunt setting) is required, drivers should be
   phased over to use pin control. We do not yet provide a
   userspace ABI for this pull up-down setting but I suspect
   the makers are going to ask for it soon enough. PCA953x
   is the first user of this new API.
 
 - The GPIO mockup driver has been revamped after some
   discussion improving the IRQ simulator in the process.
   The idea is to make it possible to use the mockup for
   both testing and virtual prototyping, e.g. when you do
   not yet have a GPIO expander to play with but really
   want to get something to develop code around before
   hardware is available. It's neat. The blackbox testing
   usecase is currently making its way into kernelci.
 
 - ACPI GPIO core preserves non direction flags when updating
   flags.
 
 - A new device core helper for devm_platform_ioremap_resource()
   is funneled through the GPIO tree with Greg's ACK.
 
 New drivers:
 
 - TQ-Systems QTMX86 GPIO controllers (using port-mapped
   I/O)
 
 - Gateworks PLD GPIO driver (vaccumed up from OpenWrt)
 
 - AMD G-Series PCH (Platform Controller Hub) GPIO driver.
 
 - Fintek F81804 & F81966 subvariants.
 
 - PCA953x now supports NXP PCAL6416.
 
 Driver improvements:
 
 - IRQ support on the Nintendo Wii (Hollywood) GPIO.
 
 - get_direction() support for the MVEBU driver.
 
 - Set the right output level on SAMA5D2.
 
 - Drop the unused irq trigger setting on the Spreadtrum
   driver.
 
 - Wakeup support for PCA953x.
 
 - A slew of cleanups in the various Intel drivers.
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABAgAGBQJcgoLEAAoJEEEQszewGV1zjBAP/3OmTFGv49PFmJwSx+PlLiYf
 V6/UPaQzq81CGSMtHxbS51TyP9Id7PCfsacbuFYutzn0D1efvl7jrkb8qJ6fVvCM
 bl/i6q8ipRTPzAf1hD3QCgCe3BXCA064/OcPrz987oIvI3bJQXsmBjBSXHWr4Cwa
 WfB5DX/afn9TK3XHhMQGfw5f0d+TtnKAs90RTTVKiz9Ow8eFYZJOhgPkvhCR3Gi9
 YJIzIAiwhHZ7/zauo4JAYFU/O/Z3YEC5zeLne2ItebzNooRkSxdz0c9Hs7HlCZmU
 930Uv9jNN89N3vPqpZzAHtPvwDOmAILMWvKy9xRSp+eoIukarRJgF7ALPk7QWxK1
 yy+tGj4dXBQ6tI8W3wUN1WgjNpii3K1HbJ+1LQVQL2/q9o+3YXXqmjdjuw7C8YYV
 5ystNrUppkgfIIciHL4lhqw3wKJJhVEAns2V245hIitoShT+RvIg8GQbGZmWlQFd
 YsHbynqHL9iwfRNv26kEqZXZOo/4D1t6Scw+OPVyba2Wyttf+qbmg+XaYMqFaxYW
 mfydvdtymeCOUIPJMzw58KGPUTXJ4UPLENyayXNUHokr1a8VO8OIthY7zwi0CpvJ
 IcsAY9zoGxvfbRV922mlIsw3oOBcM2IN2lC9sY469ZVnjBrdC3rsQpIBZr+Vzz8i
 YlUfXLSGSyuUZUz//2eG
 =VoVC
 -----END PGP SIGNATURE-----

Merge tag 'gpio-v5.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

Pull GPIO updates from Linus Walleij:
 "This is the bulk of GPIO changes for the v5.1 cycle:

  Core changes:

   - The big change this time around is the irqchip handling in the
     qualcomm pin controllers, closely coupled with the gpiochip. This
     rework, in a classic fall-between-the-chairs fashion has been
     sidestepped for too long.

     The Qualcomm IRQchips using the SPMI and SSBI transport mechanisms
     have been rewritten to use hierarchical irqchip. This creates the
     base from which I intend to gradually pull support for hierarchical
     irqchips into the gpiolib irqchip helpers to cut down on duplicate
     code.

     We have too many hacks in the kernel because people have been
     working around the missing hierarchical irqchip for years, and once
     it was there, noone understood it for a while. We are now slowly
     adapting to using it.

     This is why this pull requests include changes to MFD, SPMI,
     IRQchip core and some ARM Device Trees pertaining to the Qualcomm
     chip family. Since Qualcomm have so many chips and such large
     deployments it is paramount that this platform gets this right, and
     now it (hopefully) does.

   - Core support for pull-up and pull-down configuration, also from the
     device tree. When a simple GPIO chip supports an "off or on" pull-up
     or pull-down resistor, we provide a way to set this up using
     machine descriptors or device tree.

     If more elaborate control of pull up/down (such as resistance shunt
     setting) is required, drivers should be phased over to use pin
     control. We do not yet provide a userspace ABI for this pull
     up-down setting but I suspect the makers are going to ask for it
     soon enough. PCA953x is the first user of this new API.

   - The GPIO mockup driver has been revamped after some discussion
     improving the IRQ simulator in the process.

     The idea is to make it possible to use the mockup for both testing
     and virtual prototyping, e.g. when you do not yet have a GPIO
     expander to play with but really want to get something to develop
     code around before hardware is available. It's neat. The blackbox
     testing usecase is currently making its way into kernelci.

   - ACPI GPIO core preserves non direction flags when updating flags.

   - A new device core helper for devm_platform_ioremap_resource() is
     funneled through the GPIO tree with Greg's ACK.

  New drivers:

   - TQ-Systems QTMX86 GPIO controllers (using port-mapped I/O)

   - Gateworks PLD GPIO driver (vaccumed up from OpenWrt)

   - AMD G-Series PCH (Platform Controller Hub) GPIO driver.

   - Fintek F81804 & F81966 subvariants.

   - PCA953x now supports NXP PCAL6416.

  Driver improvements:

   - IRQ support on the Nintendo Wii (Hollywood) GPIO.

   - get_direction() support for the MVEBU driver.

   - Set the right output level on SAMA5D2.

   - Drop the unused irq trigger setting on the Spreadtrum driver.

   - Wakeup support for PCA953x.

   - A slew of cleanups in the various Intel drivers"

* tag 'gpio-v5.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (110 commits)
  gpio: gpio-omap: fix level interrupt idling
  gpio: amd-fch: Set proper output level for direction_output
  x86: apuv2: remove unused variable
  gpio: pca953x: Use PCA_LATCH_INT
  platform/x86: fix PCENGINES_APU2 Kconfig warning
  gpio: pca953x: Fix dereference of irq data in shutdown
  gpio: amd-fch: Fix type error found by sparse
  gpio: amd-fch: Drop const from resource
  gpio: mxc: add check to return defer probe if clock tree NOT ready
  gpio: ftgpio: Register per-instance irqchip
  gpio: ixp4xx: Add DT bindings
  x86: pcengines apuv2 gpio/leds/keys platform driver
  gpio: AMD G-Series PCH gpio driver
  drivers: depend on HAS_IOMEM for devm_platform_ioremap_resource()
  gpio: tqmx86: Set proper output level for direction_output
  gpio: sprd: Change to use SoC compatible string
  gpio: sprd: Use SoC compatible string instead of wildcard string
  gpio: of: Handle both enable-gpio{,s}
  gpio: of: Restrict enable-gpio quirk to regulator-gpio
  gpio: davinci: use devm_platform_ioremap_resource()
  ...
2019-03-08 10:09:53 -08:00
Linus Torvalds
cf2e8c544c - New Drivers
- Add STMPE ADC Input driver
    - Add STMicroelectronics STPMIC1 Parent driver
    - Add STMicroelectronics STPMIC1 OnKey Misc driver
    - Add STMicroelectronics STPMIC1 Watchdog driver
    - Add Cirrus Logic Lochnagar Parent driver
    - Add TQ-Systems TQMX86 Parent driver
 
  - New Device Support
    - Add support for ADC to STMPE
 
  - New (or moved) Functionality
    - Move Lightbar functionality to its own driver; cros_ec_lightbar
    - Move VBC functionality to its own driver; cros_ec_vbc
    - Move VBC functionality to its own driver; cros_ec_vbc
    - Move DebugFS functionality to its own driver; cros_ec_debugfs
    - Move SYSFS functionality to its own driver; cros_ec_sysfs
    - Add support for input voltage options; tps65218
 
  - Fix-ups
    - Use devm_* managed resources; cros_ec
    - Device Tree documentation; stmpe, aspeed-lpc, lochnagar
    - Trivial Clean-ups; stmpe
    - Rip out broken modular code; aat2870-core, adp5520, as3711,
          db8500-prcmu, htc-i2cpld, max8925-core, rc5t583, sta2x11-mfd,
 	 syscon, tps65090, tps65910, tps68470 tps80031, wm831x-spi,
 	 wm831x-i2c, wm831x-core, wm8350-i2c, wm8350-core, wm8400-core
    - Kconfig fixups; INTEL_SOC_PMIC
    - Improve error path; sm501, sec-core
    - Use struct_size() helper; sm501
    - Constify; at91-usart
    - Use pointers instead of copying data; at91-usart
    - Deliver proper return value; cros_ec_dev
    - Trivial formatting/whitespace; sec-core
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEdrbJNaO+IJqU8IdIUa+KL4f8d2EFAlyA5j4ACgkQUa+KL4f8
 d2EAyw/+N7N77ex5Ryxmyn61SWvgTL221tj+olw6RqC92Vfw6S2ZFP1CsM/E7tZb
 qCLYkkJSgBLKoOCI5OLiXsvWCPjyLU33nG/oS0SSiMJ1Fp9M0h7uRnOtOio3z31i
 w9MJAvEY3RN8I1bRGMO6aWUtT0q3AzHNtdl+7BqAkjjeXiUE0lGd5eARRS1zRWSa
 ki0OzUkJeszPk+6E6N0K+BQZxcL3cBEsR8ZAif903cMEbqsJIv4nmif4b5D63BKH
 PtOLn+6HVMG4bzqRRytVhcO/z2uj2jlLCHH9wBnyd4b7SoLFuz15yN5DhD4bKLt7
 0UMqiBlC2MeaTv3wyKjeNPQtaMY7zJNUpdFly1PHAYR4oy5kbqk2IAv30N/zRfPK
 zLmWWq7DYdazBxSSGKmpGEW63Dkr/MQY2oj4nUlcank/X0K7LvmXv7kIxp9jJhA5
 bE76f77uHneHvq5OTc5CZtaYNqZbE6tO8rqZ2QlfCqa0M8VxbcrYiym0fQFJBdsH
 eFtaTG162ssZq1npV759c4/2E3zQ3EW+rj89/AWp8ViJULQLyPY2nUYddx+w04Se
 kSdgYCvMI5byvF+Tuq/CbUWz7kyca3D+EFiYTkzIfrZr+4yiG2VO8wEO1knkEUVo
 9X/wnAD5hQJePEM8CyPZrnirndB0W6SAvSmRZlF/OAbuCBz1DkQ=
 =tUge
 -----END PGP SIGNATURE-----

Merge tag 'mfd-next-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

Pull MFD updates from Lee Jones:
 "New Drivers:
   - Add STMPE ADC Input driver
   - Add STMicroelectronics STPMIC1 Parent driver
   - Add STMicroelectronics STPMIC1 OnKey Misc driver
   - Add STMicroelectronics STPMIC1 Watchdog driver
   - Add Cirrus Logic Lochnagar Parent driver
   - Add TQ-Systems TQMX86 Parent driver

  New Device Support:
   - Add support for ADC to STMPE

  New (or moved) Functionality:
   - Move Lightbar functionality to its own driver; cros_ec_lightbar
   - Move VBC functionality to its own driver; cros_ec_vbc
   - Move VBC functionality to its own driver; cros_ec_vbc
   - Move DebugFS functionality to its own driver; cros_ec_debugfs
   - Move SYSFS functionality to its own driver; cros_ec_sysfs
   - Add support for input voltage options; tps65218

  Fixes:
   - Use devm_* managed resources; cros_ec
   - Device Tree documentation; stmpe, aspeed-lpc, lochnagar
   - Trivial Clean-ups; stmpe
   - Rip out broken modular code; aat2870-core, adp5520, as3711,
         db8500-prcmu, htc-i2cpld, max8925-core, rc5t583, sta2x11-mfd,
	 syscon, tps65090, tps65910, tps68470 tps80031, wm831x-spi,
	 wm831x-i2c, wm831x-core, wm8350-i2c, wm8350-core, wm8400-core
   - Kconfig fixups; INTEL_SOC_PMIC
   - Improve error path; sm501, sec-core
   - Use struct_size() helper; sm501
   - Constify; at91-usart
   - Use pointers instead of copying data; at91-usart
   - Deliver proper return value; cros_ec_dev
   - Trivial formatting/whitespace; sec-core"

* tag 'mfd-next-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (53 commits)
  mfd: mxs-lradc: Mark expected switch fall-through
  mfd: sec-core: Cleanup formatting to a consistent style
  mfd: tqmx86: IO controller with I2C, Wachdog and GPIO
  mfd: intel-lpss: Move linux/pm.h to the local header
  mfd: cros_ec_dev: Return number of bytes read with CROS_EC_DEV_IOCRDMEM
  mfd: tps68470: Drop unused MODULE_DEVICE_TABLE
  mfd: at91-usart: No need to copy mfd_cell in probe
  mfd: at91-usart: Constify at91_usart_spi_subdev and at91_usart_serial_subdev
  mfd: lochnagar: Add support for the Cirrus Logic Lochnagar
  mfd: lochnagar: Add initial binding documentation
  dt-bindings: mfd: aspeed-lpc: Make parameter optional
  mfd: sec-core: Return gracefully instead of BUG() if device cannot match
  mfd: sm501: Use struct_size() in devm_kzalloc()
  mfd: sm501: Fix potential NULL pointer dereference
  mfd: Kconfig: Fix I2C_DESIGNWARE_PLATFORM dependencies
  mfd: tps65218.c: Add input voltage options
  mfd: wm8400-core: Make it explicitly non-modular
  mfd: wm8350-core: Drop unused module infrastructure from non-modular code
  mfd: wm8350-i2c: Make it explicitly non-modular
  mfd: wm831x-core: Drop unused module infrastructure from non-modular code
  ...
2019-03-08 10:02:58 -08:00
Linus Torvalds
e266ca36da Staging/IIO patches for 5.1-rc1
Here is the big staging/iio driver pull request for 5.1-rc1.
 
 Lots of good IIO driver updates and cleanups in here as always.
 Combined with the removal of the xgifb driver, we have a net "loss" of
 over 9000 lines in the pull request, always a nice thing.
 
 As the outreachy application process is currently happening, there are
 loads of tiny checkpatch cleanup fixes all over the staging tree, which
 accounts for the majority of the fixups.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCXH+gLQ8cZ3JlZ0Brcm9h
 aC5jb20ACgkQMUfUDdst+ymBiQCeJpoBhG+W3r+kP8w65ZY8qU+/liIAn0Tkl4/k
 IX1dQzCsEpO1jA8AHj6n
 =7wCH
 -----END PGP SIGNATURE-----

Merge tag 'staging-5.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging

Pull staging/IIO updates from Greg KH:
 "Here is the big staging/iio driver pull request for 5.1-rc1.

  Lots of good IIO driver updates and cleanups in here as always.
  Combined with the removal of the xgifb driver, we have a net "loss" of
  over 9000 lines in the pull request, always a nice thing.

  As the outreachy application process is currently happening, there are
  loads of tiny checkpatch cleanup fixes all over the staging tree,
  which accounts for the majority of the fixups"

* tag 'staging-5.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (341 commits)
  staging: mt7621-dma: remove license boilerplate text
  staging: mt7621-dma: add SPDX GPL-2.0+ license identifier
  Staging: ks7010: Replace typecast to int
  Staging: vt6655: Align a static function declaration
  staging: speakup: fix line over 80 characters.
  staging: mt7621-eth: Remove license boilerplate text
  staging: mt7621-eth: Add SPDX license identifier
  staging: ks7010: removed custom Michael MIC implementation.
  staging: rtl8192e: Fix space and suspect issue
  Staging: vt6655: Modify comment style of SPDX License Identifier
  Staging: vt6655: Modify comment style for SPDX-License-Identifier
  Staging: vt6655: Align a function declaration
  Staging: vt6655: Alignment of function declaration
  staging: rtl8712: Fix indentation issue
  staging: wilc1000: fix incorrent type in initializer
  staging: rtl8188eu: remove unused P2P_PRIVATE_IOCTL_SET_LEN
  staging: rtl8188eu: remove unused enum P2P_PROTO_WK_ID
  staging: rtl8723bs: Remove duplicated include from drv_types.h
  Staging: vt6655: Alignment should match open parenthesis
  staging: erofs: fix mis-acted TAIL merging behavior
  ...
2019-03-06 16:29:27 -08:00
Linus Torvalds
45763bf4bc Char/Misc driver patches for 5.1-rc1
Here is the big char/misc driver patch pull request for 5.1-rc1.
 
 The largest thing by far is the new habanalabs driver for their AI
 accelerator chip.  For now it is in the drivers/misc directory but will
 probably move to a new directory soon along with other drivers of this
 type.
 
 Other than that, just the usual set of individual driver updates and
 fixes.  There's an "odd" merge in here from the DRM tree that they asked
 me to do as the MEI driver is starting to interact with the i915 driver,
 and it needed some coordination.  All of those patches have been
 properly acked by the relevant subsystem maintainers.
 
 All of these have been in linux-next with no reported issues, most for
 quite some time.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCXH+dPQ8cZ3JlZ0Brcm9h
 aC5jb20ACgkQMUfUDdst+ym1fACgvpZAxjNzoRQJ6f06tc8ujtPk9rUAnR+tCtrZ
 9e3l7H76oe33o96Qjhor
 =8A2k
 -----END PGP SIGNATURE-----

Merge tag 'char-misc-5.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Pull char/misc driver updates from Greg KH:
 "Here is the big char/misc driver patch pull request for 5.1-rc1.

  The largest thing by far is the new habanalabs driver for their AI
  accelerator chip. For now it is in the drivers/misc directory but will
  probably move to a new directory soon along with other drivers of this
  type.

  Other than that, just the usual set of individual driver updates and
  fixes. There's an "odd" merge in here from the DRM tree that they
  asked me to do as the MEI driver is starting to interact with the i915
  driver, and it needed some coordination. All of those patches have
  been properly acked by the relevant subsystem maintainers.

  All of these have been in linux-next with no reported issues, most for
  quite some time"

* tag 'char-misc-5.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (219 commits)
  habanalabs: adjust Kconfig to fix build errors
  habanalabs: use %px instead of %p in error print
  habanalabs: use do_div for 64-bit divisions
  intel_th: gth: Fix an off-by-one in output unassigning
  habanalabs: fix little-endian<->cpu conversion warnings
  habanalabs: use NULL to initialize array of pointers
  habanalabs: fix little-endian<->cpu conversion warnings
  habanalabs: soft-reset device if context-switch fails
  habanalabs: print pointer using %p
  habanalabs: fix memory leak with CBs with unaligned size
  habanalabs: return correct error code on MMU mapping failure
  habanalabs: add comments in uapi/misc/habanalabs.h
  habanalabs: extend QMAN0 job timeout
  habanalabs: set DMA0 completion to SOB 1007
  habanalabs: fix validation of WREG32 to DMA completion
  habanalabs: fix mmu cache registers init
  habanalabs: disable CPU access on timeouts
  habanalabs: add MMU DRAM default page mapping
  habanalabs: Dissociate RAZWI info from event types
  misc/habanalabs: adjust Kconfig to fix build errors
  ...
2019-03-06 14:18:59 -08:00
Linus Torvalds
384d11fa0e ARM: SoC driver updates for 5.1
As usual, the drivers/tee and drivers/reset subsystems get merged
 here, with the expected set of smaller updates and some new hardware
 support. The tee subsystem now supports device drivers to be attached
 to a tee, the first example here is a random number driver with its
 implementation in the secure world.
 
 Three new power domain drivers get added for specific chip families:
  - Broadcom BCM283x chips (used in Raspberry Pi)
  - Qualcomm Snapdragon phone chips
  - Xilinx ZynqMP FPGA SoCs
 
 One new driver is added to talk to the BPMP firmware on NVIDIA
 Tegra210
 
 Existing drivers are extended for new SoC variants from NXP,
 NVIDIA, Amlogic and Qualcomm.
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABCAAGBQJcfpKpAAoJEGCrR//JCVInMpYQANwKKWOTm5NHqtf7/ZKBzx6/
 Yk7Jj8QLGKrHScnuBZSBvTwv5Cc5O5Ye+tAuGVArOoD2ktXlLZmHZ/ZPFAudT3di
 aFYbA44RNhv+O/xOmToDCCjSHm176hwUY0Cs5bFnfx6TcMsdOYIQIG+XQKx/a9zg
 3ZBEv7wZqcBArLc0X2Z2/uiVrEIh3wWwXytvw+8TG8ifUfpbDxRUxDlj1JRDpjMu
 yX4q8JDhdQvi2FTXbXcEHTdQ6RT11svPM/YxQDxfULRK9aNKf4GZJ4QlwZy+SO7N
 cEFxDd4ML/iJ1LjalvtXGkR0xrw9/gOlO3vbB9Uw3EngBDUSQfHmqJet10a14l8q
 KcToe3teIB+Z1R+plrt+h5UDJTbVibgZXhU6wIdkDgtF6oTyg1moIbTqNKHgcA3b
 HLJv4gFejeluQzJ/3dZHBnkvJo1XFAvGFmFXle0bmJRFtDx73CKnf6MA9N82l2/x
 nTn4LTxXIJVKWTWAs1qkrFyIx1gOrpGhiHPQ2JiOPMZLstz3Sr6tiJuWOr+1Ex4/
 UlZsD/CrRb+SbPBonpkD+bvzSR+j0M72A7hGmfZcDzainciWgunyXglUlzO/MT24
 C6p4R9MZ2Fffoe8pESppabRNUItp8gNsNGI7CY1IK8pgpxLrujw8OnqykpV0VETo
 As+6dZrHfPNSuI7udJi5
 =+DOl
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC driver updates from Arnd Bergmann:
 "As usual, the drivers/tee and drivers/reset subsystems get merged
  here, with the expected set of smaller updates and some new hardware
  support. The tee subsystem now supports device drivers to be attached
  to a tee, the first example here is a random number driver with its
  implementation in the secure world.

  Three new power domain drivers get added for specific chip families:
   - Broadcom BCM283x chips (used in Raspberry Pi)
   - Qualcomm Snapdragon phone chips
   - Xilinx ZynqMP FPGA SoCs

  One new driver is added to talk to the BPMP firmware on NVIDIA
  Tegra210

  Existing drivers are extended for new SoC variants from NXP, NVIDIA,
  Amlogic and Qualcomm"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (113 commits)
  tee: optee: update optee_msg.h and optee_smc.h to dual license
  tee: add cancellation support to client interface
  dpaa2-eth: configure the cache stashing amount on a queue
  soc: fsl: dpio: configure cache stashing destination
  soc: fsl: dpio: enable frame data cache stashing per software portal
  soc: fsl: guts: make fsl_guts_get_svr() static
  hwrng: make symbol 'optee_rng_id_table' static
  tee: optee: Fix unsigned comparison with less than zero
  hwrng: Fix unsigned comparison with less than zero
  tee: fix possible error pointer ctx dereferencing
  hwrng: optee: Initialize some structs using memset instead of braces
  tee: optee: Initialize some structs using memset instead of braces
  soc: fsl: dpio: fix memory leak of a struct qbman on error exit path
  clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' static
  soc: qcom: llcc-slice: Fix typos
  qcom: soc: llcc-slice: Consolidate some code
  qcom: soc: llcc-slice: Clear the global drv_data pointer on error
  drivers: soc: xilinx: Add ZynqMP power domain driver
  firmware: xilinx: Add APIs to control node status/power
  dt-bindings: power: Add ZynqMP power domain bindings
  ...
2019-03-06 09:41:12 -08:00
Linus Torvalds
6ad63dec9c ARM: SoC device tree updates for 5.1
This is a smaller update than the past few times, but with just over
 500 non-merge changesets still dwarfes the rest of the SoC tree.
 
 Three new SoC platforms get added, each one a follow-up to an existing
 product, and added here in combination with a reference platform:
 
  - Renesas RZ/A2M (R7S9210) 32-bit Cortex-A9 Real-time imaging processor
    https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rza/rza2m.html
 
  - Renesas RZ/G2E (r8a774c0) 64-bit Cortex-A53 SoC "for
    Rich Graphics Applications".
    https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rzg/rzg2e.html
 
  - NXP i.MX8QuadXPlus 64-bit Cortex-A35 SoC
    https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-8-processors/i.mx-8x-family-arm-cortex-a35-3d-graphics-4k-video-dsp-error-correcting-code-on-ddr:i.MX8X
 
 These are actual commercial products we now support with an in-kernel
 device tree source file:
 
  - Bosch Guardian is a product made by Bosch Power
    Tools GmbH, based on the Texas Instruments AM335x chip
 
  - Winterland IceBoard is a Texas Instruments AM3874 based
    machine used in telescopes at the south pole and elsewhere, see commit
    d031773169 for some pointers:
 
  - Inspur on5263m5 is an x86 server platform with an Aspeed
    ast2500 baseboard management controller. This is for running on
    the BMC.
 
  - Zodiac Digital Tapping Unit, apparently a kind of ethernet
    switch used in airplanes.
 
  - Phicomm K3 is a WiFi router based on Broadcom bcm47094
 
  - Methode Electronics uDPU FTTdp distribution point unit
 
  - X96 Max, a generic TV box based on Amlogic G12a (S905X2)
 
  - NVIDIA Shield TV (Darcy) based on Tegra210
 
 And then there are several new SBC, evaluation, development or modular
 systems that we add:
 
  - Three new Rockchips rk3399 based boards:
     - FriendlyElec NanoPC-T4 and NanoPi M4
     - Radxa ROCK Pi 4
 
  - Five new i.MX6 family SoM modules and boards for industrial
    products:
     - Logic PD i.MX6QD SoM and evaluation baseboad
     - Y Soft IOTA Draco/Hydra/Ursa family boards based on i.MX6DL
     - Phytec phyCORE i.MX6 UltraLite SoM and evaluation module
 
  - MYIR Tech MYD-LPC4357 development based on the NXP lpc4357
    microcontroller
 
  - Chameleon96, an Intel/Altera Cyclone5 based FPGA development
    system in 96boards form factor
 
  - Arm Fixed Virtual Platforms(FVP) Base RevC, a purely
    virtual platform for corresponding to the latest "fast model"
 
  - Another Raspberry Pi variant: Model 3 A+, supported both
    in 32-bit and 64-bit mode.
 
  - Oxalis Evalkit V100 based on NXP Layerscape LS1012a,
    in 96Boards enterprise form factor
 
  - Elgin RV1108 R1 development board based on 32-bit Rockchips RV1108
 
 For already supported boards and SoCs, we often add support for new
 devices after merging the drivers. This time, the largest changes include
 updates for
 
  - STMicroelectronics stm32mp1, which was now formally
    launched last week
 
  - Qualcomm Snapdragon 845, a high-end phone and low-end laptop chip
 
  - Action Semi S700
 
  - TI AM654x, their recently merged 64-bit SoC from the OMAP family
 
  - Various Amlogic Meson SoCs
 
  - Mediatek MT2712
 
  - NVIDIA Tegra186 and Tegra210
 
  - The ancient NXP lpc32xx family
 
  - Samsung s5pv210, used in some older mobile phones
 
 Many other chips see smaller updates and bugfixes beyond that.
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABCAAGBQJcf9c1AAoJEGCrR//JCVInvl8QAIgmK09QZr3VAD5WnKSoWwiX
 GP1+qgmr/cbIF9X+Kt/0Y2E+oIi9uxu7v5iwpYf0inzV4QOKwy9LvpeInd7s07bf
 hSPMN0wZ9bV5Ylk0YtlvGvOQTqys9oweeSEkHfjQ8Jm7aFkaRXQ1dt23d8KLILoB
 8GKk9A4ncn1AB1vu6xBqeqBiaQiqhMjb9paWkmjYrjhP22hHlVyGlMd8cwfG+A5a
 5Ft4lWkzvgrXPMwZgrCGU233OV5UHrn2A8ohiIUN5J6aSWxu8eMEryU+MF0poidl
 malJ+AHl2mK83YN3wYemxy/lEJzAW4PrjCVgY2bRDqwlOnI3+d+z7rVSfuMCzSKs
 TDTbv9VqPJhsZFr/GIkvB3iwnYfvP/mXrzM7gbw7rQqthEKOy+3HtZwmHAKF4QNK
 TT4wyngC/CwiyULEwtPCjbxZ/7yal6sygllioCo+M2OHeattIQEnqi/Yvc0vx/th
 th9Pepf26jUp/ZJNlxk0XDyBMPhUf6sHUvh7a+y6l6ZxZ6avbFdGPeJrQe5HF2Sp
 KM7BH3w/CpoNRSKs37mR7JpNdYNDSonItgaIm5xVJZk+Wr/BWgtcr6BbGD/vlT7N
 kIDDinyhczhvhpTmWs6QZdZNQmf6bASzTVeFv2+ES+kXt/AKhv0O5N4Pw/oU+VBv
 pD5+7YjjA0fMKcYae3gs
 =1goV
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC device tree updates from Arnd Bergmann:
 "This is a smaller update than the past few times, but with just over
  500 non-merge changesets still dwarfes the rest of the SoC tree.

  Three new SoC platforms get added, each one a follow-up to an existing
  product, and added here in combination with a reference platform:

   - Renesas RZ/A2M (R7S9210) 32-bit Cortex-A9 Real-time imaging
     processor:

       https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rza/rza2m.html

   - Renesas RZ/G2E (r8a774c0) 64-bit Cortex-A53 SoC "for Rich Graphics
     Applications":

       https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rzg/rzg2e.html

   - NXP i.MX8QuadXPlus 64-bit Cortex-A35 SoC:

       https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-8-processors/i.mx-8x-family-arm-cortex-a35-3d-graphics-4k-video-dsp-error-correcting-code-on-ddr:i.MX8X

  These are actual commercial products we now support with an in-kernel
  device tree source file:

   - Bosch Guardian is a product made by Bosch Power Tools GmbH, based
     on the Texas Instruments AM335x chip

   - Winterland IceBoard is a Texas Instruments AM3874 based machine
     used in telescopes at the south pole and elsewhere, see commit
     d031773169 for some pointers:

   - Inspur on5263m5 is an x86 server platform with an Aspeed ast2500
     baseboard management controller. This is for running on the BMC.

   - Zodiac Digital Tapping Unit, apparently a kind of ethernet switch
     used in airplanes.

   - Phicomm K3 is a WiFi router based on Broadcom bcm47094

   - Methode Electronics uDPU FTTdp distribution point unit

   - X96 Max, a generic TV box based on Amlogic G12a (S905X2)

   - NVIDIA Shield TV (Darcy) based on Tegra210

  And then there are several new SBC, evaluation, development or modular
  systems that we add:

   - Three new Rockchips rk3399 based boards:
       - FriendlyElec NanoPC-T4 and NanoPi M4
       - Radxa ROCK Pi 4

   - Five new i.MX6 family SoM modules and boards for industrial
     products:
       - Logic PD i.MX6QD SoM and evaluation baseboad
       - Y Soft IOTA Draco/Hydra/Ursa family boards based on i.MX6DL
       - Phytec phyCORE i.MX6 UltraLite SoM and evaluation module

   - MYIR Tech MYD-LPC4357 development based on the NXP lpc4357
     microcontroller

   - Chameleon96, an Intel/Altera Cyclone5 based FPGA development system
     in 96boards form factor

   - Arm Fixed Virtual Platforms(FVP) Base RevC, a purely virtual
     platform for corresponding to the latest "fast model"

   - Another Raspberry Pi variant: Model 3 A+, supported both in 32-bit
     and 64-bit mode.

   - Oxalis Evalkit V100 based on NXP Layerscape LS1012a, in 96Boards
     enterprise form factor

   - Elgin RV1108 R1 development board based on 32-bit Rockchips RV1108

  For already supported boards and SoCs, we often add support for new
  devices after merging the drivers. This time, the largest changes
  include updates for

   - STMicroelectronics stm32mp1, which was now formally launched last
     week

   - Qualcomm Snapdragon 845, a high-end phone and low-end laptop chip

   - Action Semi S700

   - TI AM654x, their recently merged 64-bit SoC from the OMAP family

   - Various Amlogic Meson SoCs

   - Mediatek MT2712

   - NVIDIA Tegra186 and Tegra210

   - The ancient NXP lpc32xx family

   - Samsung s5pv210, used in some older mobile phones

  Many other chips see smaller updates and bugfixes beyond that"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (506 commits)
  ARM: dts: exynos: Fix max voltage for buck8 regulator on Odroid XU3/XU4
  dt-bindings: net: ti: deprecate cpsw-phy-sel bindings
  ARM: dts: am335x: switch to use phy-gmii-sel
  ARM: dts: am4372: switch to use phy-gmii-sel
  ARM: dts: dm814x: switch to use phy-gmii-sel
  ARM: dts: dra7: switch to use phy-gmii-sel
  arch: arm: dts: kirkwood-rd88f6281: Remove disabled marvell,dsa reference
  ARM: dts: exynos: Add support for secondary DAI to Odroid XU4
  ARM: dts: exynos: Add support for secondary DAI to Odroid XU3
  ARM: dts: exynos: Disable ARM PMU on Odroid XU3-lite
  ARM: dts: exynos: Add stdout path property to Arndale board
  ARM: dts: exynos: Add minimal clkout parameters to Exynos3250 PMU
  ARM: dts: exynos: Enable ADC on Odroid HC1
  arm64: dts: sprd: Remove wildcard compatible string
  arm64: dts: sprd: Add SC27XX fuel gauge device
  arm64: dts: sprd: Add SC2731 charger device
  arm64: dts: sprd: Add ADC calibration support
  arm64: dts: sprd: Remove PMIC INTC irq trigger type
  arm64: dts: rockchip: Enable tsadc device on rock960
  ARM: dts: rockchip: add chosen node on veyron devices
  ...
2019-03-06 09:36:37 -08:00
Linus Torvalds
aebbfafc74 ARM: SoC platform updates for 5.1
The APM X-Gene platform is now maintained by folks from Ampere
 computing that took over the product line a while ago, this gets
 reflected in the MAINTAINERS file.
 
 Cleanups continue on the older mach-davinci and mach-pxa platform,
 to get them to be more like the modern ones. For pxa, we
 now remove the Raumfeld platform code as it now works with
 device tree based booting.
 
 i.MX adds a couple new features for the i.MX7ULP SoC
 
 Mediatek gains support for a new SoC: MT7629 is a new wireless
 router platform, following MT7623.
 
 Aside from those, there are the usual minor cleanups and bugfixes
 across several platforms.
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABCAAGBQJcf+c8AAoJEGCrR//JCVInuUsQAK+F+7hrfkwCSLXzqVIPMYC1
 hFV11s7bgbHfzkSa6ZyFC0uuT737dZjJrOdvZOXFJ2VxDscxI62mj56jCrF8tr1x
 BQqIiDLGU55mLTkPiVtmVi8p79IXz2G/1dBeYrfyj/xec6DsjVkO1Cm2itQ3vg5Q
 ZM8DRmIxsKsUv6YSGRfwVNXso9jOh+LPxlfrGL5ijdHgzDxRr7gO+B+jxgx9Sf6s
 DNLj6M8L8DFo528eHp2pJNBL21pMywAaIrDELUJyg5P3XnDX18F8CjbSRgm7OG1+
 hkdmML9qQlpOjokPJ9eeitX2e+tvKoXLn+N9kq12Pn4fkvJpKlOVnZmU+Le/3By+
 agX7hE2A21nsZuoHQjq16QoO4X9mDee7tcDMzGwTrSq1M18m2dEJW57vivda0qKN
 wNJC3qwLmh2/wfxNpO2wS29hQni7cIrFgRvUPsB/u8KvzITbQ/PMGApNV+Kf7BiO
 mZjH8X+0IkX0veS11KLsFUCbq4ezpPCNxbul2mMIVcTIV0Oz6mQXNHAecNxCCqMk
 GAgi48+9KYNszG01Xqx++x79BFnIoUJp3+gIGIa8rTvdSSsF8DlQlSzXufD9Sb2h
 CS+M8kvgfymUrjaKZNyR5ouI1ae1Q16pbapkpS4B6ucoc4Qbqz2POiSVhex+eU/N
 IrEAFEhRg7iQ9NHUaWlx
 =vxwd
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC platform updates from Arnd Bergmann:
 "The APM X-Gene platform is now maintained by folks from Ampere
  computing that took over the product line a while ago, this gets
  reflected in the MAINTAINERS file.

  Cleanups continue on the older mach-davinci and mach-pxa platform, to
  get them to be more like the modern ones. For pxa, we now remove the
  Raumfeld platform code as it now works with device tree based booting.

  i.MX adds a couple new features for the i.MX7ULP SoC

  Mediatek gains support for a new SoC: MT7629 is a new wireless router
  platform, following MT7623.

  Aside from those, there are the usual minor cleanups and bugfixes
  across several platforms"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (49 commits)
  MAINTAINERS: Update Ampere email address
  usb: ohci-da8xx: remove unused callbacks from platform data
  ARM: davinci: da830-evm: remove legacy usb helpers
  ARM: davinci: omapl138-hawk: remove legacy usb helpers
  usb: ohci-da8xx: add vbus and overcurrent gpios
  ARM: davinci: da830-evm: use gpio lookup entries for usb gpios
  ARM: davinci: omapl138-hawk: use gpio lookup entries for usb gpios
  usb: ohci-da8xx: add a helper pointer to &pdev->dev
  usb: ohci-da8xx: add a new line after local variables
  arm64: meson: enable g12a clock controller
  MAINTAINERS: Add entry for uDPU board
  ARM: davinci: da850-evm: use GPIO hogs instead of the legacy API
  arm: mediatek: add MT7629 smp bring up code
  Revert "ARM: mediatek: add MT7623a smp bringup code"
  dt-bindings: soc: fix typo of MT8173 power dt-bindings
  ARM: meson: remove COMMON_CLK_AMLOGIC selection
  arm64: meson: remove COMMON_CLK_AMLOGIC selection
  ARM: lpc32xx: remove platform data of ARM PL111 LCD controller
  ARM: lpc32xx: remove platform data of ARM PL180 SD/MMC controller
  ARM: lpc32xx: Use kmemdup to replace duplicating its implementation
  ...
2019-03-06 09:33:05 -08:00
Linus Torvalds
d9862cfbe2 Here's the main MIPS pull request for v5.1:
- Support for the MIPSr6 MemoryMapID register & Global INValidate TLB
   (GINVT) instructions, allowing for more efficient TLB maintenance when
   running on a CPU such as the I6500 that supports these.
 
 - Enable huge page support for MIPS64r6.
 
 - Optimize post-DMA cache sync by removing that code entirely for kernel
   configurations in which we know it won't be needed.
 
 - The number of pages allocated for interrupt stacks is now calculated
   correctly, where before we would wastefully allocate too much memory
   in some configurations.
 
 - The ath79 platform migrates to devicetree.
 
 - The bcm47xx platform sees fixes for the Buffalo WHR-G54S board.
 
 - The ingenic/jz4740 platform gains support for appended devicetrees.
 
 - The cavium_octeon, lantiq, loongson32 & sgi-ip27 platforms all see
   cleanups as do various pieces of core architecture code.
 -----BEGIN PGP SIGNATURE-----
 
 iIsEABYIADMWIQRgLjeFAZEXQzy86/s+p5+stXUA3QUCXH3BQxUccGF1bC5idXJ0
 b25AbWlwcy5jb20ACgkQPqefrLV1AN1+4wD+Oh4JTfZN/NEOQMlrSkXxjEHqjX3u
 1Y6CiiPCs+q2UnYBANb+ic+ZH5MnvJxxmcvlYI2q3rIh4b8TDriip4KMUTUP
 =Sw9X
 -----END PGP SIGNATURE-----

Merge tag 'mips_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Paul Burton:

 - Support for the MIPSr6 MemoryMapID register & Global INValidate TLB
   (GINVT) instructions, allowing for more efficient TLB maintenance
   when running on a CPU such as the I6500 that supports these.

 - Enable huge page support for MIPS64r6.

 - Optimize post-DMA cache sync by removing that code entirely for
   kernel configurations in which we know it won't be needed.

 - The number of pages allocated for interrupt stacks is now calculated
   correctly, where before we would wastefully allocate too much memory
   in some configurations.

 - The ath79 platform migrates to devicetree.

 - The bcm47xx platform sees fixes for the Buffalo WHR-G54S board.

 - The ingenic/jz4740 platform gains support for appended devicetrees.

 - The cavium_octeon, lantiq, loongson32 & sgi-ip27 platforms all see
   cleanups as do various pieces of core architecture code.

* tag 'mips_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (66 commits)
  MIPS: lantiq: Remove separate GPHY Firmware loader
  MIPS: ingenic: Add support for appended devicetree
  MIPS: SGI-IP27: rework HUB interrupts
  MIPS: SGI-IP27: do boot CPU init later
  MIPS: SGI-IP27: do xtalk scanning later
  MIPS: SGI-IP27: use pr_info/pr_emerg and pr_cont to fix output
  MIPS: SGI-IP27: clean up bridge access and header files
  MIPS: SGI-IP27: get rid of volatile and hubreg_t
  MIPS: irq: Allocate accurate order pages for irq stack
  MIPS: dma-noncoherent: Remove bogus condition in dma_sync_phys()
  MIPS: eBPF: Remove REG_32BIT_ZERO_EX
  MIPS: eBPF: Always return sign extended 32b values
  MIPS: CM: Fix indentation
  MIPS: BCM47XX: Fix/improve Buffalo WHR-G54S support
  MIPS: OCTEON: program rx/tx-delay always from DT
  MIPS: OCTEON: delete board-specific link status
  MIPS: OCTEON: don't lie about interface type of CN3005 board
  MIPS: OCTEON: warn if deprecated link status is being used
  MIPS: OCTEON: add fixed-link nodes to in-kernel device tree
  MIPS: Delete unused flush_cache_sigtramp()
  ...
2019-03-05 11:28:25 -08:00
Anson Huang
0c91c11c7d clk: imx8mq: add GPIO clocks to clock tree
i.MX8MQ has clock gate for each GPIO bank, add them
into clock tree for GPIO driver to manage.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-28 10:28:28 -08:00
Seiya Wang
64f4466c88 clk: mediatek: correct cpu clock name for MT8173 SoC
Correct cpu clock name from ca57 to ca72 since MT8173 does use cortex-a72.

Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-26 10:17:40 -08:00
Edgar Bernardi Righi
0c8c53e033 dt-bindings: clock: Add DT bindings for Actions Semi S500 CMU
Add devicetree bindings for Actions Semi S500 Clock Management Unit.

Signed-off-by: Edgar Bernardi Righi <edgar.righi@lsitec.org.br>
[Mani: Documented S500 CMU compatible]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
[sboyd@kernel.org: Fix SPDX comment style in header file]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-22 00:01:08 -08:00
Gabriel Fernandez
585fc46bd4 dt-bindings: clock: remove unused definition for stm32mp1
A copy of LTDC_PX and ETHCK_K (LTDC_K and ETHMAC_K) was introduced in
stm32mp1 dt-bindings file by mistake.
These bindings are not used and shouldn't be use to be conform with
convention name of the stm32mp1 clock IP.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:16:27 -08:00
David Dai
04053f4d23 clk: qcom: clk-rpmh: Add IPA clock support
The clk-rpmh driver only supports on and off RPMh clock resources. Let's
extend the driver by adding support for clocks that are managed by a
different type of RPMh resource known as Bus Clock Manager(BCM). The BCM
is a configurable shared resource aggregator that scales performance
based on a set of frequency points. The Qualcomm IP Accelerator (IPA)
clock is an example of a resource that is managed by the BCM and this a
requirement from the IPA driver in order to scale its core clock.

Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 13:57:55 -08:00
Lubomir Rintel
ed11aff3ee dt-bindings: marvell,mmp2: Add clock id for the LCDC clock
The peripheral clock is required for access the the LCDC registers. It
is in fact separate from the "AXI clock" that is optionally used to
generate the pixel clock and as such requires a separate clock id.

Link: https://lists.freedesktop.org/archives/dri-devel/2019-January/203975.html
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 13:52:00 -08:00