Enable both USB-C/DP ports on Jetson AGX Xavier and wire up the power
supplies for the SORs that drive these outputs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Some of the PMIC regulators had names that don't match the schematics.
Rename them so that it is easier to cross-reference with the hardware
documentation.
Signed-off-by: Thierry Reding <treding@nvidia.com>
It turns out that both SORs on Tegra186 are the same, so there's no need
to distinguish between them in the compatible string.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the AVDD_IO_EDP_1V05 and enable the SOR and DPAUX hardware blocks
that are used to drive DisplayPort on Jetson Nano.
Signed-off-by: Thierry Reding <treding@nvidia.com>
This clock was not previously used because it is a fixed clock. However,
adding it here allows operating systems to deal with SOR0 the same way
as SOR1.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Although Tegra194 has support for CLKREQ sideband signal and P2972
has routing of the same till the slot, it is the case most of the time
that the connected device doesn't have CLKREQ support. Hence, it makes
sense to assume that there is no CLKREQ support by default and it can
be enabled on need basis when a card with CLKREQ support is connected.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This enables the use of the USB ports found on the Jetson TX2 for input
or external storage, for example.
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enabling the SMMU for XUSB host allows buffers to be mapped through the
ARM SMMU, which helps protecting the system from rogue memory accesses
by the XUSB host.
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The XUSB pad controller is a prerequisite for enabling XUSB support.
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Tegra194 EQOS controller is used as primary Ethernet interface.
Set the ethernet0 alias to reflect that.
Generic bootloader code can use this to find the primary Ethernet device
and set the MAC address, for example.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The EQOS Ethernet controller found on Tegra194 is compatible with its
predecessor or Tegra186. However, it is an established practice to add
a compatible string for the most recent generation of the SoC as well,
just in case some incompatibilities or bugs are later discovered.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The SOR1 hardware block's registers start at physical address 0x15b40000
as correctly specified by the unit-address, but the reg property lists a
wrong value, likely because it was copy-and-pasted from SOR0 but not
correctly updated.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The ACONNECT complex starts at physical address 0x2900000, so give it a
unit-address to comply with standard naming practices checked for by the
device tree compiler.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The control back-bone (CBB) starts at physical address 0, so give it a
unit-address to comply with standard naming practices checked for by the
device tree compiler.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra194 has four CPU clusters, each with their own cache hierarchy.
This patch creates the CPU map for these clusters and adds the second-
and third-level caches and associates them with the CPUs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Commit 4fdbfd60a3a2 ("arm64: tegra: Add PCIe slot supply information
in p2972-0000 platform") added regulators for the PCIe slot on the
Jetson Xavier platform. One of these regulators has an active-low enable
and this commit incorrectly added an active-low specifier for the GPIO
which causes the following warning to occur on boot ...
WARNING KERN regulator@3 GPIO handle specifies active low - ignored
The fixed-regulator binding does not use the active-low flag from the
gpio specifier and purely relies of the presence of the
'enable-active-high' property to determine if it is active high or low
(if this property is omitted). Fix this warning by setting the GPIO
to active-high in the GPIO specifier. Finally, remove the
'enable-active-low' as this is not a valid property.
Fixes: 4fdbfd60a3a2 ("arm64: tegra: Add PCIe slot supply information in p2972-0000 platform")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Commit 3499359418 ("arm64: tegra: Enable HDMI on Jetson TX1")
added a regulator for HDMI on the Jetson TX1 platform. This regulator
has an active high enable, but the GPIO specifier for enabling the
regulator incorrectly defines it as active-low. This causes the
following warning to occur on boot ...
WARNING KERN regulator@10 GPIO handle specifies active low - ignored
The fixed-regulator binding does not use the active-low flag from the
gpio specifier and purely relies of the presence of the
'enable-active-high' property to determine if it is active high or low
(if this property is omitted). Fix this warning by setting the GPIO
to active-high in the GPIO specifier which aligns with the presense of
the 'enable-active-high' property.
Fixes: 3499359418 ("arm64: tegra: Enable HDMI on Jetson TX1")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the watchdog node to the RTD129x Device Tree.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
[AF: Moved from RTD1295 to new RTD129x]
Signed-off-by: Andreas Färber <afaerber@suse.de>
Move the SPDX-License-Identifier to the top line and update to SPDX 2.0.
While at it, switch from GPLv2+/MIT to GPLv2+/BSD2c before adding more.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Single patch to add support for Mali GPU on all versions of Juno.
Though it's disabled by default, it is very useful to test panfrost
drivers.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAl22ZX8ACgkQAEG6vDF+
4piRLQ//cZ6Gq/ZoE7ebmyQxooY0tnmfAyq6cZgGqR6DZUKvZLnShSAnUt/ojMWO
P8Ske10LkRU4yRjjkUhjELho5vMvz2TVTlZ5xX95Yto9+IbAIfox9XnwCp0amznx
B4VgksPf74SOKPKACaKX5xMZHURvOdWd0k/rV7XpS4WLnmRLkYC5XPvj/dU1Ycp1
4fV55NU5DQ0kCqkY9eRJn4RPHLlEloakvmvNgYblYPD3jC4DuGt+y80PURGuN7b0
+fWNQpRVMRZRm7nocvpj64PMWJispRrFboJxv+Gu+IH3R/NBn7uZL9pGRUCP3ibh
LKaQXsCz3rq4gq9FqtDaykMco82x1U8DPjfjyqukk0eYn1h1Yq60iJeAacgieAiM
xPK1AZGmUiPSa4IXGnHmYnEvyukZxPQr6ZPmw4n6Fkx8Z1ycPkuehkZ7RQncIpPS
VhBl1voS1l89EWDcm+vrJWr/RhHGQ2b3NicsOLwtmdtQcJYbakgJw1/QlFkw+FfP
GpZJU2Yww04ErBuF+jiMOfaYGKV62qZj0CTuKIUdbEeKLMJpuANE/mZopCDLYURY
Hz5QPmpm6VhLLHPZa3zzOOShlcOLHqpY8QssdMKjUBHu//UgrtlJJNZAgiodqAgo
TIZK0yttqC4O1yq96Z3gY0y3COapLQsBiJSgtcjn7S8IZ7zci10=
=W+dh
-----END PGP SIGNATURE-----
Merge tag 'juno-update-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt
ARMv8 Juno update for v5.5
Single patch to add support for Mali GPU on all versions of Juno.
Though it's disabled by default, it is very useful to test panfrost
drivers.
* tag 'juno-update-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: add GPU subsystem
Link: https://lore.kernel.org/r/20191028040022.GC20568@e107533-lin.cambridge.arm.com
Signed-off-by: Olof Johansson <olof@lixom.net>
i.MX8MN LPDDR4 EVK board shares most of the device as DDR4 EVK board,
the ONLY difference are the DDR type and PMIC, add support for it
and make it default i.MX8MN EVK board as usual.
The PMIC driver is NOT ready, so cpu-freq needs to be disabled as
it depends on regulator provided by PMIC.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
i.MX8MN has different EVK boards to support different DDR types,
the ONLY differences are DDR chips and PMIC, so most of the devices
can be shared between these EVK boards, create a EVK dtsi file for
common use.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
usdhc's clock rate is different according to different devices
connected, so clock rate assignment should be placed in board
DT according to different devices connected on each usdhc port.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
usdhc's clock rate is different according to different devices
connected, so clock rate assignment should be placed in board
DT according to different devices connected on each usdhc port.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
usdhc's clock rate is different according to different devices
connected, so clock rate assignment should be placed in board
DT according to different devices connected on each usdhc port.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
usdhc's clock rate is different according to different devices
connected, so clock rate assignment should be placed in board
DT according to different devices connected on each usdhc port.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add initial version of device tree for S32V234-EVB, including nodes for the
4 Cortex-A53 cores, AIPS bus with UART modules, ARM architected timer and
Generic Interrupt Controller (GIC).
Keep SoC level separate from board level to let future boards with this SoC
share common properties, while the dts files will keep board-dependent
properties.
Signed-off-by: Stoica Cosmin-Stefan <cosmin.stoica@nxp.com>
Signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com>
Signed-off-by: Dan Nica <dan.nica@nxp.com>
Signed-off-by: Larisa Grigore <Larisa.Grigore@nxp.com>
Signed-off-by: Phu Luu An <phu.luuan@nxp.com>
Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Assign clocks and clock-rates for audio plls, that audio
drivers can utilize them.
Add dai-tdm-slot-num and dai-tdm-slot-width for sound-wm8524,
that sai driver can generate correct bit clock.
Fixes: 13f3b9fdef ("arm64: dts: imx8mm-evk: Enable audio codec wm8524")
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Regulator-vsd-3v3 is supplied via GEN_3V3 rail which is an output of
an "always on" load switch supplied by 3V3_MAIN. GEN_3V3 is also used
as vin-supply by a number of peripherals, so adding it also allows us
to follow the schematic more closely.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org,
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Update the property #clock-cells = <1> to #clock-cells = <0> of the
dpclk, since the Display output pixel clock driver provides single
clock output.
Signed-off-by: Wen He <wen.he_1@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
SDMA in i.MX8MN should use same configuration as i.MX8MQ
So need to change compatible string to be "fsl,imx8mq-sdma".
Fixes: 6c3debcbae ("arm64: dts: freescale: Add i.MX8MN dtsi support")
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
SDMA in i.MX8MM should use same configuration as i.MX8MQ
So need to change compatible string to be "fsl,imx8mq-sdma".
Fixes: a05ea40eb3 ("arm64: dts: imx: Add i.mx8mm dtsi support")
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.
This patch add basic core dtsi file for it.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Link: https://lore.kernel.org/r/20191021084616.28431-1-andy.yan@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This is unused on cheza. Delete the node to get ride of the reserved-
memory section, and to avoid the driver from attempting to load a zap
shader that doesn't exist every time it powers up the GPU.
This also avoids a massive amount of dmesg spam about missing zap fw:
msm ae00000.mdss: [drm:adreno_request_fw] *ERROR* failed to load
qcom/a630_zap.mdt: -2
adreno 5000000.gpu: [drm:adreno_zap_shader_load] *ERROR* Unable to
load a630_zap.mdt
Signed-off-by: Rob Clark <robdclark@chromium.org>
Cc: Douglas Anderson <dianders@chromium.org>
Fixes: 3fdeaee951 ("arm64: dts: sdm845: Add zap shader region for GPU")
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Andy Gross <agross@kernel.org>
msm8916 uses sensors 0, 1, 2, 4 and 5. Sensor 3 is NOT used. Fixup the
device tree so that the correct sensor ID is used and as a result we can
actually check the temperature for the cpu2_3 sensor.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Andy Gross <agross@kernel.org>
Register upper-lower interrupts for each of the two tsens controllers.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Andy Gross <agross@kernel.org>
Register upper-lower interrupts for each of the two tsens controllers.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
Register upper-lower interrupts for each of the two tsens controllers.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
Register upper-lower interrupt for the tsens controller.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
This patch adds the GXL crypto hardware node for all GXL SoCs.
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
hi6220 has a Mali450 MP4 so lets add it into the DT.
Cc: Wei Xu <xuwei5@hisilicon.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
A slightly larger set of fixes have accrued in the last two weeks.
Mostly a collection of the usual smaller fixes:
- Marvell Armada: USB phy setup issues on Turris Mox
- Broadcom: GPIO/pinmux DT mapping corrections for Stingray, MMC bus
width fix for RPi Zero W, GPIO LED removal for RPI CM3. Also some
maintainer updates.
- OMAP: Fixlets for display config, interrupt settings for wifi, some
clock/PM pieces. Also IOMMU regression fix and a ti-sysc no-watchdog
regression fix.
- i.MX: A few fixes around PM/settings, some devicetree fixlets and
catching up with config option changes in DRM
- Rockchip: RockRro64 misc DT fixups, Hugsun X99 USB-C, Kevin display
panel settings
... and some smaller fixes for Davinci (backlight, McBSP DMA), Allwinner
(phy regulators, PMU removal on A64, etc).
-----BEGIN PGP SIGNATURE-----
iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAl2zFiIPHG9sb2ZAbGl4
b20ubmV0AAoJEIwa5zzehBx3HtgQAI+fVql3qk2qnDhP2CJihxPWTl5tyM26hvRH
dSRmpAIEXyPyjEOkqfaYqNUgHQVR+GlT5JxL5M//nrVZDngpKmIZs3pJlT4FF75o
VyC/lufeKqPaAfEaewkw8ZasN9sOtOW4ZSNB9sWsqQ5wWaz40py0E+XzIb8njz3r
EvN8JvSpCRteyIpqXCwskwLLjjCyWKFrh1DglVdQ5UObRdqboZulwl3ll9koDMJO
GT6FFHr/oc8CHFntPcP2dCgtMLlxtK7AH6scy8RaHX8uysJBrpKH5cAvszi2n4je
vIS+h8/U/NhFt1M6QjvtC4+DqK5medWbw5Opd14PHeuNwSWjyrhIkNuoSLb2jXBG
QvfEQ0daXFAJLzzW4jl+EIHUJ0Ad/64NV3jQ2we4ah4d/eApGizdrKSxb+tRF7ma
s6ju0v1DNZWpzqVsoOprC/00h3Fm5OI5CtvzCO/Oi1jYSP+OVnGCmveleXxz+8Tm
z/MPml18ykeSOgwCmh8yvg0oVu7AGjqQ7JlFqErwdiSmW6dgLERcQANxQk1Bme7B
0aE94L/9SvNPElnCvmuQy1NYIMisE9r4+/7s46rQIlKajdke3GFZvTGQzynrVDAQ
C3EzBnflIjqjJsJ8TEslHld69ZzqcPzkxE1jKkNLHLh6Z13o3MXIhE4/93VDtlwG
6CbfV6T0
=Jy/6
-----END PGP SIGNATURE-----
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC fixes from Olof Johansson:
"A slightly larger set of fixes have accrued in the last two weeks.
Mostly a collection of the usual smaller fixes:
- Marvell Armada: USB phy setup issues on Turris Mox
- Broadcom: GPIO/pinmux DT mapping corrections for Stingray, MMC bus
width fix for RPi Zero W, GPIO LED removal for RPI CM3. Also some
maintainer updates.
- OMAP: Fixlets for display config, interrupt settings for wifi, some
clock/PM pieces. Also IOMMU regression fix and a ti-sysc
no-watchdog regression fix.
- i.MX: A few fixes around PM/settings, some devicetree fixlets and
catching up with config option changes in DRM
- Rockchip: RockRro64 misc DT fixups, Hugsun X99 USB-C, Kevin display
panel settings
... and some smaller fixes for Davinci (backlight, McBSP DMA),
Allwinner (phy regulators, PMU removal on A64, etc)"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (42 commits)
ARM: dts: stm32: relax qspi pins slew-rate for stm32mp157
MAINTAINERS: Update the Spreadtrum SoC maintainer
MAINTAINERS: Remove Gregory and Brian for ARCH_BRCMSTB
ARM: dts: bcm2837-rpi-cm3: Avoid leds-gpio probing issue
bus: ti-sysc: Fix watchdog quirk handling
ARM: OMAP2+: Add pdata for OMAP3 ISP IOMMU
ARM: OMAP2+: Plug in device_enable/idle ops for IOMMUs
ARM: davinci_all_defconfig: enable GPIO backlight
ARM: davinci: dm365: Fix McBSP dma_slave_map entry
ARM: dts: bcm2835-rpi-zero-w: Fix bus-width of sdhci
ARM: imx_v6_v7_defconfig: Enable CONFIG_DRM_MSM
arm64: dts: imx8mn: Use correct clock for usdhc's ipg clk
arm64: dts: imx8mm: Use correct clock for usdhc's ipg clk
arm64: dts: imx8mq: Use correct clock for usdhc's ipg clk
ARM: dts: imx7s: Correct GPT's ipg clock source
ARM: dts: vf610-zii-scu4-aib: Specify 'i2c-mux-idle-disconnect'
ARM: dts: imx6q-logicpd: Re-Enable SNVS power key
arm64: dts: lx2160a: Correct CPU core idle state name
mailmap: Add Simon Arlott (replacement for expired email address)
arm64: dts: rockchip: Fix override mode for rk3399-kevin panel
...
The I2C multiplexer used on ls1028aqds is PCA9547, not PCA9847.
If the wrong compatible was used, this chip will not be able to
be probed correctly and hence fail to work.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Fixes: 8897f3255c ("arm64: dts: Add support for NXP LS1028A SoC")
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On i.MX8MQ EVK board, VDD_ARM is from a DC-DC converter which
is always ON, the GPIO1_IO13 is ONLY to switch VDD_ARM's voltage
between 0.9V and 1V for CPU DVFS, so VDD_ARM's GPIO regulator
should be always ON to avoid below confusion after kernel boot
up:
imx8mqevk login:
[ 31.776619] vdd_arm: disabling
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add scu key node for i.MX8QXP, disabled by default as it
depends on board design.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
for 5.5, please pull the following:
- Stefan paves the way for supporting the Raspberry Pi 4 and gets rid of
a bunch of dtc checker warnings by removing incorrect
nodes/properties, moving BCM2835/6/7 specific nodes into the
appropriate DTS, converts Raspberry Pi boards to JSON schema, and
finally adds minimal Raspberry Pi 4 model B support
- Dan adds support for the Luxul XWC-2000 router based on the BCM47094 SoC
- Chris adds a proper label to the Hurricane 2 watchdog controller node
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAl2wpM0ACgkQh9CWnEQH
BwQf0RAAhvYUYVmhCWjNSW5sien2GrPjayDan8D0MD66VvWqeF56UzENC4ab2Yax
fFNY8+CBKAVvIs4k2rIl50epb7eUEzDDw32g8rFJTqnLw0ZBTMxpNs1H2OjgEEz5
ewP9wkyxsgMhS43DdD/4xZvjonce4xEyloSG8S/o3uVceokEWX72Hcqo9lol5uB2
sFv8aBsavYWopCo0iG9AU3ZifHpz3LWTwS4uFyxJTj4T9kVd+W3WAqDgZKkGHd1U
YqCytE8Zqo56QsDExWuN0QzakXTz59xEi2jIkALZuQOhJH7yGjiGZZpaooAWzrVU
ks1eCCm4s1vrbo4/DL72tJ7yhy7nWTIvdZTLv4nWcLWYm76U6cQ++MwcGA66CMgr
AWAIbu/eFCcZxdNsusrx2CwFsvfpRsn3qEFbD9HkUqMIgrv6MNQ4FbrTOLqQOg64
1mWhuY8htz9avmav7E2XFMnTIUfFaYqvRM3OoS3h3Zh0u3TK68Q1qFA91guEu6ko
y2TRiFUaUPwcv4l/kRaWZ1cNsnX2FJggJ5hmsIdvRx7/9LhukGPb0BJFmuUDFm1X
WTTPRB0WX06NzxkH0YQZCnz/5YvKaSGmCxQ7mcAw0KZ66rcVNJiPk5EdukkU7g60
ZOtVIxJXja7JEJ3T+7frei10LhayCL2/0e4eQFMFgdFzm2KtIHQ=
=CWof
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-5.5/devicetree' of https://github.com/Broadcom/stblinux into arm/dt
This pull request contains Broadcom ARM-based SoCs Device Tree updates
for 5.5, please pull the following:
- Stefan paves the way for supporting the Raspberry Pi 4 and gets rid of
a bunch of dtc checker warnings by removing incorrect
nodes/properties, moving BCM2835/6/7 specific nodes into the
appropriate DTS, converts Raspberry Pi boards to JSON schema, and
finally adds minimal Raspberry Pi 4 model B support
- Dan adds support for the Luxul XWC-2000 router based on the BCM47094 SoC
- Chris adds a proper label to the Hurricane 2 watchdog controller node
* tag 'arm-soc/for-5.5/devicetree' of https://github.com/Broadcom/stblinux:
ARM: dts: bcm: HR2: add label to sp805 watchdog
ARM: dts: BCM5301X: Add DT for Luxul XWC-2000
arm64: dts: broadcom: Add reference to RPi 4 B
ARM: dts: Add minimal Raspberry Pi 4 support
dt-bindings: arm: bcm2835: Add Raspberry Pi 4 to DT schema
dt-bindings: arm: Convert BCM2835 board/soc bindings to json-schema
ARM: dts: bcm283x: Move BCM2835/6/7 specific to bcm2835-common.dtsi
ARM: dts: bcm283x: Remove brcm,bcm2835-pl011 compatible
ARM: dts: bcm283x: Remove simple-bus from fixed clocks
Link: https://lore.kernel.org/r/20191023212814.30622-1-f.fainelli@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
- A fixup for the A10 CSI DT binding merged during the 5.4-rc1 window
- A fix for a dt-binding error
- Addition of phy regulator delays
- The PMU on the A64 was found to be non-functional, so we've dropped it for now
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXa/4RQAKCRDj7w1vZxhR
xU3XAQDYuCixpCCftKIhjcz+oultXqAJysDEE44dATwT1YfINgD/eBSwBw1l/Ni7
yOumUvRZ1fJC3NO8e7vh9cYN9yy5tgw=
=3/ru
-----END PGP SIGNATURE-----
Merge tag 'sunxi-fixes-for-5.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/fixes
A number of fixes for this release, but mostly:
- A fixup for the A10 CSI DT binding merged during the 5.4-rc1 window
- A fix for a dt-binding error
- Addition of phy regulator delays
- The PMU on the A64 was found to be non-functional, so we've dropped it for now
* tag 'sunxi-fixes-for-5.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: dts: sun7i: Drop the module clock from the device tree
dt-bindings: media: sun4i-csi: Drop the module clock
media: dt-bindings: Fix building error for dt_binding_check
arm64: dts: allwinner: a64: sopine-baseboard: Add PHY regulator delay
arm64: dts: allwinner: a64: Drop PMU node
arm64: dts: allwinner: a64: pine64-plus: Add PHY regulator delay
Link: https://lore.kernel.org/r/80085a57-c40f-4bed-a9c3-19858d87564e.lettre@localhost
Signed-off-by: Olof Johansson <olof@lixom.net>
Add support for zynqmp nvmem firmware driver.
Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
[m.tretter@pengutronix.de: move to subnode of firmware]
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
This will simplify dt overlay structure for the whole PL.
Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Add support for zynqmp fpga manager.
Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
[m.tretter@pengutronix.de: moved to subnode of firmware]
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Add firmware DT node in ZynqMP device tree. This node
uses bindings as per new firmware interface driver.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Most of the basic infrastructure is completed for the ARM64 S900 SoC.
It can now boot a distro from eMMC/uSD with mainline kernel. Below are
the changes for this cycle (only S900):
- Added MMC controller support for S900 SoC. There are 4 controllers in
this SoC, each capable of accessing MMC cards as well as SDIO.
- Added onboard eMMC and uSD support for 96Boards Bubblegum96 board based
on S900. Since the MMC driver is not capable of supporting SDIO currently,
it is not enabled for now. And with the absence of PMIC support, fixed
regulators are used to model the power supply.
-----BEGIN PGP SIGNATURE-----
iQEzBAABCgAdFiEEZ6VDKoFIy9ikWCeXVZ8R5v6RzvUFAl2vFLgACgkQVZ8R5v6R
zvWvLAf+PU1sBy9Z97OiFKOhUooDXX8g1dKnQU7KbYKcGlbUSohxyrByblXBzxon
2b85Q8xE63eelDpRq5tCtQk6mry2q48FNltQxCj8meTipF9l+vsDSVijOPc+llCA
b8GE+xwl6FEP7mLcuJQmUmrYspSeeAi+bGWakj/8yp1wwwX+M89NvD7odBdNFpq9
+hEkgyxC4wtKhz2142ZaxlFleTAorsnrgSicOm4VtHZwbWmjgoYH0X4D9nSyWbcT
5nJZ6R6igi+BwZ683Lq87Z7NC4XebXuYmK4xYvqDPAzBwg76Jj/fgxOZsWoZMoON
+vO0tw6/EwGg1pKRWu259t0ytTwzEQ==
=f4lh
-----END PGP SIGNATURE-----
Merge tag 'actions-arm64-dt-for-v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-actions into arm/dt
Actions Semi ARM64 changes for v5.5:
Most of the basic infrastructure is completed for the ARM64 S900 SoC.
It can now boot a distro from eMMC/uSD with mainline kernel. Below are
the changes for this cycle (only S900):
- Added MMC controller support for S900 SoC. There are 4 controllers in
this SoC, each capable of accessing MMC cards as well as SDIO.
- Added onboard eMMC and uSD support for 96Boards Bubblegum96 board based
on S900. Since the MMC driver is not capable of supporting SDIO currently,
it is not enabled for now. And with the absence of PMIC support, fixed
regulators are used to model the power supply.
* tag 'actions-arm64-dt-for-v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-actions:
arm64: dts: actions: Add uSD and eMMC support for Bubblegum96
arm64: dts: actions: Add MMC controller support for S900
Link: https://lore.kernel.org/r/20191022145012.GB3601@Mani-XPS-13-9360
Signed-off-by: Olof Johansson <olof@lixom.net>
Add uSD and eMMC support for Bubblegum96 board based on Actions Semi
S900 SoC. SD0 is connected to uSD slot and SD2 is connected to eMMC.
Since there is no PMIC support added yet, fixed regulator has been
used as a regulator node.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Add MMC controller support for Actions Semi S900 SoC. There are 4 MMC
controllers in this SoC which can be used for accessing SD/MMC/SDIO cards.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Add service layer, fpga manager and fpga region to the device tree
on Intel Agilex platform.
Signed-off-by: Richard Gong <richard.gong@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Enable USB on the Agilex devkit. Also the Agilex devkit will use the
same daughter card that is used on Stratix10, thus it map the same
LEDs and GPIOs.
pushbutton PB_SW0 = gpio1.io4
pushbutton PB_SW1 = gpio1.io5
LED HPS_LED0 = gpio1.io20
LED HPS_LED1 = gpio1.io19
LED HPS_LED2 = gpio1.io21
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
This patch updates the reg addresses for QSPI boot and QSPI rootfs in
the device tree for Stratix10
Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
This patch adds QSPI flash interface in device tree for Intel Agilex
Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
1. Fix boot of Exynos7 due to wrong address/size of memory node,
2. Move GPU under /soc node,
3. Minor of DT bindings.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAl2t7H0QHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD17T9EACHCmKr7tFKZFbtJbAkFJcFHypIf38CmQ4S
gUUsFLCbod3WcS73UQjj/73iBjlM+tdgxWSaHbUqW87Z4oqIze9/7f/REAJnFVtg
8VpgJ/hksauIw9IhiZKbrgOTqVL/QaoLfbWObkOwhF5dZi2X0RkcVp7GfJQqGoBL
JJ+o6smzZ7adJ8JCx1kRFzVseu5t+ZPDMr8nwRzl/vVXUOqbcJ0ijW1Jj6UFubyY
/zZdRg6uaOWDmARd6nXs/j3qI8TpFGkyktgJdB209wTdb+2XOjQSJsDL9/XyhUwW
rW161QGD/2STjpMlC0lly5n8OHXaicrX9xGEC6zUVPbJ5EvnHUGLn7NK2yzUfomf
fM8ZpSMy0KfqdJxJDMEsIbWwSCsi8PYG+islDMvLYp7vguNBp6e5QHawDF8ZQ2WR
TtXV2pCsc0EivHuVGKKxVsMWGrrsxn9yjsmYgDEz0Tw+0kF3wGxVq421WyK2yArG
x9kj2emj0xDIOBxjGK8gdIr9Djg2//PanJ9WOYB93Tpk94ok9PtlybwFFq4Xq+qE
b4cMl1gOgl92dfYVq8x8LFzoytnq4KNPQv6XahtBik6o9emCPOZnCNwGShmv+E+B
6FbsJ0Y+oiwsHFdBHRUi6YPRlXoANYbZOgjwYAuWRGr01fDOyeg5Qh+L0Sgxnqfl
M5ZEHIJFAQ==
=tNpa
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt64-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Samsung DTS ARM64 changes for v5.5
1. Fix boot of Exynos7 due to wrong address/size of memory node,
2. Move GPU under /soc node,
3. Minor of DT bindings.
* tag 'samsung-dt64-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Rename Multi Core Timer node to "timer" on Exynos5433
arm64: dts: exynos: Split phandle in dmas property on Exynos5433
arm64: dts: exynos: Swap clock order of sysmmu on Exynos5433
arm64: dts: exynos: Revert "Remove unneeded address space mapping for soc node"
arm64: dts: exynos: Move GPU under /soc node for Exynos7
arm64: dts: exynos: Move GPU under /soc node for Exynos5433
Link: https://lore.kernel.org/r/20191021180453.29455-5-krzk@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
power-tree improvements ofr the roc-rk3399-pc, after a long wait
also support for the CR50 TPM device found on some RK3399-Gru devices,
some audio and gmac improvements for NanoPi4 and Rockpro64 as well
as marking the redundant RK_FUNC_x -> x mapping as deprecated and
fixing a missing #msi-cells on rk3399.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAl2tn3IQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgRQcB/4zxlsdUJbwmocLmZadCfBYII1QKdeh2kcr
u4D1T3KuxFjLPCjDcIdZ94+i8iruvXDjPi/PYGBQc63RQmgTud1woEmL5NxBsNOe
TJm9VOHKbkIYxnwSfrkBNTgtmKvxl6H0VWXpUA85f01s7HDAPnk+/8p37Vm22mIa
+MJy6dFHN2/jM6PC9E0rMmS4GEn90b7US0SRHHu2ENtZTH9qKWPW5+9RUqkgQsnl
qvnopEervmbQ0Di50L1KTaeEnzzCgbclc95rGMWmsUwAXe6gS9UmKuVlSogHCSP3
u4h6gsCPW4IwV4lkYVVubDn3eB0r0T8FUSdNIGUqZ0KYPYgPClun
=BXS2
-----END PGP SIGNATURE-----
Merge tag 'v5.5-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
A lot of improvements for the (till now) somewhat dormant px30 soc,
power-tree improvements ofr the roc-rk3399-pc, after a long wait
also support for the CR50 TPM device found on some RK3399-Gru devices,
some audio and gmac improvements for NanoPi4 and Rockpro64 as well
as marking the redundant RK_FUNC_x -> x mapping as deprecated and
fixing a missing #msi-cells on rk3399.
* tag 'v5.5-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
include: dt-bindings: rockchip: mark RK_FUNC defines as deprecated
arm64: dts: rockchip: restyle rockchip,pins on rk3399-rock-pi-4
arm64: dts: rockchip: Update nanopi4 phy reset properties
arm64: dts: rockchip: Enable nanopi4 HDMI audio
arm64: dts: rockchip: add cr50 tpm to rk3399-gru scarlet and bob
arm64: dts: rockchip: add analog audio nodes on rk3399-rockpro64
arm64: dts: rockchip: add missing #msi-cells to rk3399
arm64: dts: rockchip: Fix roc-rk3399-pc regulator input rails
arm64: dts: rockchip: Rename vcc12v_sys into dc_12v for roc-rk3399-pc
dt-bindings: document PX30 usb2phy General Register Files
arm64: dts: rockchip: add px30-evb i2c1 devices
arm64: dts: rockchip: document explicit px30 cru dependencies
arm64: dts: rockchip: remove unused pin settings from px30
arm64: dts: rockchip: move px30-evb console output to uart 5
arm64: dts: rockchip: add emmc-powersequence to px30-evb
arm64: dts: rockchip: fix the px30-evb power tree
arm64: dts: rockchip: add default px30 emmc pinctrl
arm64: dts: rockchip: remove px30 emmc_pwren pinctrl
arm64: dts: rockchip: remove static xin32k from px30
arm64: dts: rockchip: fix iface clock-name on px30 iommus
Link: https://lore.kernel.org/r/1650793.YZj09CGBNl@phil
Signed-off-by: Olof Johansson <olof@lixom.net>
as well as a fix for the Gru-Kevin display override and fixing the dt-
binding for Theobroma boards to the correct naming that is also actually
used in the wild.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAl2tm/UQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgeUsB/4uN9dnY062/aFUBOpJx8dLL380YA/tVoFd
tLS1FSt5avkZi5cWZQrpmW+WqXyFZN1i4r6LMnDQmhmRvHiYBVSubLDmzlc2hXLH
m2OOm4+6ukAid1zQhYMSGl2ks3uz0gAesZ+EeLrzsyvA9xnS64a4HswEVRY5gAcN
VXA7gxY4kqnWPr88b/pZwwThGbcHIbT9vctHlicRgyhI8kqW0x/jNVzMnx+iaQwR
CQT6v0mDQhU2Ig03/TZmZmMNbdlR+qpmOhiSSuuttfElNCcrPjWxLMoZWshXnQ6s
ewKwc0JQ1jFlmel8tuPUvCnO39qVX7UixgFZBLTNn6gJFLlFVvFL
=Zs4u
-----END PGP SIGNATURE-----
Merge tag 'v5.4-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
A number of fixes for individual boards like the rockpro64, and Hugsun X99
as well as a fix for the Gru-Kevin display override and fixing the dt-
binding for Theobroma boards to the correct naming that is also actually
used in the wild.
* tag 'v5.4-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: Fix override mode for rk3399-kevin panel
arm64: dts: rockchip: Fix usb-c on Hugsun X99 TV Box
arm64: dts: rockchip: fix RockPro64 sdmmc settings
arm64: dts: rockchip: fix RockPro64 sdhci settings
arm64: dts: rockchip: fix RockPro64 vdd-log regulator settings
dt-bindings: arm: rockchip: fix Theobroma-System board bindings
arm64: dts: rockchip: fix Rockpro64 RK808 interrupt line
Link: https://lore.kernel.org/r/1599050.HRXuSXmxRg@phil
Signed-off-by: Olof Johansson <olof@lixom.net>
- Re-enable SNVS power key for imx6q-logicpd board which was accidentally
disabled by a SoC level change.
- Fix I2C switches on vf610-zii-scu4-aib board by specifying property
i2c-mux-idle-disconnect.
- A fix on imx-scu API that reads UID from firmware to avoid kernel NULL
pointer dump.
- A series from Anson to correct i.MX7 GPT and i.MX8 USDHC IPG clock.
- A fix on DRM_MSM Kconfig regression on i.MX5 by adding the option
explicitly into imx_v6_v7_defconfig.
- Fix ARM regulator states issue for zii-ultra board, which is impacting
stability of the board.
- A correction on CPU core idle state name for LayerScape LX2160A SoC.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJdqHcmAAoJEFBXWFqHsHzOIqAIAJXqhCpbQkP5orCfXdFQxlvb
KpBiK0VEatMwPYAEm19Ij7/raFv+lRGIDo9ZyD9YGyDDIvOvRrSyeqDJCJSTEkol
QwTYl0KSNp2I4D7a0urcO4xMvcJt2QD2k3oe1Pe5mMDn5jbiMHAguUqrH96j/7zv
/9BE4n8aL9YBk6RE86YX0WMoDSfxToVQO+RQJ+7Yg66M83/9oUY3XqGv3svvZMD2
jsYtuHw8ounthr1OJSqcjUPTPLOCoEF+cG9HSkNmMCcShKNZ2wXIzvjeuBOdblKZ
MXnImEse4p7+81rsarGZLfj10tsfam4OibsgFqDIkgsT/aOdsOvXpjfp4/aO46Y=
=DFFA
-----END PGP SIGNATURE-----
Merge tag 'imx-fixes-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
i.MX fixes for 5.4:
- Re-enable SNVS power key for imx6q-logicpd board which was accidentally
disabled by a SoC level change.
- Fix I2C switches on vf610-zii-scu4-aib board by specifying property
i2c-mux-idle-disconnect.
- A fix on imx-scu API that reads UID from firmware to avoid kernel NULL
pointer dump.
- A series from Anson to correct i.MX7 GPT and i.MX8 USDHC IPG clock.
- A fix on DRM_MSM Kconfig regression on i.MX5 by adding the option
explicitly into imx_v6_v7_defconfig.
- Fix ARM regulator states issue for zii-ultra board, which is impacting
stability of the board.
- A correction on CPU core idle state name for LayerScape LX2160A SoC.
* tag 'imx-fixes-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: imx_v6_v7_defconfig: Enable CONFIG_DRM_MSM
arm64: dts: imx8mn: Use correct clock for usdhc's ipg clk
arm64: dts: imx8mm: Use correct clock for usdhc's ipg clk
arm64: dts: imx8mq: Use correct clock for usdhc's ipg clk
ARM: dts: imx7s: Correct GPT's ipg clock source
ARM: dts: vf610-zii-scu4-aib: Specify 'i2c-mux-idle-disconnect'
ARM: dts: imx6q-logicpd: Re-Enable SNVS power key
arm64: dts: lx2160a: Correct CPU core idle state name
arm64: dts: zii-ultra: fix ARM regulator states
soc: imx: imx-scu: Getting UID from SCU should have response
Link: https://lore.kernel.org/r/20191017141851.GA22506@dragon
Signed-off-by: Olof Johansson <olof@lixom.net>
for 5.4, please pull the following:
- Rayangonda fixes the GPIO pins assignment for the Stringray SoCs
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAl2mADgACgkQh9CWnEQH
BwSncRAAtMWJpwK/tVAj6U0RkQf8TWE3Jhwg+1kSZ/+IHOLABRdofqx/jeriNKqZ
7ROwJ4Q1nQ57CzIG9GFIcSsRQH27qJg+cB1jIYkEDO+CTSZd+OuGkSyI5rDecyaE
XakxnHBf/imNp2YrWRdJ/3+qmj9WaGqVXWU+ex2h/fw4uR0i9uaYzSGNyX/+AFtr
xRE0ANeY0+SeRnfcJE1t3HGdqL/qT0B5XhbzYYrnggrhRUaV+bmHuo/ZdtSqcD5d
tCUEXo8CizxlSIf6CUb6k7HXdqdigXSSM50jLfFj+a3OsFFwjxRRr/S1iMI/rSV2
O2axJrgWPIJlZqIUiti7SEu+O+naFOm3CC/oGB/dB/3SL6HZboSHKP5ehP1wckOD
JGw7Ax3m0iwkkYjRP2y1onX1s7Itf9mTzvhAUzxYeI2eVJdU2Ac/E4RWdNj8u9LI
ZJBQoCrkVksz8mlWDE81kl5HQ1Ek+gGhqioJBpZqY2e1C/KJd7vgLy8Qv63tALg1
N21fJU+g0kzqbDA1bK7/v5laMQ7IBL7kQRigqnObDgvLGp76Lvrla2El0oFiZjry
nbx9hQSbsgFs0LUOlGebWN65RJLB8TP9IyQD9UiZaOBy24Sk6jDchzETxAM9+pMq
LCOcnndK+xCg6ATQEyzTp8fu/s3cZ4cS+tN3ztU1ZQF2HQIthdI=
=0Eti
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-5.4/devicetree-arm64-fixes' of https://github.com/Broadcom/stblinux into arm/fixes
This pull request contains Broadcom ARM64-based SoCs Device Tree fixes
for 5.4, please pull the following:
- Rayangonda fixes the GPIO pins assignment for the Stringray SoCs
* tag 'arm-soc/for-5.4/devicetree-arm64-fixes' of https://github.com/Broadcom/stblinux:
arm64: dts: Fix gpio to pinmux mapping
Link: https://lore.kernel.org/r/20191015172356.9650-2-f.fainelli@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
Since we now have bindings for Mali Midgard GPUs, let's use them to
describe Juno's GPU subsystem, if only because we can. Juno sports a
Mali-T624 integrated behind an MMU-400 (as a gesture towards
virtualisation), in their own dedicated power domain with DVFS
controlled by the SCP.
CC: Liviu Dudau <liviu.dudau@arm.com>
CC: Sudeep Holla <sudeep.holla@arm.com>
CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Follow what the sun50i-a64-pine64.dts does and expose all 5 serial
connections.
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Signed-off-by: Maxime Ripard <mripard@kernel.org>
Add CMM units to Renesas R-Car Gen3 SoC that support it, and reference them
from the Display Unit they are connected to.
Sort the 'vsps', 'renesas,cmm' and 'status' properties in the DU unit
consistently in all the involved DTS.
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Link: https://lore.kernel.org/r/20191016085548.105703-8-jacopo+renesas@jmondi.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add a node describing the watchdog found in the application subsystem.
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Specify the firmware-name for the adsp, cdsp and mpss and enable the
nodes.
Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Bluetooth is provided by a wcn3990, which is connected to the main SoC via
blsp1_uart3.
Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Bluetooth is provided by a wcn3990, which is connected to the main SoC via
blsp1_uart3.
Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The blsp1_uart3 peripheral appears to be commonly used for interfacing with
other SoCs on a platform, such as a wcn3990 to provide bluetooth.
Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The BAM in the blsp1 block can be used as a DMA engine to offload work
when managing any of the peripherals in the blsp.
Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
MMC0_SDWP is not connected to the card. Indicate this by adding a
disable-wp flag.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
sdhci0 is connected to an eMMC and sdhci1 is connected to an SD card
slot. Add support for these nodes.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add nodes for the 3 SDHCI instances present on TI's J721E device.
instance 0 supports HS400 (8 bit bus widht, DDR, 400 MBps)
while instances 1 and 2 support SDR104 (4 bit width, SDR, 100 MBps) as
their highest speed modes. Currently, only High speed (50 MHz clock) has
been enabled.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add the sub-mailbox nodes that are used to communicate between MPU and
various remote processors present in the J721E SoCs to the J721E common
processor board. These include the R5F remote processors in the dual-R5F
cluster (MCU_R5FSS0) in the MCU domain and the two dual-R5F clusters
(MAIN_R5FSS0 & MAIN_R5FSS1) in the MAIN domain; the two C66x DSP remote
processors and the single C71x DSP remote processor in the MAIN domain.
These sub-mailbox nodes utilize the System Mailbox clusters 0 through 4.
All the remaining mailbox clusters are currently not used on A72 core,
and so are disabled.
The sub-mailbox nodes added match the hard-coded mailbox configuration
used within the TI RTOS IPC software packages. The R5F processor
sub-systems are assumed to be running in Split mode, so a sub-mailbox
node is used by each of the R5F cores. Only the sub-mailbox node for
the first R5F core in each cluster is used in case of a Lockstep mode
for that R5F cluster.
NOTE:
The GIC_SPI interrupts to be used are dynamically allocated and managed
by the System Firmware through the ti-sci-intr irqchip driver. So, only
valid interrupts (each cluster's User 0 IRQ output) that are used by the
sub-mailbox devices are enabled. This is done to minimize the number of
NavSS Interrupt Router outputs utilized.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The J721E Main NavSS block contains a Mailbox IP instance with
multiple clusters. Each cluster is equivalent to an Mailbox IP
instance on OMAP platforms.
Add all the Mailbox clusters as their own nodes under the MAIN
NavSS cbass_main_navss interconnect node instead of creating an
almost empty parent node for the new K3 mailbox IP and the clusters
as its child nodes. All these nodes are enabled by default in the
base dtsi file, but any cluster that does not define any child
sub-mailbox nodes should be disabled in the corresponding board
dts files.
NOTE:
The NavSS only has a limited number of interrupts, so none of the
interrupts generated by a Mailbox IP are added by default. Only
the needed interrupts that are targeted towards the A72 GIC will
have to be added later on in the board dts files alongside the
corresponding sub-mailbox child nodes.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add the sub-mailbox nodes that are used to communicate between MPU and
the two R5F remote processors present in the MCU domain to the AM654
EVM base board. These sub-mailbox nodes utilize the System Mailbox
clusters 0 and 1. The interrupts associated with the Mailbox Cluster
User interrupt used by the sub-mailbox nodes are also added. The GIC_SPI
interrupt to be used is dynamically allocated and managed by the System
Firmware through the ti-sci-intr irqchip driver. All the remaining
mailbox clusters are currently not used on A53 core, and so are disabled.
The sub-mailbox nodes added match the hard-coded mailbox configuration
used within the TI RTOS IPC software packages. The Cortex R5F processor
sub-system is assumed to be running in Split mode, so a sub-mailbox node
is used by each of the R5F cores. Only the sub-mailbox node from cluster 0
is used in case of Lockstep mode.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The AM65x Main NavSS block contains a Mailbox IP instance with
multiple clusters. Each cluster is equivalent to an Mailbox IP
instance on OMAP platforms.
Add all the Mailbox clusters as their own nodes under the MAIN
NavSS cbass_main_navss interconnect node instead of creating an
almost empty parent node for the new K3 mailbox IP and the clusters
as its child nodes. All these nodes are enabled by default in the
base dtsi file, but any cluster that does not define any child
sub-mailbox nodes should be disabled in the corresponding board
dts files.
NOTE:
The NavSS only has a limited number of interrupts, so none of the
interrupts generated by a Mailbox IP are added by default. Only
the needed interrupts that are targeted towards the A53 GIC will
have to be added later on in the board dts files alongside the
corresponding sub-mailbox child nodes.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add the rc-vega-s9x keymap to the existing IR node in the device tree.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add an IR node to the Vega S96 dts to include the rc-vega-s9x keymap.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add missing #colling-cells field for G12B SoC
Add cooling-map for passive and hot trip point
Tested-by: Christian Hewitt <christianshewitt@gmail.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add missing #colling-cells field for G12A SoC
Add cooling-map for passive and hot trip point
Tested-by: Christian Hewitt <christianshewitt@gmail.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add minimal thermal zone for two temperature sensor
One is located close to the DDR and the other one is
located close to the PLLs (between the CPU and GPU)
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Tested-by: Christian Hewitt <christianshewitt@gmail.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add cpu and ddr temperature sensors for G12 Socs
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Tested-by: Christian Hewitt <christianshewitt@gmail.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add and enable the audio devices on the sei610.
The new FRDDR/TODDR D of the SM1 have been left out on purpose. The
plaftorm has 2 possible playback interfaces and 3 possible capture
interfaces. 3 pcm interfaces for each direction is enough.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add the audio devices found on the SM1 SoC family. Only the spdif output
and input are missing. These are not supported yet since no platform is
available to them.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
an USB3.0 Type A connector and a M.2 Key M slot.
The PHY driving these differential lines is shared between
the USB3.0 controller and the PCIe Controller, thus only
a single controller can use it.
The needed DT configuration when the MCU is configured to mux
the PCIe/USB3.0 differential lines to the M.2 Key M slot is
added commented and may be uncommented to disable USB3.0 from the
USB Complex and enable the PCIe controller.
The End User is not expected to uncomment the following except for
testing purposes, but instead rely on the firmware/bootloader to
update these nodes accordingly if PCIe mode is selected by the MCU.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
This adds the Amlogic G12A PCI Express controller node, also
using the USB3+PCIe Combo PHY.
The PHY mode selection is static, thus the USB3+PCIe Combo PHY
phandle would need to be removed from the USB control node if the
shared differential lines are used for PCIe instead of USB3.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Add nodes for Volume UP button connected to GPIO and Volume DOWN button,
which is handled by the pm8916 as is common with msm8916 devices.
Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Nikita Travkin <nikitos.tr@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
WCNSS is used on L8150 for WiFi and BT.
Its firmware isn't relocatable and must be loaded at specific address.
Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Nikita Travkin <nikitos.tr@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
All nodes are better to follow alphabetical sort except iomuxc
which has huge pinctrl data, better to put it at the end of
file.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Adjust some nodes to make them follow alphabetical sort except
iomuxc node which is put at the end of file because of its huge
pinctrl data.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
layerscape otg function should be supported HNP SRP and ADP protocol
accroing to rm doc, but dwc3 code not realize it and use id pin to
detect who is host or device(0 is host 1 is device) this patch is to
enable OTG mode on ls1028ardb ls1088ardb and ls1046ardb in dts
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The iomuxc node is being put at end of file because of its huge
pinctrl data. I2C devices should be placed in alphabetical sort.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On i.MX8MQ, usdhc's ipg clock is from IMX8MQ_CLK_IPG_ROOT,
assign it explicitly instead of using IMX8MQ_CLK_DUMMY.
Fixes: 748f908cc8 ("arm64: add basic DTS for i.MX8MQ")
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
In order to maximise performance of the LCD Controller's 64-bit AXI
bus, for any give speed bin of the device, the AXI master interface
clock(ACLK) clock can be up to CPU_frequency/2, which is already
capable of optimal performance. In general, ACLK is always expected
to be equal to CPU_frequency/2. APB slave interface clock(PCLK) and
Main processing clock(PCLK) both are tied to the same clock as ACLK.
This change followed the LS1028A Architecture Specification Manual.
Signed-off-by: Wen He <wen.he_1@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
lx2160a support PW15 but not PW20, correct name to avoid confusing.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Fixes: 00c5ce8ac0 ("arm64: dts: lx2160a: add cpu idle support")
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
In the same way as for msm8974-hammerhead, l21 load, used for SDCARD
VMMC, needs to be increased in order to prevent any voltage drop issues
(due to limited current) happening with some SDCARDS or during specific
operations (e.g. write).
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Fixes: 660a9763c6 (arm64: dts: qcom: db820c: Add pm8994 regulator node)
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
According to the RockPro64 schematic [1] the rk3399 sdmmc controller is
connected to a microSD (TF card) slot. Remove the cap-mmc-highspeed
property of the sdmmc controller, since no mmc card can be connected here.
[1] http://files.pine64.org/doc/rockpro64/rockpro64_v21-SCH.pdf
Fixes: e4f3fb4909 ("arm64: dts: rockchip: add initial dts support for Rockpro64")
Signed-off-by: Soeren Moch <smoch@web.de>
Link: https://lore.kernel.org/r/20191004203213.4995-1-smoch@web.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Scarlet and Bob use the Google-developed cr50 chip to do things
like TPM and closed-case-debugging.
Add the nodes describing the cr50 and its spi-connection.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20180822120925.12388-1-heiko@sntech.de
This adds a reference to the dts of the Raspberry Pi 4 B,
so we don't need to maintain the content in arm64.
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
The plan for the HiHope RZ/G2N board is to enable pciec0 by default,
and use pciec1 physical interface for SATA (as SATA and PCIE1 share
the same physical interface), therefore move pciec1 enabling away
from hihope-rzg2-ex.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Link: https://lore.kernel.org/r/1570178133-21532-8-git-send-email-fabrizio.castro@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds support for Advantech idk-1110wr LVDS panel.
The HiHope RZ/G2[MN] is advertised as compatible with panel
idk-1110wr from Advantech, however the panel isn't sold alongside
the board.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/1570029619-43238-10-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
RZ/G2N board is pin compatible with RZ/G2M board. However on the SoC
side RZ/G2N uses DU3 where as RZ/G2M uses DU2 for the DPAD. In order to
reuse the common dtsi for both the boards, it is required to move du clock
properties from common dtsi to board specific dts.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/1570029619-43238-2-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
