1. Current QCOM I2C driver hangs when sending data to address 0x03-0x07
in some scenarios. The QUP controller generates invalid write in this
case, since these addresses are reserved for different bus formats.
2. Also, the error handling is done by I2C QUP ISR in the case of DMA
mode. The state need to be RESET in case of any error for clearing the
available data in FIFO, which otherwise leaves the BAM DMA controller
in hang state.
This patch fixes the above two issues by clearing the error bits from
I2C and QUP status in ISR in case of I2C error, QUP error and resets
the QUP state to clear the FIFO data.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
qup_i2c_issue_read() derives the address from i2c_msg.
This called in the read path when I2C_M_RD flag is set.
Therefore, use the 8 bit address helper function.
Signed-off-by: Naveen Kaje <nkaje@codeaurora.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Among the bus errors reported from the QUP_MASTER_STATUS register
only NACK is considered and transfer gets suspended, while
other errors are ignored. Correct this and suspend the transfer
for other errors as well. This avoids unnecessary 'timeouts' which
happens when waiting for events that would never happen when there
is already an error condition on the bus. Also the error handling
procedure should be the same for both NACK and other bus errors in
case of dma mode. So correct that as well.
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
With CONFIG_DEBUG_SG is enabled and when dma mode is used, below dump is seen,
------------[ cut here ]------------
kernel BUG at include/linux/scatterlist.h:140!
Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.0-00459-g9f087b9-dirty #7
Hardware name: Qualcomm Technologies, Inc. APQ 8016 SBC (DT)
task: ffffffc036868000 ti: ffffffc036870000 task.ti: ffffffc036870000
PC is at qup_sg_set_buf.isra.13+0x138/0x154
LR is at qup_sg_set_buf.isra.13+0x50/0x154
pc : [<ffffffc0005a0ed8>] lr : [<ffffffc0005a0df0>] pstate: 60000145
sp : ffffffc0368735c0
x29: ffffffc0368735c0 x28: ffffffc036873752
x27: ffffffc035233018 x26: ffffffc000c4e000
x25: 0000000000000000 x24: 0000000000000004
x23: 0000000000000000 x22: ffffffc035233668
x21: ffffff80004e3000 x20: ffffffc0352e0018
x19: 0000004000000000 x18: 0000000000000028
x17: 0000000000000004 x16: ffffffc0017a39c8
x15: 0000000000001cdf x14: ffffffc0019929d8
x13: ffffffc0352e0018 x12: 0000000000000000
x11: 0000000000000001 x10: 0000000000000001
x9 : ffffffc0012b2d70 x8 : ffffff80004e3000
x7 : 0000000000000018 x6 : 0000000030000000
x5 : ffffffc00199f018 x4 : ffffffc035233018
x3 : 0000000000000004 x2 : 00000000c0000000
x1 : 0000000000000003 x0 : 0000000000000000
Process swapper/0 (pid: 1, stack limit = 0xffffffc036870020)
Stack: (0xffffffc0368735c0 to 0xffffffc036874000)
sg_set_bug expects that the buf parameter passed in should be from
lowmem and a valid pageframe. This is not true for pages from
dma_alloc_coherent which can be carveouts, hence the check fails.
Change allocation of sg buffers from dma_coherent memory to kzalloc
to fix the issue. Note that now dma_map/unmap is used to make the
kzalloc'ed buffers coherent before passing it to the dmaengine.
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
After the addition of V2 support, there was a regression observed
when testing it on MSM8996. The reason is driver puts the controller
in to RUN state and writes the data to be 'tx' ed in fifo. But controller
has to be put in to 'PAUSE' state and data has to written to fifo. Then
should be put in to 'RUN' state separately.
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Tested-by: Pramod Gurav <gpramod@codeaurora.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
QUP cores can be attached to a BAM module, which acts as
a dma engine for the QUP core. When DMA with BAM is enabled,
the BAM consumer pipe transmitted data is written to the
output FIFO and the BAM producer pipe received data is read
from the input FIFO.
With BAM capabilities, qup-i2c core can transfer more than
256 bytes, without a 'stop' which is not possible otherwise.
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
Tested-by: Archit Taneja <architt@codeaurora.org>
Tested-by: Telkar Nagender <ntelkar@codeaurora.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
The definition of i2c_msg says that
"If this is the last message in a group, it is followed by a STOP.
Otherwise it is followed by the next @i2c_msg transaction segment,
beginning with a (repeated) START"
So the expectation is that there is no 'STOP' bit inbetween individual
i2c_msg segments with repeated 'START'. Adding the support for the same.
This is required for some clients like touchscreen which keeps
incrementing counts across individual transfers and 'STOP' bit inbetween
resets the counter, which is not required.
This patch adds the support in non-dma mode.
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
Tested-by: Archit Taneja <architt@codeaurora.org>
Tested-by: Telkar Nagender <ntelkar@codeaurora.org>
[wsa: updated commit message]
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
QUP from version 2.1.1 onwards, supports a new format of
i2c command tags. Tag codes instructs the controller to
perform a operation like read/write. This new tagging version
supports bam dma and transfers of more than 256 bytes without 'stop'
in between. Adding the support for the same.
For each block a data_write/read tag and data_len tag is added to
the output fifo. For the final block of data write_stop/read_stop
tag is used.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Tested-by: Archit Taneja <architt@codeaurora.org>
Tested-by: Telkar Nagender <ntelkar@codeaurora.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
qup_wait_writeready waits only on a output fifo empty event.
Change the same function to accept the event and data length
to wait as parameters. This way the same function can be used for
timeouts in other places as well.
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
Tested-by: Archit Taneja <architt@codeaurora.org>
Tested-by: Telkar Nagender <ntelkar@codeaurora.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
The runtime pm calls need to be done before populating the children via the
i2c_add_adapter call. If this is not done, a child can run into issues trying
to do i2c read/writes due to the pm_runtime_sync failing.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Cc: stable@kernel.org
This fixes a error handling scenario where clocks were not being disabled
when QUP_OUTPUT_BLOCK_SIZE returns a size greater than the size of blk_sizes
array. So this patch adds a statement to jump to the fail lable to release the
clocks.
Signed-off-by: Pramod Gurav <pramod.gurav@smartplayin.com>
Acked-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This patch corrects the error check on the call to pm_runtime_get_sync.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Reviewed-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
It is used with of_property_read_u32(), so it should be u32.
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Fixes: 10c5a84259 ('i2c: qup: New bus driver for the Qualcomm QUP I2C controller')
These should ">= ARRAY_SIZE()" instead of "> ARRAY_SIZE()".
Fixes: 10c5a84259 ('i2c: qup: New bus driver for the Qualcomm QUP I2C controller')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This bus driver supports the QUP i2c hardware controller in the Qualcomm SOCs.
The Qualcomm Universal Peripheral Engine (QUP) is a general purpose data path
engine with input/output FIFOs and an embedded i2c mini-core. The driver
supports FIFO mode (for low bandwidth applications) and block mode (interrupt
generated for each block-size data transfer).
Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Reviewed-by: Andy Gross <agross@codeaurora.org>
Tested-by: Philip Elcan <pelcan@codeaurora.org>
[wsa: removed needless IS_ERR_VALUE]
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
