Commit Graph

8 Commits

Author SHA1 Message Date
Kumar Gala
1e8ed06d34 powerpc/mpc85xx: Add FSL QorIQ DPAA BMan support to device tree(s)
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Signed-off-by: Hai-Ying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
[Emil Medve: Sync with the upstream binding]
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2015-03-23 19:51:19 -05:00
Emil Medve
eaffcb0f1b powerpc/dts: Factorize the clock control node
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Change-Id: I25ce24a25862b4ca460164159867abefe00ccdd1
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-11-07 18:10:49 -06:00
Scott Wood
e83eb028bb powerpc/fsl: Add fsl,portid-mapping to corenet1-cf chips
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Diana Craciun <diana.craciun@freescale.com>
2014-05-22 18:10:42 -05:00
Diana Craciun
846c944357 powerpc/fsl: Updated corenet-cf compatible string for corenet1-cf chips
Updated the device trees according to the corenet-cf
binding definition.

Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-05-22 18:08:28 -05:00
Tang Yuantian
5d1a566e51 powerpc/mpc85xx: Update clock nodes in device tree
The following SoCs will be affected: p2041, p3041, p4080,
p5020, p5040, b4420, b4860, t4240

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-19 16:04:23 -05:00
Stephen George
37f2808bc0 powerpc/fsl-booke: Update DCSR EPU device tree entries for existing SoCs
Identifies the epu as compatible with Chassis v1 Debug IP.

Signed-off-by: Stephen George <Stephen.George@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2013-03-18 14:09:28 -05:00
Timur Tabi
0408753fae powerpc/85xx: describe the PAMU topology in the device tree
The PAMU caches use the LIODNs to determine which cache lines hold the
entries for the corresponding LIODs.  The LIODNs must therefore be
carefully assigned to avoid cache thrashing -- two active LIODs with
LIODNs that put them in the same cache line.

Currently, LIODNs are statically assigned by U-Boot, but this has
limitations.  LIODNs are assigned even for devices that may be disabled
or unused by the kernel.  Static assignments also do not allow for device
drivers which may know which LIODs can be used simultaneously.  In
other words, we really should assign LIODNs dynamically in Linux.

To do that, we need to describe the PAMU device and cache topologies in
the device trees.

Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Stuart Yoder <stuart.yoder@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2013-02-13 07:49:02 -06:00
Kim Phillips
7a4da6f70b powerpc/85xx: add Freescale P5040 SOC and SEC v5.2 device trees
Add device tree (dtsi) files for the Freescale P5040 SOC.  Since this
SOC introduces SEC v5.2, add the dtsi file for that also.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-09-12 14:57:07 -05:00