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powerpc/fsl: Updated corenet-cf compatible string for corenet1-cf chips

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Updated the device trees according to the corenet-cf
binding definition.

Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Diana Craciun 2014-05-07 09:29:17 +03:00 committed by Scott Wood
parent f2e7bfbb04
commit 846c944357
5 changed files with 5 additions and 5 deletions
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2
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
View File

@ -246,7 +246,7 @@ cpc: l3-cache-controller@10000 {
};
corenet-cf@18000 {
compatible = "fsl,corenet-cf";
compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
reg = <0x18000 0x1000>;
interrupts = <16 2 1 31>;
fsl,ccf-num-csdids = <32>;

2
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
View File

@ -273,7 +273,7 @@ cpc: l3-cache-controller@10000 {
};
corenet-cf@18000 {
compatible = "fsl,corenet-cf";
compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
reg = <0x18000 0x1000>;
interrupts = <16 2 1 31>;
fsl,ccf-num-csdids = <32>;

2
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
View File

@ -281,7 +281,7 @@ cpc: l3-cache-controller@10000 {
};
corenet-cf@18000 {
compatible = "fsl,corenet-cf";
compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
reg = <0x18000 0x1000>;
interrupts = <16 2 1 31>;
fsl,ccf-num-csdids = <32>;

2
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
View File

@ -278,7 +278,7 @@ cpc: l3-cache-controller@10000 {
};
corenet-cf@18000 {
compatible = "fsl,corenet-cf";
compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
reg = <0x18000 0x1000>;
interrupts = <16 2 1 31>;
fsl,ccf-num-csdids = <32>;

2
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
View File

@ -233,7 +233,7 @@ cpc: l3-cache-controller@10000 {
};
corenet-cf@18000 {
compatible = "fsl,corenet-cf";
compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
reg = <0x18000 0x1000>;
interrupts = <16 2 1 31>;
fsl,ccf-num-csdids = <32>;