Commit Graph

13085 Commits

Author SHA1 Message Date
Jani Nikula
2a307c2e91 drm/i915: add some more "i" in platform names for consistency
Consistency FTW.

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/9ab811dc06570bd3fc05a917ade1bdc9bb805a75.1480520526.git.jani.nikula@intel.com
2016-12-07 15:19:31 +02:00
Jani Nikula
c0f86832e3 drm/i915: rename BROADWATER and CRESTLINE to I965G and I965GM, respectively
Add more consistency to our naming. Pineview remains the outlier. Keep
using code names for gen5+.

v2: rebased

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1481105584-23033-1-git-send-email-jani.nikula@intel.com
2016-12-07 15:18:33 +02:00
Jani Nikula
a5ce929bc3 drm/i915: keep intel device info structs in gen based order
Move G33 and Pineview higher up in the list. Add a couple of blank lines
for OCD while at it.

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/ef4cc8e6ddf592c8c2769b84d4b88a5422d46ea5.1480520526.git.jani.nikula@intel.com
2016-12-07 15:15:53 +02:00
Jani Nikula
2e0d26f866 drm/i915: replace platform flags with a platform enum
The platform flags in device info are (mostly) mutually
exclusive. Replace the flags with an enum. Add the platform enum also
for platforms that previously didn't have a flag, and give them codename
logging in dmesg.

Pineview remains an exception, the platform being G33 for that.

v2: Sort enum by gen and date

v3: rebase on geminilake enabling

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480596595-3278-1-git-send-email-jani.nikula@intel.com
2016-12-07 11:58:26 +02:00
Arkadiusz Hiler
c499af5a69 drm/i915/guc: Drop comment on fwif autogeneration
The firmware interface file was initially partially autogenerated, but
this is no longer the case.

It was never updated automatically, and a lot manual changes were
introduced since.

>From now on any changes to the firmware interface will be managed by
hand, which gives us flexibility when it comes to structure reuse
(HuC/GuC) and naming conventions.

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Jeff Mcgee <jeff.mcgee@intel.com>
Cc: Sagar A. Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480953869-25267-1-git-send-email-arkadiusz.hiler@intel.com
2016-12-07 07:10:21 +00:00
Michel Thierry
70821af60b drm/i915: Keep has_* in alphabetical order
As it already says in the comment block...

Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161206015704.12654-1-michel.thierry@intel.com
2016-12-07 07:09:55 +00:00
Michel Thierry
9e1d0e604e drm/i915: Advertise ppgtt support type in platform definition
Instead of being hidden in sanitize_enable_ppgtt.
It also seems to be the place to do so nowadays.

Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2016-12-07 07:09:55 +00:00
Chris Wilson
d637c17832 drm/i915: Use memcpy_from_wc for GPU error capture
On all platforms we now always read the contents of buffers via the GTT,
i.e. using WC cpu access. Reads are slow, but they can be accelerated
with an internal read buffer using sse4.1 (movntqda). This is our
i915_memcpy_from_wc() routine which also checks for sse4.1 support and
so we can fallback to using a regular slow memcpy if we need to.

When compressing the pages, the reads are currently done inside zlib's
fill_window() routine and so we must copy the page into a temporary
which is then already inside the CPU cache and fast for zlib's
compression. When not compressing the pages, we don't need a temporary
and can just use the accelerated read from WC into the destination.

v2: Use zstream locals to reduce diff and allocate the additional
temporary storage only if sse4.1 is supported.
v3: Use length=0 for the sse4.1 support check

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161206124051.17040-1-chris@chris-wilson.co.uk
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2016-12-06 14:23:16 +00:00
Matthew Auld
4cfa20c834 drm/i915: allow GEM_BUG_ON expr checking with !DEBUG_GEM
Use BUILD_BUG_ON_INVALID(expr) in GEM_BUG_ON when building without
DEBUG_GEM. This means the compiler can now check the validity of expr
without generating any code, in turn preventing us from inadvertently
breaking the build when DEBUG_GEM is not enabled.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161202184750.3843-1-matthew.auld@intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-12-05 20:49:17 +00:00
Chris Wilson
0798cff46b drm/i915/execlists: Use list_safe_reset_next() instead of opencoding
list.h provides a macro for updating the next element in a safe
list-iter, so let's use it so that it is hopefully clearer to the reader
about the unusual behaviour, and also easier to grep.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161205142941.21965-6-chris@chris-wilson.co.uk
2016-12-05 20:49:17 +00:00
Chris Wilson
bdb821ca44 drm/i915: Enable swfence debugobject support for i915.ko
Only once the debugobject symbols are exported can we enable support for
debugging swfences when i915 is built as a module. Requires commit
2617fdca3f68 ("lib/debugobjects: export for use in modules")

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161205142941.21965-5-chris@chris-wilson.co.uk
2016-12-05 20:49:17 +00:00
Chris Wilson
778e23a9e0 drm/i915: Implement local atomic_state_free callback
As we use debugobjects to track the lifetime of fences within our atomic
state, we ideally want to mark those objects as freed along with their
containers. This merits us hookin into config->funcs->atomic_state_free
for this purpose.

This allows us to enable debugobjects for sw-fences without triggering
known issues.

Fixes: fc1584059d ("drm/i915: Integrate i915_sw_fence with debugobjects")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161205142941.21965-4-chris@chris-wilson.co.uk
2016-12-05 20:49:17 +00:00
Chris Wilson
7d1d9aea3e drm/i915: Tidy i915_gem_valid_gtt_space()
We can replace a couple of tests with an assertion that the passed in
node is already allocated (as matches the existing call convention) and
by a small bit of refactoring we can bring the line lengths to under
80cols.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161205142941.21965-3-chris@chris-wilson.co.uk
2016-12-05 20:49:17 +00:00
Chris Wilson
172ae5b4c8 drm/i915: Fix i915_gem_evict_for_vma (soft-pinning)
Soft-pinning depends upon being able to check for availabilty of an
interval and evict overlapping object from a drm_mm range manager very
quickly. Currently it uses a linear list, and so performance is dire and
not suitable as a general replacement. Worse, the current code will oops
if it tries to evict an active buffer.

It also helps if the routine reports the correct error codes as expected
by its callers and emits a tracepoint upon use.

For posterity since the wrong patch was pushed (i.e. that missed these
key points and had known bugs), this is the changelog that should have
been on commit 506a8e87d8 ("drm/i915: Add soft-pinning API for
execbuffer"):

Userspace can pass in an offset that it presumes the object is located
at. The kernel will then do its utmost to fit the object into that
location. The assumption is that userspace is handling its own object
locations (for example along with full-ppgtt) and that the kernel will
rarely have to make space for the user's requests.

This extends the DRM_IOCTL_I915_GEM_EXECBUFFER2 to do the following:
* if the user supplies a virtual address via the execobject->offset
  *and* sets the EXEC_OBJECT_PINNED flag in execobject->flags, then
  that object is placed at that offset in the address space selected
  by the context specifier in execbuffer.
* the location must be aligned to the GTT page size, 4096 bytes
* as the object is placed exactly as specified, it may be used by this
  execbuffer call without relocations pointing to it

It may fail to do so if:
* EINVAL is returned if the object does not have a 4096 byte aligned
  address
* the object conflicts with another pinned object (either pinned by
  hardware in that address space, e.g. scanouts in the aliasing ppgtt)
  or within the same batch.
  EBUSY is returned if the location is pinned by hardware
  EINVAL is returned if the location is already in use by the batch
* EINVAL is returned if the object conflicts with its own alignment (as meets
  the hardware requirements) or if the placement of the object does not fit
  within the address space

All other execbuffer errors apply.

Presence of this execbuf extension may be queried by passing
I915_PARAM_HAS_EXEC_SOFTPIN to DRM_IOCTL_I915_GETPARAM and checking for
a reported value of 1 (or greater).

v2: Combine the hole/adjusted-hole ENOSPC checks
v3: More color, more splitting, more blurb.

Fixes: 506a8e87d8 ("drm/i915: Add soft-pinning API for execbuffer")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161205142941.21965-2-chris@chris-wilson.co.uk
2016-12-05 20:49:17 +00:00
Chris Wilson
85fd4f58d7 drm/i915: Mark all non-vma being inserted into the address spaces
We need to distinguish between full i915_vma structs and simple
drm_mm_nodes when considering eviction (i.e. we must be careful not to
treat a mere drm_mm_node as a much larger i915_vma causing memory
corruption, if we are lucky). To do this, color these not-a-vma with -1
(I915_COLOR_UNEVICTABLE).

v2...v200: New name for -1.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161205142941.21965-1-chris@chris-wilson.co.uk
2016-12-05 20:49:17 +00:00
Hans de Goede
721d484563 drm/i915/dsi: Do not clear DPOUNIT_CLOCK_GATE_DISABLE from vlv_init_display_clock_gating
On my Cherrytrail CUBE iwork8 Air tablet PIPE-A would get stuck on loading
i915 at boot 1 out of every 3 boots, resulting in a non functional LCD.
Once the i915 driver has successfully loaded, the panel can be disabled /
enabled without hitting this issue.

The getting stuck is caused by vlv_init_display_clock_gating() clearing
the DPOUNIT_CLOCK_GATE_DISABLE bit in DSPCLK_GATE_D when called from
chv_pipe_power_well_ops.enable() on driver load, while a pipe is enabled
driving the DSI LCD by the BIOS.

Clearing this bit while DSI is in use is a known issue and
intel_dsi_pre_enable() / intel_dsi_post_disable() already set / clear it
as appropriate.

This commit modifies vlv_init_display_clock_gating() to leave the
DPOUNIT_CLOCK_GATE_DISABLE bit alone fixing the pipe getting stuck.

Changes in v2:
-Replace PIPE-A with "a pipe" or "the pipe" in the commit msg and
comment

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97330
Cc: stable@vger.kernel.org
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161202142904.25613-1-hdegoede@redhat.com
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2016-12-05 20:45:58 +02:00
Ville Syrjälä
e339d67eeb drm/i915: Pass crtc state to vlv_compute_wm_level()
Rather than accessing crtc->config in vlv_compute_wm_level() let's
pass in the crtc state explicitly. One step closer to atomic.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480354637-14209-16-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2016-12-05 16:23:28 +02:00
Ville Syrjälä
fa292a4be9 drm/i915: Clean up vlv_program_watermarks()
Add small helpers to make the intent of the staggered enable/disable
sequence in vlv_program_watermarks() easier on the eyes.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480354637-14209-15-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2016-12-05 16:23:28 +02:00
Ville Syrjälä
50f4caef86 drm/i915: Write all DDL registers in one go
We'll want to decouple the vlv/chv wm register reprogramming from any
single pipe. So let's just write all the DDL registers in one go. We
already write all the wm registers anyway since the bits are sprinkled
all over the place and so writing them for just a single pipe would have
been too messy anyway.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480354637-14209-14-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2016-12-05 16:23:28 +02:00
Ville Syrjälä
6fe6a7ffd3 drm/i915: Zero out HOWM registers before writing new WM/HOWM register values
On VLV/CHV some of the watermark values are split across two registers:
low order bits in one, and high order bits in another. So we may not be
able to update a single watermark value atomically, and thus we must be
careful that we don't temporarily introduce out of bounds values during
the reprogramming. To prevent this we can simply zero out all the high
order bits initially, then we update the low order bits, and finally
we update the high order bits with the final value.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480354637-14209-13-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2016-12-05 16:23:27 +02:00
Ville Syrjälä
11a85d6ab1 drm/i915: Skip vblank wait if cxsr was already off
Before we attempt to turn any planes on or off we must first exit
csxr. That's due to cxsr effectively making the plane enable bits
read-only. Currently we achieve that with a vblank wait right after
toggling the cxsr enable bit. We do the vblank wait even if cxsr was
already off, which seems wasteful, so let's try to only do it when
absolutely necessary.

We could start tracking the cxsr state fully somewhere, but for now
it seems easiest to just have intel_set_memory_cxsr() return the
previous cxsr state.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480354637-14209-11-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2016-12-05 16:23:27 +02:00
Ville Syrjälä
3d90e649fa drm/i915: Protect cxsr state with wm_mutex
Let's protect the cxsr state with the wm_mutex, since it might
get poked from multiple places if there's a parallel plane update
happening with a pipe getting enable/disabled.

It's still pretty racy for the old platforms, but for vlv/chv it
should work, I think. If not, we'll improve it later anyway.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480354637-14209-10-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2016-12-05 16:23:27 +02:00
Ville Syrjälä
7c951c0025 drm/i915: Pass around dev_priv in vlv wm functions
Passing dev_priv instead of dev is the future. Let's make the vlv/chv wm
functions respect that idea.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480354637-14209-9-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2016-12-05 16:23:26 +02:00
Ville Syrjälä
26cca0e5f3 drm/i915: Introduce vlv_invert_wm_value()
Add a small helper to do invert the vlv/chv values. Less fragile
perhaps, and let's us clearly mark all overlarge wateramarks as
disabled (by just making them all USHRT_MAX).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480354637-14209-8-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2016-12-05 16:23:26 +02:00
Ville Syrjälä
1b31389cd0 drm/i915: Organize vlv/chv watermarks by plane_id
Store the vlv/chv watermark values in straight up arrays indexed by
enum plane_id. Avoids a lot of useless checks for the plane type when
we don't have to think which structure member we need to access.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480354637-14209-7-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2016-12-05 16:23:26 +02:00
Ville Syrjälä
6b6b3eeffb drm/i915: Remove duplicated wm setup for vlv and chv
The code for vlv and chv wm latency/function pointer setup is
identical. Drop one of the copies.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480354637-14209-6-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2016-12-05 16:23:25 +02:00
Ville Syrjälä
50a9dd3f24 drm/i915: Clean up VLV/CHV maxfifo watermark setup
Let's compute the maxfifo watermarks using max() instead of min().
Can't even recall why I did it the other way originally. Anyways
using max() avoids having to initialize the watermarks to the max
value first.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480354637-14209-5-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2016-12-05 16:23:25 +02:00
Ville Syrjälä
1be4d3793d drm/i915: Fix the level 0 max_wm hack on VLV/CHV
The watermark should never exceed the FIFO size, so we need to
check against the current FIFO size instead of the theoretical
maximum when we clamp the level 0 watermark.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480354637-14209-4-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2016-12-05 16:23:24 +02:00
Ville Syrjälä
ddd2b792cc drm/i915: Use the ilk_disable_lp_wm() return value
ilk_disable_lp_wm() will tell us whether the LP1+ watermarks were
disabled or not, and hence whether we need to for the vblank wait or
not. Let's use that information to eliminate some useless vblank
waits.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480354637-14209-3-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2016-12-05 16:23:24 +02:00
Ville Syrjälä
3125d39fe6 drm/i915: Drop the nop intel_update_watermarks() call from haswell_crtc_enable()
HSW+ all use the .initial_watermarks() hook, so there's no point in
calling intel_update_watermarks() from HSW+ specific code. We'll still
hang on to the .initial_watermarks NULL check since theoretically if the
memory latencies are not populated we would not populate the function
pointer either.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480354637-14209-2-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2016-12-05 16:23:24 +02:00
Dhinakaran Pandiyan
22a2c8e045 drm/i915: Validate mode against max. link data rate for DP MST
Not validating the mode rate against max. link rate results in not pruning
invalid modes. For e.g, a HBR2 5.4 Gbps 2-lane configuration does not
support 4k@60Hz. But, we do not reject this mode.

So, make use of the helpers in intel_dp to validate mode data rate against
max. link data rate of a configuration.

v3: Renamed local variables again for consistency (Manasi)
v2: Renamed mode data rate local variable to be more explanatory.

Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1479243546-17189-1-git-send-email-dhinakaran.pandiyan@intel.com
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2016-12-05 16:23:18 +02:00
Dhinakaran Pandiyan
fd81c44eba drm/i915: Fix DP link rate math
We store DP link rates as link clock frequencies in kHz, just like all
other clock values. But, DP link rates in the DP Spec. are expressed in
Gbps/lane, which seems to have led to some confusion.

E.g., for HBR2
Max. data rate = 5.4 Gbps/lane x 4 lane x 8/10 x 1/8 = 2160000 kBps
where, 8/10 is for channel encoding and 1/8 is for bit to Byte conversion

Using link clock frequency, like we do
Max. data rate = 540000 kHz * 4 lanes = 2160000 kSymbols/s
Because, each symbol has 8 bit of data, this is 2160000 kBps
and there is no need to account for channel encoding here.

But, currently we do 540000 kHz * 4 lanes * (8/10) = 1728000 kBps

Similarly, while computing the required link bandwidth for a mode,
there is a mysterious 1/10 term.
This should simply be pixel_clock kHz * (bpp/8) to give the final result in
kBps

v2: Changed to DIV_ROUND_UP() and comment changes (Ville)

Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1479160220-17794-1-git-send-email-dhinakaran.pandiyan@intel.com
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2016-12-05 16:23:02 +02:00
Imre Deak
3c30c7f7b0 drm/i915: Add I2C and DP-AUX char devices to debug kconfig
These char devices exposing the driver's I2C and DP-AUX adapters for
user space tools are useful to debug display output related issues.
Enable them with the rest of additional driver debug options.

Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480696541-13697-1-git-send-email-imre.deak@intel.com
2016-12-05 13:17:34 +02:00
Daniel Vetter
93cd6fa680 Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next-queued
Resync, and we need all the fancy new drm_mm stuff to implement more
efficient evict algorithms for softpin.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
2016-12-05 09:52:17 +01:00
Daniel Vetter
ce6612d684 drm/i915: Update DRIVER_DATE to 20161205
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2016-12-05 09:25:26 +01:00
Dave Airlie
f03ee46be9 Linux 4.9-rc8
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Backmerge tag 'v4.9-rc8' into drm-next

Linux 4.9-rc8

Daniel requested this so we could apply some follow on fixes cleanly to -next.
2016-12-05 17:11:48 +10:00
Rodrigo Vivi
01a551971c drm/i915: Only poll DW3_A when init DDI PHY for ports B and C.
According to Bspec we need to
"Poll for PORT_REF_DW3_A grc_done == 1b"
only on ports B and C initialization sequence when
copying rcomp from port A.

So let's follow the spec and only poll for that case
and not on every port A initialization.

v2: Also remove the grc_done check from bxt_ddi_phy_is_enabled()
    otherwise it might believe it is disabled and force it to re program.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1479410256-25735-1-git-send-email-rodrigo.vivi@intel.com
2016-12-02 12:16:25 -08:00
Ander Conselvan de Oliveira
e9c9882556 drm/i915/glk: Configure number of sprite planes properly
Geminilake has 4 planes (3 sprites) per pipe.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-10-git-send-email-ander.conselvan.de.oliveira@intel.com
2016-12-02 16:42:36 +02:00
Ander Conselvan de Oliveira
b817c440c1 drm/i915/glk: Implement core display init/uninit sequence for geminilake
The sequence is pretty much the same as broxton, except that bspec
requires the AUX domains to be enabled. But since those can't be enabled
before the phys are initialized, we just use the same sequence as
broxton.

v2: Don't manually enable AUX domains. (Ander)

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-9-git-send-email-ander.conselvan.de.oliveira@intel.com
2016-12-02 16:42:27 +02:00
Ander Conselvan de Oliveira
09d093869f drm/i915/glk: Allow dotclock up to 2 * cdclk on geminilake
Geminilake has double wide pipes so it can output two pixels per CD
clock.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-8-git-send-email-ander.conselvan.de.oliveira@intel.com
2016-12-02 16:42:11 +02:00
Ander Conselvan de Oliveira
89b3c3c7ee drm/i915/glk: Reuse broxton's cdclk code for GLK
Geminilake has the same register layout, reference clock and programming
sequence as broxton. The difference is that it doesn't support the 1.5
divider and has different ratios, but a lot of code can be shared
between the two platforms.

v2: Rebase (s/broxton/bxt).

v3: Fix vco calculation in glk_de_pll_vco().

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-7-git-send-email-ander.conselvan.de.oliveira@intel.com
2016-12-02 16:42:00 +02:00
Madhav Chauhan
f7044dd904 drm/i915/glk: Update Port PLL enable sequence for Geminilkae
Add steps for enabling and disabling Port PLL as per bspec.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-6-git-send-email-ander.conselvan.de.oliveira@intel.com
2016-12-02 16:41:47 +02:00
Ander Conselvan de Oliveira
51b3ee35af drm/i915/glk: Set DCC delay range 2 in PLL enable sequence
Follow the PLL enable sequence updated in bspec, which requires the DCC
delay range 2 bit to be set.

v2: Moved from DDI init sequence to PLL enable.
v3: Don't read value from GRP register. (Rodrido)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ander Conselvan De Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-5-git-send-email-ander.conselvan.de.oliveira@intel.com
2016-12-02 16:41:35 +02:00
Ander Conselvan de Oliveira
0a116ce895 drm/i915/glk: Implement Geminilake DDI init sequence
Implement the DDI initsequence and add information about the different
phys in GLK.

v2: Rebase on the move of phys to be power wells.

v3: Rebase on addition of struct bxt_ddi_phy_info.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-4-git-send-email-ander.conselvan.de.oliveira@intel.com
2016-12-02 16:40:49 +02:00
Ander Conselvan de Oliveira
0d03926de5 drm/i915/glk: Add power wells for Geminilake
Geminilake has power wells are similar to SKL, but with the misc IO well
being split into separate AUX IO wells.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-3-git-send-email-ander.conselvan.de.oliveira@intel.com
2016-12-02 16:40:42 +02:00
Ander Conselvan de Oliveira
cc3f90f063 drm/i915/glk: Reuse broxton code for geminilake
Geminilake is mostly backwards compatible with broxton, so change most
of the IS_BROXTON() checks to IS_GEN9_LP(). Differences between the
platforms will be implemented in follow-up patches.

v2: Don't reuse broxton's path in intel_update_max_cdclk().
    Don't set plane count as in broxton.

v3: Rebase

v4: Include the check intel_bios_is_port_hpd_inverted().
    Commit message.

v5: Leave i915_dmc_info() out; glk's csr version != bxt's. (Rodrigo)

v6: Rebase.

v7: Convert a few mode IS_BROXTON() occurances in pps, ddi, dsi and pll
    code. (Rodrigo)

v8: Squash a couple of DDI patches with more conversions. (Rodrigo)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-2-git-send-email-ander.conselvan.de.oliveira@intel.com
2016-12-02 16:38:56 +02:00
Imre Deak
8bf41b7298 drm/i915/gen6+: Clear upper data byte during PCODE write
The spec calls for the upper data byte to be cleared before most of the
PCODE write commands, for others like IPS control it doesn't say
anything about this byte. Let's clear it in case it's clobbered somehow,
especially that there are places where we only do a PCODE write without
a preceding PCODE read.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480346969-16121-1-git-send-email-imre.deak@intel.com
2016-12-02 16:32:44 +02:00
Libin Yang
f55d23be11 drm/i915/audio: extend audio sync rate support for DP MST
Remove the type judgement in i915_audio_component_sync_audio_rate().
Audio rate sync is necessary for all i915 digital audio now.

Signed-off-by: Libin Yang <libin.yang@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480569439-54252-2-git-send-email-libin.yang@intel.com
2016-12-02 16:20:48 +02:00
Libin Yang
31613268c0 drm/i915/audio: extend get_saved_enc() to support more scenarios
In initialization, audio driver will call functions get_eld() and etc.
But at that time, audio driver may not know whether it is DP MST or not.
In the original function get_saved_enc(), if it is DP MST, it requires to
set the pipe to the correct value, otherwise, pipe to be -1.

Although audio driver can get the knowledge whether it is in DP MST mode
or not by reading the codec register. It will drop performance each time
before it calls the get_eld and other similar functions. As gfx driver can
easily know whether it is in DP MST mode or not. Let's extend the
get_saved_enc() function to handle the situation that audio driver
still sends the device id info even it is in DP SST mode and return
the correct intel_encoder instead of panic.

Signed-off-by: Libin Yang <libin.yang@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480569439-54252-1-git-send-email-libin.yang@intel.com
2016-12-02 16:20:37 +02:00
Matthew Auld
a9a251c2ae drm/i915: make i915_suspend_switcheroo static
Looks like this was missed when unexporting, so let's keep sparse happy.

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Fixes: 7f26cb8801 ("drm/i915: Unexport VGA switcheroo functions")
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161202102411.19831-1-matthew.auld@intel.com
2016-12-02 11:26:51 +00:00