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drm/i915/glk: Add power wells for Geminilake
Geminilake has power wells are similar to SKL, but with the misc IO well being split into separate AUX IO wells. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-3-git-send-email-ander.conselvan.de.oliveira@intel.com
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parent
cc3f90f063
commit
0d03926de5
drivers/gpu/drm/i915
@ -1044,9 +1044,15 @@ enum skl_disp_power_wells {
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/* These numbers are fixed and must match the position of the pw bits */
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SKL_DISP_PW_MISC_IO,
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SKL_DISP_PW_DDI_A_E,
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GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
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SKL_DISP_PW_DDI_B,
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SKL_DISP_PW_DDI_C,
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SKL_DISP_PW_DDI_D,
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GLK_DISP_PW_AUX_A = 8,
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GLK_DISP_PW_AUX_B,
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GLK_DISP_PW_AUX_C,
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SKL_DISP_PW_1 = 14,
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SKL_DISP_PW_2,
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@ -453,6 +453,45 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
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BIT(POWER_DOMAIN_AUX_C) | \
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BIT(POWER_DOMAIN_INIT))
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#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_TRANSCODER_A) | \
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BIT(POWER_DOMAIN_PIPE_B) | \
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BIT(POWER_DOMAIN_TRANSCODER_B) | \
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BIT(POWER_DOMAIN_PIPE_C) | \
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BIT(POWER_DOMAIN_TRANSCODER_C) | \
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BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
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BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
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BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
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BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
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BIT(POWER_DOMAIN_AUX_B) | \
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BIT(POWER_DOMAIN_AUX_C) | \
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BIT(POWER_DOMAIN_AUDIO) | \
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BIT(POWER_DOMAIN_VGA) | \
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BIT(POWER_DOMAIN_INIT))
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#define GLK_DISPLAY_DDI_A_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
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BIT(POWER_DOMAIN_INIT))
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#define GLK_DISPLAY_DDI_B_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
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BIT(POWER_DOMAIN_INIT))
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#define GLK_DISPLAY_DDI_C_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
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BIT(POWER_DOMAIN_INIT))
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#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_AUX_A) | \
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BIT(POWER_DOMAIN_INIT))
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#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_AUX_B) | \
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BIT(POWER_DOMAIN_INIT))
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#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \
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BIT(POWER_DOMAIN_AUX_C) | \
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BIT(POWER_DOMAIN_INIT))
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#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
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GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
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BIT(POWER_DOMAIN_MODESET) | \
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BIT(POWER_DOMAIN_AUX_A) | \
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BIT(POWER_DOMAIN_INIT))
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static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
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{
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WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
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@ -694,7 +733,7 @@ gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
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}
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static void skl_set_power_well(struct drm_i915_private *dev_priv,
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struct i915_power_well *power_well, bool enable)
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struct i915_power_well *power_well, bool enable)
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{
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uint32_t tmp, fuse_status;
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uint32_t req_mask, state_mask;
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@ -720,11 +759,14 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
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return;
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}
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break;
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case SKL_DISP_PW_DDI_A_E:
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case SKL_DISP_PW_MISC_IO:
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case SKL_DISP_PW_DDI_A_E: /* GLK_DISP_PW_DDI_A */
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case SKL_DISP_PW_DDI_B:
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case SKL_DISP_PW_DDI_C:
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case SKL_DISP_PW_DDI_D:
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case SKL_DISP_PW_MISC_IO:
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case GLK_DISP_PW_AUX_A:
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case GLK_DISP_PW_AUX_B:
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case GLK_DISP_PW_AUX_C:
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break;
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default:
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WARN(1, "Unknown power well %lu\n", power_well->id);
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@ -2150,6 +2192,70 @@ static struct i915_power_well bxt_power_wells[] = {
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},
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};
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static struct i915_power_well glk_power_wells[] = {
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{
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.name = "always-on",
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.always_on = 1,
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.domains = POWER_DOMAIN_MASK,
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.ops = &i9xx_always_on_power_well_ops,
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},
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{
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.name = "power well 1",
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/* Handled by the DMC firmware */
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.domains = 0,
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.ops = &skl_power_well_ops,
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.id = SKL_DISP_PW_1,
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},
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{
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.name = "DC off",
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.domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
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.ops = &gen9_dc_off_power_well_ops,
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.id = SKL_DISP_PW_DC_OFF,
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},
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{
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.name = "power well 2",
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.domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
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.ops = &skl_power_well_ops,
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.id = SKL_DISP_PW_2,
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},
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{
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.name = "AUX A",
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.domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
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.ops = &skl_power_well_ops,
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.id = GLK_DISP_PW_AUX_A,
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},
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{
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.name = "AUX B",
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.domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
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.ops = &skl_power_well_ops,
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.id = GLK_DISP_PW_AUX_B,
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},
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{
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.name = "AUX C",
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.domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
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.ops = &skl_power_well_ops,
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.id = GLK_DISP_PW_AUX_C,
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},
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{
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.name = "DDI A power well",
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.domains = GLK_DISPLAY_DDI_A_POWER_DOMAINS,
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.ops = &skl_power_well_ops,
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.id = GLK_DISP_PW_DDI_A,
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},
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{
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.name = "DDI B power well",
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.domains = GLK_DISPLAY_DDI_B_POWER_DOMAINS,
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.ops = &skl_power_well_ops,
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.id = SKL_DISP_PW_DDI_B,
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},
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{
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.name = "DDI C power well",
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.domains = GLK_DISPLAY_DDI_C_POWER_DOMAINS,
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.ops = &skl_power_well_ops,
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.id = SKL_DISP_PW_DDI_C,
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},
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};
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static int
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sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
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int disable_power_well)
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@ -2246,6 +2352,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
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set_power_wells(power_domains, skl_power_wells);
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} else if (IS_BROXTON(dev_priv)) {
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set_power_wells(power_domains, bxt_power_wells);
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} else if (IS_GEMINILAKE(dev_priv)) {
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set_power_wells(power_domains, glk_power_wells);
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} else if (IS_CHERRYVIEW(dev_priv)) {
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set_power_wells(power_domains, chv_power_wells);
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} else if (IS_VALLEYVIEW(dev_priv)) {
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