The LS1028A SoC features a PCI Integrated Endpoint Root Complex
(IERC) defining several integrated PCI devices, including the ENETC
ethernet controller integrated endpoints (IEPs). The IERC implements
ECAM (Enhanced Configuration Access Mechanism) to provide access
to the PCIe config space of the IEPs. This means the the IEPs
(including ENETC) do not support the standard PCIe BARs, instead
the Enhanced Allocation (EA) capability structures in the ECAM space
are used to fix the base addresses in the system, and the PCI
subsystem uses these structures for device enumeration and discovery.
The "ranges" entries contain basic information from these EA capabily
structures required by the kernel for device enumeration.
The current patch also enables the first 2 ENETC PFs (Physiscal
Functions) and the associated VFs (Virtual Functions), 2 VFs for
each PF. Each of these ENETC PFs has an external ethernet port
on the LS1028A SoC.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The comments could not reflect the code, and it is easy to get
what this function does from a straight-line reading of the code.
So let's drop the comments
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Debug exception handlers may be called for exceptions generated both by
user and kernel code. In many cases, this is checked explicitly, but
in other cases things either happen to work by happy accident or they
go slightly wrong. For example, executing 'brk #4' from userspace will
enter the kprobes code and be ignored, but the instruction will be
retried forever in userspace instead of delivering a SIGTRAP.
Fix this issue in the most stable-friendly fashion by simply adding
explicit checks of the triggering exception level to all of our debug
exception handlers.
Cc: <stable@vger.kernel.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
FAR_EL1 is UNKNOWN for all debug exceptions other than those caused by
taking a hardware watchpoint. Unfortunately, if a debug handler returns
a non-zero value, then we will propagate the UNKNOWN FAR value to
userspace via the si_addr field of the SIGTRAP siginfo_t.
Instead, let's set si_addr to take on the PC of the faulting instruction,
which we have available in the current pt_regs.
Cc: <stable@vger.kernel.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This reverts commit 0bd3ef34d2.
There is ongoing work on objtool to identify incorrect uses of
user_access_{begin,end}. Until this is sorted, do not enable the
functionality on arm64. Also, on ARMv8.2 CPUs with hardware PAN and UAO
support, there is no obvious performance benefit to the unsafe user
accessors.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Building a preprocessed source file for arm64 now always produces
a warning with clang because of the page_to_virt() macro assigning
a variable to itself.
Adding a new temporary variable avoids this issue.
Fixes: 2813b9c029 ("kasan, mm, arm64: tag non slab memory allocated via pagealloc")
Reviewed-by: Andrey Konovalov <andreyknvl@google.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
When ARCH_MXC get enabled, ARM64_ERRATUM_845719 will be selected and
this warning will happen when COMPAT isn't set.
WARNING: unmet direct dependencies detected for ARM64_ERRATUM_845719
Depends on [n]: COMPAT [=n]
Selected by [y]:
- ARCH_MXC [=y]
Rework to add 'if COMPAT' before ARM64_ERRATUM_845719 gets selected,
since ARM64_ERRATUM_845719 depends on COMPAT.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Anders Roxell <anders.roxell@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Ensure that inX() provides the same ordering guarantees as readX()
by hooking up __io_par() so that it maps directly to __iormb().
Reported-by: Andrew Murray <andrew.murray@arm.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
On the Fujitsu-A64FX cores ver(1.0, 1.1), memory access may cause
an undefined fault (Data abort, DFSC=0b111111). This fault occurs under
a specific hardware condition when a load/store instruction performs an
address translation. Any load/store instruction, except non-fault access
including Armv8 and SVE might cause this undefined fault.
The TCR_ELx.NFD1 bit is used by the kernel when CONFIG_RANDOMIZE_BASE
is enabled to mitigate timing attacks against KASLR where the kernel
address space could be probed using the FFR and suppressed fault on
SVE loads.
Since this erratum causes spurious exceptions, which may corrupt
the exception registers, we clear the TCR_ELx.NFDx=1 bits when
booting on an affected CPU.
Signed-off-by: Zhang Lei <zhang.lei@jp.fujitsu.com>
[Generated MIDR value/mask for __cpu_setup(), removed spurious-fault handler
and always disabled the NFDx bits on affected CPUs]
Signed-off-by: James Morse <james.morse@arm.com>
Tested-by: zhang.lei <zhang.lei@jp.fujitsu.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Another batch of changes for ASoC, no big core changes - it's mainly
small fixes and improvements for individual drivers.
- A big refresh and cleanup of the Samsung drivers, fixing a number of
issues which allow the driver to be used with a wider range of
userspaces.
- Fixes for the Intel drivers to make them more standard so less likely
to get bitten by core issues.
- New driver for Cirrus Logic CS35L26.
-----BEGIN PGP SIGNATURE-----
iQFHBAABCgAxFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAlx3z7ETHGJyb29uaWVA
a2VybmVsLm9yZwAKCRAk1otyXVSH0H5QB/9jwKEwOdk6ynoFUpQwXPPkQl7CGkIh
P8J3OMTt+U4FNOrVG2S7xgUl69ZoaLm9rS/PHVrMV5krSLqY//2CTvF068qDBBlj
haBxgeRbe4pwLZPfFUnWvn6v1rdvNCXzDG/be9jGPJjDcm6wK44VJQWkPbqTsh6O
ZORqvKn48D89W0DegG1B+4jvbietPkhA0+nHQXwsWZ+sfMcEV/AWWsE5FIQ7ucCC
bundBBncUFKMMp9whuhj2W9FO62LUd8OAM7ejis3hfKk9MsQWUy6vrcN1XgRCq47
4I0doB5o+WhsOGMTZMcuhFISCVaCDqbNqGuVbeK0sdonjc1xz0682jLo
=9rq8
-----END PGP SIGNATURE-----
Merge tag 'asoc-v5.1-2' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-next
ASoC: More changes for v5.1
Another batch of changes for ASoC, no big core changes - it's mainly
small fixes and improvements for individual drivers.
- A big refresh and cleanup of the Samsung drivers, fixing a number of
issues which allow the driver to be used with a wider range of
userspaces.
- Fixes for the Intel drivers to make them more standard so less likely
to get bitten by core issues.
- New driver for Cirrus Logic CS35L26.
On big endian arm64 kernels, the xchacha20-neon and xchacha12-neon
self-tests fail because hchacha_block_neon() outputs little endian words
but the C code expects native endianness. Fix it to output the words in
native endianness (which also makes it match the arm32 version).
Fixes: cc7cf991e9 ("crypto: arm64/chacha20 - add XChaCha20 support")
Signed-off-by: Eric Biggers <ebiggers@google.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
The change to encrypt a fifth ChaCha block using scalar instructions
caused the chacha20-neon, xchacha20-neon, and xchacha12-neon self-tests
to start failing on big endian arm64 kernels. The bug is that the
keystream block produced in 32-bit scalar registers is directly XOR'd
with the data words, which are loaded and stored in native endianness.
Thus in big endian mode the data bytes end up XOR'd with the wrong
bytes. Fix it by byte-swapping the keystream words in big endian mode.
Fixes: 2fe55987b2 ("crypto: arm64/chacha - use combined SIMD/ALU routine for more speed")
Signed-off-by: Eric Biggers <ebiggers@google.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This is a follow-up to the y2038 syscall patches already merged in the tip
tree. As the final 32-bit RISC-V syscall ABI is still being decided on,
this is the last chance to make a few corrections to leave out interfaces
based on 32-bit time_t along with the old off_t and rlimit types.
The series achieves this in a few steps:
- A couple of bug fixes for minor regressions I introduced
in the original series
- A couple of older patches from Yury Norov that I had never
merged in the past, these fix up the openat/open_by_handle_at and
getrlimit/setrlimit syscalls to disallow the old versions of off_t
and rlimit.
- Hiding the deprecated system calls behind an #ifdef in
include/uapi/asm-generic/unistd.h
- Change arch/riscv to drop all these ABIs.
Originally, the plan was to also leave these out on C-Sky, but that now
has a glibc port that uses the older interfaces, so we need to leave
them in place.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJcdEhGAAoJEGCrR//JCVInQuUQAN+mRFzRXAqhbpb63/vYGJei
nmDqB+SoxzaIKAIGAVIdMGUoFxBrY1oyS4m6/a9lzQ9G4aSkr0PruZnUID+vIo2h
rj+3FBlB/c9nvW+NG8iEtVadlRbTmoRILCWpvgIuLNd6fwvNzP3V4uu6a1QRIMx4
aUCWQfhzv18kW1EAPIroPA1gEL2HKbhDdEuN2V0SKnsKNiWkHQeswWQFAYpLgT36
eZ+L52lh+miEdtBxycxJ5lh3KsWO4dPImh+QHONZgeB9iS8v47K0R6ONKm4NMeQV
5KW55pepUq1uQUdEU9KRrh2krMih2IJbOQoN2lvb2ao5UG6erHbj0N55RQym5gSC
+TrvP3dnqfohh9hWdHDwME+5OTeOM+8SUMRnaZBJKuywzo7W1ceLpf+KZjwlk2s5
AgEX67fKrUbtBfTgVhzlYhJLWcgSD1yt64ed5SF15c5M3JZhkK8cd50dB9pM2/YB
o9VbijkYwb2KyCNUiV3nghgiiqcROvOIO7PK6z3XFFiRm/Gn2CgNZyZa7c4+Vgrr
PM/DmDvCdFqYnqBOlV2ilCLigKGN0JgwzMXnbQU77d71Yg7Bco8e/yqSucSilp2d
lEv44extu9FINWXIqvWEjRqdSq+sNgj21VSp6Zu/GaTgNCQKac2wsAZtnQgnslko
knKwwp525fjqnJEDd1aH
=/iFA
-----END PGP SIGNATURE-----
Merge tag 'y2038-syscall-abi' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/playground into timers/2038
Pull additional syscall ABI cleanup for y2038 from Arnd Bergmann:
This is a follow-up to the y2038 syscall patches already merged in the tip
tree. As the final 32-bit RISC-V syscall ABI is still being decided on,
this is the last chance to make a few corrections to leave out interfaces
based on 32-bit time_t along with the old off_t and rlimit types.
The series achieves this in a few steps:
- A couple of bug fixes for minor regressions I introduced
in the original series
- A couple of older patches from Yury Norov that I had never
merged in the past, these fix up the openat/open_by_handle_at and
getrlimit/setrlimit syscalls to disallow the old versions of off_t
and rlimit.
- Hiding the deprecated system calls behind an #ifdef in
include/uapi/asm-generic/unistd.h
- Change arch/riscv to drop all these ABIs.
Originally, the plan was to also leave these out on C-Sky, but that now
has a glibc port that uses the older interfaces, so we need to leave
them in place.
Currently, we don't coordinate BT USB activity with our handling of the
BT out-of-band wake pin, and instead just use gpio-keys. That causes
problems because we have no way of distinguishing wake activity due to a
BT device (e.g., mouse) vs. the BT controller (e.g., re-configuring wake
mask before suspend). This can cause spurious wake events just because
we, for instance, try to reconfigure the host controller's event mask
before suspending.
We can avoid these synchronization problems by handling the BT wake pin
directly in the btusb driver -- for all activity up until BT controller
suspend(), we simply listen to normal USB activity (e.g., to know the
difference between device and host activity); once we're really ready to
suspend the host controller, there should be no more host activity, and
only *then* do we unmask the GPIO interrupt.
This is already supported by btusb; we just need to describe the wake
pin in the right node.
We list 2 compatible properties, since both PID/VID pairs show up on
Scarlet devices, and they're both essentially identical QCA6174A-based
modules.
Also note that the polarity was wrong before: Qualcomm implemented WAKE
as active high, not active low. We only got away with this because
gpio-keys always reconfigured us as bi-directional edge-triggered.
Finally, we have an external pull-up and a level-shifter on this line
(we didn't notice Qualcomm's polarity in the initial design), so we
can't do pull-down. Switch to pull-none.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
My console locks up as soon as Linux writes to [88800000,88f00000[
AFAIU, that memory area is reserved for trustzone.
Extend TZ reserved memory range, to prevent Linux from stepping on
trustzone's toes.
Cc: stable@vger.kernel.org # 4.20+
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
Fixes: c783394956 ("arm64: dts: qcom: msm8998: Add smem related nodes")
Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The assembly macro get_thread_info() actually returns a task_struct and is
analogous to the current/get_current macro/function.
While it could be argued that thread_info sits at the start of
task_struct and the intention could have been to return a thread_info,
instances of loads from/stores to the address obtained from
get_thread_info() use offsets that are generated with
offsetof(struct task_struct, [...]).
Rename get_thread_info() to state it returns a task_struct.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Julien Thierry <julien.thierry@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
TIF_USEDFPU is not defined as thread flags for Arm64. So drop it from
the documentation.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Julien Grall <julien.grall@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Three conflicts, one of which, for marvell10g.c is non-trivial and
requires some follow-up from Heiner or someone else.
The issue is that Heiner converted the marvell10g driver over to
use the generic c45 code as much as possible.
However, in 'net' a bug fix appeared which makes sure that a new
local mask (MDIO_AN_10GBT_CTRL_ADV_NBT_MASK) with value 0x01e0
is cleared.
Signed-off-by: David S. Miller <davem@davemloft.net>
Only a handful of device tree fixes, all simple enough:
NVIDIA Tegra:
- Fix a regression for booting on chromebooks
TI OMAP:
- Two fixes PHY mode on am335x reference boards
Marvell mvebu:
- A regression fix for Armada XP NAND flash controllers
- An incorrect reset signal on the clearfog board
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJccHWeAAoJEGCrR//JCVInLQAQAIKQEEQXxPn1fnXH5oH7n/Yn
aALv0zoRKx5ybgQvp15hkdD/H7AUt01ADopCvgOxh0EkheIOEZdtb/FCaRPzaYhC
TrrZhqI6+w0rcMwUzpaDU+90/rxkh6oeIs95lfTkHaZV0ZdbWqwwvX/JuQcPJOh2
tQXwfNMv4WZetvAFrJHr9L+7/CebgQaOe/Me78wq/bjKEROShaF6j6lQMTeZwX6C
Jp75cI5gCktqg4ZDQ2NEE8O9Tng4uzIpoVlCptFc38XGKnRZMexZZlZWpMwTeQg1
QmNmyTal6gbY5tDs3AGg3diSPFQ1nwUiMk2pWvGkkRo5hkNP80lNCouu8F99r/Ub
QoPRcKzGyBwLj0MwpHBoO5gI1X4mgfZDpL71SdS81p8q3rpnt/W2HU+CTAgnEpAi
aILCMmRzes3jpNHREUQc5X3dTwfHW8MBW/Bia6XnidqmUw5GoRq+98rCOKFpg2HQ
m68yDZlOq2odATmaa4xASVfTwccm8jIyQwZVWFPLyekZ9kzMcdYmAI7lGGofJAbg
SkRXDHsAQ21pDoUZY3C0lE49kPKoTNrt4bsihG0I3hM09moF6ryqmymgAy82mzsD
e/ZVG2w1E0CS4vKjKq7BEof3PZ6wSdfaYOFzS7v9bXAeBSdRVE/qjzi/aBgAKD8J
KpDRnh2huOMvPTO5bDKC
=nXrB
-----END PGP SIGNATURE-----
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC fixes from Arnd Bergmann:
"Only a handful of device tree fixes, all simple enough:
NVIDIA Tegra:
- Fix a regression for booting on chromebooks
TI OMAP:
- Two fixes PHY mode on am335x reference boards
Marvell mvebu:
- A regression fix for Armada XP NAND flash controllers
- An incorrect reset signal on the clearfog board"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
ARM: tegra: Restore DT ABI on Tegra124 Chromebooks
ARM: dts: am335x-evm: Fix PHY mode for ethernet
ARM: dts: am335x-evmsk: Fix PHY mode for ethernet
arm64: dts: clearfog-gt-8k: fix SGMII PHY reset signal
ARM: dts: armada-xp: fix Armada XP boards NAND description
- A number of pre-nested code rework
- Direct physical timer assignment on VHE systems
- kvm_call_hyp type safety enforcement
- Set/Way cache sanitisation for 32bit guests
- Build system cleanups
- A bunch of janitorial fixes
-----BEGIN PGP SIGNATURE-----
iQJJBAABCgAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAlxwH3EVHG1hcmMuenlu
Z2llckBhcm0uY29tAAoJECPQ0LrRPXpD9j4P/i1lIUKfg/bxGw46wwoqF1MjOEPD
uDQ6irms65FfqFkUkIPaU1du51UcI9nwncUPeJh+E3g2wp2f5EXsAp7tksARfIWU
YCLLez5AiuYH6Otrs7YxLm8L/Sqqc3DacGWuyOamXmdWM9wZlv7F295Yfo5nX8zk
IhksfBQH4/KvOPxkzbY6yy1StKOreuXQuboecrcfUP0lxwaUcbqxHMuynP7DneCv
EHNo5TUjK975xH4jS/K61Ji9FmTlA/PgGqgn+EOw5KXGnKlphFBaTrzuE7vPLveR
XPV1VeNEuEitH/+qVhZr8k2Du+3kKqQA8Ikxv6SasYAnqyVFTPPPMtUEgZXTLpHa
6D4kIc+5jxgxF6Dyk3PKnjoNHPolCApj/uPCcTiD8dyY4smpJQ3+gxGiJkX68e92
EkJlBj0Hn4xgudHi9UWLP+eZHT+v3L8mvVLP9N9oqapwc0x4g9YqJVbJMyAnT5Pw
pLPSKTx9ApmyAEkdzRHjB89gG5cwjUzmx5BF7gASYSmTS9el9r5Kaaxx8zCmMt1R
gM1TF7rBrgyW5s+bsIBf2rqk+5WAxag+FmeCQwghuNc+uhNfboRgoJzx7qFTpxeX
KFS86QmQPRMWGR0klXgW1+hNOD8ACnqCOPGB+3d41ql3bgQ0otLItvj4RoA44JYG
0Guq7o9EZNUYqDzA
=iEs0
-----END PGP SIGNATURE-----
Merge tag 'kvmarm-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into kvm-next
KVM/arm updates for Linux v5.1
- A number of pre-nested code rework
- Direct physical timer assignment on VHE systems
- kvm_call_hyp type safety enforcement
- Set/Way cache sanitisation for 32bit guests
- Build system cleanups
- A bunch of janitorial fixes
Fix PHY reset signal on clearfog gt 8K (Armada 8040 based)
Fix NAND description on Armada XP boards which was broken since a few
release
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCXG/EtQAKCRALBhiOFHI7
1VPDAJ9DSFQaCmlSRwC/jO1HvchB+y9sxACcDQioH28bCYQt3SYp7K87D1ow8wE=
=b5Ed
-----END PGP SIGNATURE-----
Merge tag 'mvebu-fixes-5.0-2' of git://git.infradead.org/linux-mvebu into arm/fixes
mvebu fixes for 5.0 (part 2)
Fix PHY reset signal on clearfog gt 8K (Armada 8040 based)
Fix NAND description on Armada XP boards which was broken since a few
release
* tag 'mvebu-fixes-5.0-2' of git://git.infradead.org/linux-mvebu:
arm64: dts: clearfog-gt-8k: fix SGMII PHY reset signal
ARM: dts: armada-xp: fix Armada XP boards NAND description
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Due to what looks like a typo dating back to the original addition
of FPEXC32_EL2 handling, KVM currently initialises this register to
an architecturally invalid value.
As a result, the VECITR field (RES1) in bits [10:8] is initialised
with 0, and the two reserved (RES0) bits [6:5] are initialised with
1. (In the Common VFP Subarchitecture as specified by ARMv7-A,
these two bits were IMP DEF. ARMv8-A removes them.)
This patch changes the reset value from 0x70 to 0x700, which
reflects the architectural constraints and is presumably what was
originally intended.
Cc: <stable@vger.kernel.org> # 4.12.x-
Cc: Christoffer Dall <christoffer.dall@arm.com>
Fixes: 62a89c4495 ("arm64: KVM: 32bit handling of coprocessor traps")
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
"nvidia,model" property is added to pass custom name for hda sound card.
This is parsed in hda driver and used for card name. This aligns with the
way with which sound cards are named in general.
This patch populates above for jetson-tx1, jetson-tx2 and jetson-xavier.
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Make the arm64 ctr-aes-neon and ctr-aes-ce algorithms update the IV
buffer to contain the next counter after processing a partial final
block, rather than leave it as the last counter. This makes these
algorithms pass the updated AES-CTR tests.
Signed-off-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
- Fix handling of PSTATE.SSBS bit in sigreturn()
- Fix version checking of the GIC during early boot
- Fix clang builds failing due to use of NEON in the crypto code
-----BEGIN PGP SIGNATURE-----
iQEzBAABCgAdFiEEPxTL6PPUbjXGY88ct6xw3ITBYzQFAlxtk30ACgkQt6xw3ITB
YzSGygf/U9P//TbPwGP2ZrCLHelJ8okYMZgJB3R/MLpGrV/MPWbN39JNMydXUPNT
Kn21TzQeYnGp4blIC5S8RQMJnrqbR03L4ch6DVrFWGJZVkfI3WFefASHUe+Hg/WB
d8GCkiqIMO+qX9+o6e+kPts3bgGsGvYEQF0vvdX6DbNXVkqusJ6TSIEAgEYUQH97
NzIqEfu6xYgmjultmMemfstaWaHI5Mfwx0fSdFhVfCDYKfoAj3U7LDRT9NFEAkTc
cxxZ3Z/BnJYPOhoqboIceZz499g++1SnISTEIIrGHKa51tK/Nuunaarsr1ZbB4gz
BLQhrJxbxxtbdkfDGA7u2mSQupCRbA==
=ujCB
-----END PGP SIGNATURE-----
Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull late arm64 fixes from Will Deacon:
"Three small arm64 fixes for 5.0.
They fix a build breakage with clang introduced in 4.20, an oversight
in our sigframe restoration relating to the SSBS bit and a boot fix
for systems with newer revisions of our interrupt controller.
Summary:
- Fix handling of PSTATE.SSBS bit in sigreturn()
- Fix version checking of the GIC during early boot
- Fix clang builds failing due to use of NEON in the crypto code"
* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: Relax GIC version check during early boot
arm64/neon: Disable -Wincompatible-pointer-types when building with Clang
arm64: fix SSBS sanitization
There are two issues with assigning random percpu seeds right now:
1. We use for_each_possible_cpu() to iterate over cpus, but cpumask is
not set up yet at the moment of kasan_init(), and thus we only set
the seed for cpu #0.
2. A call to get_random_u32() always returns the same number and produces
a message in dmesg, since the random subsystem is not yet initialized.
Fix 1 by calling kasan_init_tags() after cpumask is set up.
Fix 2 by using get_cycles() instead of get_random_u32(). This gives us
lower quality random numbers, but it's good enough, as KASAN is meant to
be used as a debugging tool and not a mitigation.
Link: http://lkml.kernel.org/r/1f815cc914b61f3516ed4cc9bfd9eeca9bd5d9de.1550677973.git.andreyknvl@google.com
Signed-off-by: Andrey Konovalov <andreyknvl@google.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Andrey Ryabinin <aryabinin@virtuozzo.com>
Cc: Alexander Potapenko <glider@google.com>
Cc: Dmitry Vyukov <dvyukov@google.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Add the PCIE EP node in dts for ls1046a.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <minghuan.lian@nxp.com>
Reviewed-by: Zhiqiang Hou <zhiqiang.hou@nxp.com>
Reviewed-by: Rob Herring <robh+dt@kernel.org>
- Add interrupt properties to S900 pinctrl node
- Add Reset controller support for S700
- Add Reset controller support for S900
- Add pinctrl support for S700
- Add I2C support for S700
- Enable I2C0 and I2C1 for s700-cubieboard7
-----BEGIN PGP SIGNATURE-----
iQEzBAABCgAdFiEEZ6VDKoFIy9ikWCeXVZ8R5v6RzvUFAlxnwSoACgkQVZ8R5v6R
zvXpeAf+NwhGUPtKeKeXOct24HqHVwvdbyBajcqcsUYsGXTxaIH7uGEupITAkxAj
6kLOpmW3WDpMr2yBHSS5oEnityD2VKCL1BLP9TE7Plj56QsWucWlWsY2xhG1828+
eT1pbSPECg7lRZnAOMj+B6EqtEcZzaoxlRdRLw6rJmb4+H5aJ80VT3pIpYI+sjR9
5wnuaWSE2nxJoICm1dL1CeVPfT9iNluYSxerO13tkF9/lj7bQpeRI85OMvpUVo5Z
iQ6OGJ6sc4Ynn0Z9F7hdBOb6tB8Z3ampXu8IMiXir1d+RG/uGNlhsQyGsgXGZ++Y
uQQR4as0k+vYYscRR2J0sLhhBT4h2w==
=EHRP
-----END PGP SIGNATURE-----
Merge tag 'actions-arm64-dt-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-actions into arm/dt
Actions ARM64 DT changes for v5.1:
- Add interrupt properties to S900 pinctrl node
- Add Reset controller support for S700
- Add Reset controller support for S900
- Add pinctrl support for S700
- Add I2C support for S700
- Enable I2C0 and I2C1 for s700-cubieboard7
* tag 'actions-arm64-dt-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-actions:
arm64: dts: actions: s700-cubieboard7: Enable I2C0 and I2C1
arm64: dts: actions: s700: Add I2C controller nodes
arm64: dts: actions: Add pinctrl node for Actions Semi S700
arm64: dts: actions: Add Reset Controller support for S900 SoC
arm64: dts: actions: Add Reset Controller support for S700 SoC
arm64: dts: actions: Add interrupt properties to pinctrl node for S900
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This API is primarily used through DT entries, but two architectures
and two drivers call it directly. So instead of selecting the config
symbol for random architectures pull it in implicitly for the actual
users. Also rename the Kconfig option to describe the feature better.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Paul Burton <paul.burton@mips.com> # MIPS
Acked-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Updates to the GIC architecture allow ID_AA64PFR0_EL1.GIC to have
values other than 0 or 1. At the moment, Linux is quite strict in the
way it handles this field at early boot stage (cpufeature is fine) and
will refuse to use the system register CPU interface if it doesn't
find the value 1.
Fixes: 021f653791 ("irqchip: gic-v3: Initial support for GICv3")
Reported-by: Chase Conklin <Chase.Conklin@arm.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Since Suzuki K Poulose's work on Dynamic IPA support, KVM_PHYS_SHIFT will
be used only when machine_type's bits[7:0] equal to 0 (by default). Thus
the outdated comment should be fixed.
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Currently, the Kbuild core manipulates header search paths in a crazy
way [1].
To fix this mess, I want all Makefiles to add explicit $(srctree)/ to
the search paths in the srctree. Some Makefiles are already written in
that way, but not all. The goal of this work is to make the notation
consistent, and finally get rid of the gross hacks.
Having whitespaces after -I does not matter since commit 48f6e3cf5b
("kbuild: do not drop -I without parameter").
[1]: https://patchwork.kernel.org/patch/9632347/
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
The header search path -I. in kernel Makefiles is very suspicious;
it allows the compiler to search for headers in the top of $(srctree),
where obviously no header file exists.
I was able to build without these extra header search paths.
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
On SMP ARM systems, cache maintenance by set/way should only ever be
done in the context of onlining or offlining CPUs, which is typically
done by bare metal firmware and never in a virtual machine. For this
reason, we trap set/way cache maintenance operations and replace them
with conditional flushing of the entire guest address space.
Due to this trapping, the set/way arguments passed into the set/way
ops are completely ignored, and thus irrelevant. This also means that
the set/way geometry is equally irrelevant, and we can simply report
it as 1 set and 1 way, so that legacy 32-bit ARM system software (i.e.,
the kind that only receives odd fixes) doesn't take a performance hit
due to the trapping when iterating over the cachelines.
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
We currently permit CPUs in the same system to deviate in the exact
topology of the caches, and we subsequently hide this fact from user
space by exposing a sanitised value of the cache type register CTR_EL0.
However, guests running under KVM see the bare value of CTR_EL0, which
could potentially result in issues with, e.g., JITs or other pieces of
code that are sensitive to misreported cache line sizes.
So let's start trapping cache ID instructions if there is a mismatch,
and expose the sanitised version of CTR_EL0 to guests. Note that CTR_EL0
is treated as an invariant to KVM user space, so update that part as well.
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Move this little function to the header files for arm/arm64 so other
code can make use of it directly.
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
At the moment we have separate system register emulation handlers for
each timer register. Actually they are quite similar, and we rely on
kvm_arm_timer_[gs]et_reg() for the actual emulation anyways, so let's
just merge all of those handlers into one function, which just marshalls
the arguments and then hands off to a set of common accessors.
This makes extending the emulation to include EL2 timers much easier.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[Fixed 32-bit VM breakage and reduced to reworking existing code]
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
[Fixed 32bit host, general cleanup]
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Instead of having an open-coded macro, reuse the sys_reg() macro
that does the exact same thing (the encoding is slightly different,
but the ordering property is the same).
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
We previously incorrectly named the define for this system register.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
In preparation for nested virtualization where we are going to have more
than a single VMID per VM, let's factor out the VMID data into a
separate VMID data structure and change the VMID allocator to operate on
this new structure instead of using a struct kvm.
This also means that udate_vttbr now becomes update_vmid, and that the
vttbr itself is generated on the fly based on the stage 2 page table
base address and the vmid.
We cache the physical address of the pgd when allocating the pgd to
avoid doing the calculation on every entry to the guest and to avoid
calling into potentially non-hyp-mapped code from hyp/EL2.
If we wanted to merge the VMID allocator with the arm64 ASID allocator
at some point in the future, it should actually become easier to do that
after this patch.
Note that to avoid mapping the kvm_vmid_bits variable into hyp, we
simply forego the masking of the vmid value in kvm_get_vttbr and rely on
update_vmid to always assign a valid vmid value (within the supported
range).
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
[maz: minor cleanups]
Reviewed-by: Julien Thierry <julien.thierry@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
We currently eagerly save/restore MPIDR. It turns out to be
slightly pointless:
- On the host, this value is known as soon as we're scheduled on a
physical CPU
- In the guest, this value cannot change, as it is set by KVM
(and this is a read-only register)
The result of the above is that we can perfectly avoid the eager
saving of MPIDR_EL1, and only keep the restore. We just have
to setup the host contexts appropriately at boot time.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
We now call VHE code directly, without going through any central
dispatching function. Let's drop that code.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
When running VHE, there is no need to jump via some stub to perform
a "HYP" function call, as there is a single address space.
Let's thus change kvm_call_hyp() and co to perform a direct call
in this case. Although this results in a bit of code expansion,
it allows the compiler to check for type compatibility, something
that we are missing so far.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
Until now, we haven't differentiated between HYP calls that
have a return value and those who don't. As we're about to
change this, introduce kvm_call_hyp_ret(), and change all
call sites that actually make use of a return value.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
We don't want new architectures to even provide the old 32-bit time_t
based system calls any more, or define the syscall number macros.
Add a new __ARCH_WANT_TIME32_SYSCALLS macro that gets enabled for all
existing 32-bit architectures using the generic system call table,
so we don't change any current behavior.
Since this symbol is evaluated in user space as well, we cannot use
a Kconfig CONFIG_* macro but have to define it in uapi/asm/unistd.h.
On 64-bit architectures, the same system call numbers mostly refer to
the system calls we want to keep, as they already pass 64-bit time_t.
As new architectures no longer provide these, we need new exceptions
in checksyscalls.sh.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The newer prlimit64 syscall provides all the functionality of getrlimit
and setrlimit syscalls and adds the pid of target process, so future
architectures won't need to include getrlimit and setrlimit.
Therefore drop getrlimit and setrlimit syscalls from the generic syscall
list unless __ARCH_WANT_SET_GET_RLIMIT is defined by the architecture's
unistd.h prior to including asm-generic/unistd.h, and adjust all
architectures using the generic syscall list to define it so that no
in-tree architectures are affected.
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: linux-arch@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-hexagon@vger.kernel.org
Cc: uclinux-h8-devel@lists.sourceforge.jp
Signed-off-by: Yury Norov <ynorov@caviumnetworks.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Mark Salter <msalter@redhat.com> [c6x]
Acked-by: James Hogan <james.hogan@imgtec.com> [metag]
Acked-by: Ley Foon Tan <lftan@altera.com> [nios2]
Acked-by: Stafford Horne <shorne@gmail.com> [openrisc]
Acked-by: Will Deacon <will.deacon@arm.com> [arm64]
Acked-by: Vineet Gupta <vgupta@synopsys.com> #arch/arc bits
Signed-off-by: Yury Norov <ynorov@marvell.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
After commit cc9f8349cb ("arm64: crypto: add NEON accelerated XOR
implementation"), Clang builds for arm64 started failing with the
following error message.
arch/arm64/lib/xor-neon.c:58:28: error: incompatible pointer types
assigning to 'const unsigned long *' from 'uint64_t *' (aka 'unsigned
long long *') [-Werror,-Wincompatible-pointer-types]
v3 = veorq_u64(vld1q_u64(dp1 + 6), vld1q_u64(dp2 + 6));
^~~~~~~~
/usr/lib/llvm-9/lib/clang/9.0.0/include/arm_neon.h:7538:47: note:
expanded from macro 'vld1q_u64'
__ret = (uint64x2_t) __builtin_neon_vld1q_v(__p0, 51); \
^~~~
There has been quite a bit of debate and triage that has gone into
figuring out what the proper fix is, viewable at the link below, which
is still ongoing. Ard suggested disabling this warning with Clang with a
pragma so no neon code will have this type of error. While this is not
at all an ideal solution, this build error is the only thing preventing
KernelCI from having successful arm64 defconfig and allmodconfig builds
on linux-next. Getting continuous integration running is more important
so new warnings/errors or boot failures can be caught and fixed quickly.
Link: https://github.com/ClangBuiltLinux/linux/issues/283
Suggested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
In valid_user_regs() we treat SSBS as a RES0 bit, and consequently it is
unexpectedly cleared when we restore a sigframe or fiddle with GPRs via
ptrace.
This patch fixes valid_user_regs() to account for this, updating the
function to refer to the latest ARM ARM (ARM DDI 0487D.a). For AArch32
tasks, SSBS appears in bit 23 of SPSR_EL1, matching its position in the
AArch32-native PSR format, and we don't need to translate it as we have
to for DIT.
There are no other bit assignments that we need to account for today.
As the recent documentation describes the DIT bit, we can drop our
comment regarding DIT.
While removing SSBS from the RES0 masks, existing inconsistent
whitespace is corrected.
Fixes: d71be2b6c0 ("arm64: cpufeature: Detect SSBS and advertise to userspace")
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Add charger device node and related battery node for SC2731 PMIC.
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch adds phandles to the calibration cells provided by the Efuse
device, which is used to calibrate the ADC channel scales.
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The Spreadtrum PMIC INTC controller has no registers to set trigger type,
since it is always high level trigger as default. So remove its child
devices' irq trigger type setting and change #interrupt-cells to 1.
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable the thermal sensor. This device also provides
temperature shutdown protection. The shutdown value is
set at 110C, as tested by the vendor.
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
- support for a new variant of pca953x
- documentation fix from Wolfram
- some tegra186 name changes
- two minor fixes for madera and altera-a10sr
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEFp3rbAvDxGAT0sefEacuoBRx13IFAlxleLcACgkQEacuoBRx
13I45Q//YMGUYzkMjOL+lp2DYnnVhVNqrF4hoLjinWVrnhZ6gqu88RgV2Cea4Pta
oxVxnSsE8LK7kY8VZ8tcBmIqLLkQAJdSVtqkeSoZF2vhWBAbE9ZaSOYb17SIkSXK
Ok16lZgZ+ZWOM5EjEvuRpB/qYGjX2glD5/Y2Kl7+wsX1W6U2pXasP0IjhcvDU8mJ
NXNgfkr6kluMUqHJyqKo8eT/P3Hdv0CK9GsN2vGyfJenCdTSd7EC6KuhWAivi+fG
/lf1bVuc2cCiXjxdSOXx+Yz7SjNe56viTaqnn/K6OlfLgErjKnRW+AxPkTZXNtDi
pfMMpPXiwPcbQR2wrXG/7OMmJ1kUsfWoIUCx5RDwhF1KbEQVqgaSITLylk+4Yp/3
eM0fYsQ+KvOdAnWKSgfxBhaaiO7z5XDdrnkSHBDoiBrm07BqBgK/v3Rivzf2GMEv
QvM4OBfThS9I8skV5BaOBRDfHZs4N0EU/vhsW9gt50urtlSM0vSYx6kdMq/8R0k4
NkJT43u+1vi5koMljBAsZYZiyXOQ2B+PlfpTMfMu+93QH8wlu9mOt1r3YTQyA1Xf
jiOK8M2yQKP5g7RuPM6MtMsqlZKDM5nAlSf7S280Z3+vBd+LaELbXvT2/JL5ViGU
hfH/gaNwUGUYd8EsWvfhHVdPAAecDCwxfKyKEnFGhMrtunTgwfI=
=nV64
-----END PGP SIGNATURE-----
Merge tag 'gpio-v5.1-updates-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into devel
gpio updates for v5.1
- support for a new variant of pca953x
- documentation fix from Wolfram
- some tegra186 name changes
- two minor fixes for madera and altera-a10sr
Pull EFI fixes from Ingo Molnar:
"This tree reverts a GICv3 commit (which was broken) and fixes it in
another way, by adding a memblock build-time entries quirk for ARM64"
* 'efi-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
efi/arm: Revert "Defer persistent reservations until after paging_init()"
arm64, mm, efi: Account for GICv3 LPI tables in static memblock reserve table
of x86 bug fixes.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQEcBAABAgAGBQJcaQI4AAoJEL/70l94x66DOPwH/0d7JDl2Qr3+1B20hv2++35C
RyG8bMayJq0AATRcjuaFXKiKikZ3NyMHHxaLRwhtcZggU+2FlykEwIKIHvv3L9bj
Rs/YNtIRI21qDSFtOmKnAYnSm10QkngJw7sd5ExHnMTiuCoca3f8EjKnatFgMlzv
UMdMTe9UaMGAl9IKveW56xneR1MDYFG8x69Uu9Si7LkIdMgEAstuJGcTQAt9TzO/
AvbckcN9MKfVCjwvnzsTMaKQMttSHHpOh50gaLlAzPubqfVaqTkSmCvN22+UAk/H
t248x3bHOCO1u1HdHC/sxf8z6HIOFD692eBRmrm5LjBsUFdktUPj7q0U8r9MEK4=
=oHHm
-----END PGP SIGNATURE-----
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull KVM fixes from Paolo Bonzini:
"A somewhat bigger ARM update, and the usual smattering of x86 bug
fixes"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
kvm: vmx: Fix entry number check for add_atomic_switch_msr()
KVM: x86: Recompute PID.ON when clearing PID.SN
KVM: nVMX: Restore a preemption timer consistency check
x86/kvm/nVMX: read from MSR_IA32_VMX_PROCBASED_CTLS2 only when it is available
KVM: arm64: Forbid kprobing of the VHE world-switch code
KVM: arm64: Relax the restriction on using stage2 PUD huge mapping
arm: KVM: Add missing kvm_stage2_has_pmd() helper
KVM: arm/arm64: vgic: Always initialize the group of private IRQs
arm/arm64: KVM: Don't panic on failure to properly reset system registers
arm/arm64: KVM: Allow a VCPU to fully reset itself
KVM: arm/arm64: Reset the VCPU without preemption and vcpu state loaded
arm64: KVM: Don't generate UNDEF when LORegion feature is present
KVM: arm/arm64: vgic: Make vgic_cpu->ap_list_lock a raw_spinlock
KVM: arm/arm64: vgic: Make vgic_dist->lpi_list_lock a raw_spinlock
KVM: arm/arm64: vgic: Make vgic_irq->irq_lock a raw_spinlock
This reverts commit eff8962888, which
deferred the processing of persistent memory reservations to a point
where the memory may have already been allocated and overwritten,
defeating the purpose.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mike Rapoport <rppt@linux.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-efi@vger.kernel.org
Link: http://lkml.kernel.org/r/20190215123333.21209-3-ard.biesheuvel@linaro.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
In the irqchip and EFI code, we have what basically amounts to a quirk
to work around a peculiarity in the GICv3 architecture, which permits
the system memory address of LPI tables to be programmable only once
after a CPU reset. This means kexec kernels must use the same memory
as the first kernel, and thus ensure that this memory has not been
given out for other purposes by the time the ITS init code runs, which
is not very early for secondary CPUs.
On systems with many CPUs, these reservations could overflow the
memblock reservation table, and this was addressed in commit:
eff8962888 ("efi/arm: Defer persistent reservations until after paging_init()")
However, this turns out to have made things worse, since the allocation
of page tables and heap space for the resized memblock reservation table
itself may overwrite the regions we are attempting to reserve, which may
cause all kinds of corruption, also considering that the ITS will still
be poking bits into that memory in response to incoming MSIs.
So instead, let's grow the static memblock reservation table on such
systems so it can accommodate these reservations at an earlier time.
This will permit us to revert the above commit in a subsequent patch.
[ mingo: Minor cleanups. ]
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Mike Rapoport <rppt@linux.ibm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-efi@vger.kernel.org
Link: http://lkml.kernel.org/r/20190215123333.21209-2-ard.biesheuvel@linaro.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
The netfilter conflicts were rather simple overlapping
changes.
However, the cls_tcindex.c stuff was a bit more complex.
On the 'net' side, Cong is fixing several races and memory
leaks. Whilst on the 'net-next' side we have Vlad adding
the rtnl-ness support.
What I've decided to do, in order to resolve this, is revert the
conversion over to using a workqueue that Cong did, bringing us back
to pure RCU. I did it this way because I believe that either Cong's
races don't apply with have Vlad did things, or Cong will have to
implement the race fix slightly differently.
Signed-off-by: David S. Miller <davem@davemloft.net>
* Add MSM8998 RPMCC, I2C, and USB related nodes
* Add MSM8996 rpmpd node
* Fix typo in MSM8996 pin definitions
* Disable MSM8996 VFE smmu to fix security violation
* Add I2C, SPI, rpmcc, uart, and WCN3990 wlan nodes on QCS404
* Enable SDCC1 HS400 support on QCS404
* Add a multitude of nodes on SDM845:
SD, UFS, USB, LPASS, SCM, QSPI, PDC, DPU, videocc, GPU, RPMh
bus interconnect, WCN3990 WLAN
* Add gpio ranges to SDM845 TLMM
* Fix regulator load on sdcard on MSM8998-mtp board
* Add thermal trip points to cpufreq
* Add SDM845 IOMMU info for SDHC, USB, and WLAN
* Fix MSM8916 clock cell argument
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJcZxDLAAoJEFKiBbHx2RXVWGgP/080wwgcj0gJP31orLypfSJa
9UYndhjdEVpomP3YOKNCUMyGO5MtQAIPXF3yPO30UER4mUsjDYmtZhlhIGPHDy3w
1ZAjIKPBb/9ujz3+/A4VHTVnySdgAdGDhUfXsae8cu+/55GGcbspbvev0Mt81QXm
n5Wk0rI2LDJsVKoV5PVV/YuWZgf7cycvW7b3kGKDD9mckbJ4IJZqXOQ+3sd8Gal+
RSS3l82ndKTJ8fugHxCroxAbS0CqPESqd8X/nopNdM3z2c4jlDd57v3NpygyfPQ6
/zKergRb02j4YqsB7Gv9m868beqmGjrmbAov1+v1MMEztoobSPwQZK/dkerHz5yf
e1K1dYHHnpvDA5sYZwNlTge/IojMZy5Rsm1Fs8ZQxun+6RrjfHW7QJbgQkcE2l/i
ISjRPUQTOGN2d+6XfoIRu76m13A7H9LiutW2IG10p6vFrwePuE3hwCO5XH2puAak
+1k4g+nBgzRlx+u01qKHqZq7nQwYfCq+fW3yqYOsepYTmaLUcT8+78C4PGu7Dz0P
sYCooq+byJ5eOPaq4DpA5szU2FuBABlBqBRVA+Wmy9slNuHiiK1fIOPO4V97Glqz
2F4Iivr9mbw79OrXx6bcqJm6EbAgpvyonlRnw0BVYd+1DEVEHntSx2QVN5wiEjqe
d6oyVpZT1VJb0CpnGU9p
=FgSp
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into arm/dt
Qualcomm ARM64 Updates for v5.1
* Add thermal trip points to cpufreq
* Add SDM845 IOMMU info for SDHC, USB, and WLAN
* Fix MSM8916 clock cell argument
* tag 'qcom-arm64-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
arm64: dts: sdm845: Fixup dependency on RPMPD includes
arm64: dts: sdm845: Add clocks and iommus to WCN3990 WLAN node
arm64: dts: qcom: sdm845: Define iommus for USB controllers
arm64: dts: qcom: sdm845: Define IOMMU for sdhc 2
arm64: dts: sdm845: wireup the thermal trip points to cpufreq
arm64: dts: msm8916: remove bogus argument to the cpu clock
[arnd: I've pulled the earlier branch again after an update, this
adds the stuff listed above, and fixes a build error from the missing
dependency, as I requested]
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
i.MX SoC changes for 5.1:
- Support cpuidle for i.MX7ULP, states WFI, WAIT and STOP get added.
- Support SoC revision detecting for i.MX7ULP by reading JTAG_ID
register from SIM module.
- Select PM and GPCv2 irqchip driver options for i.MX8 support, as they
are essential for building an i.MX8 based system.
- Skip build of ssi-fiq code if SND_SOC_IMX_PCM_FIQ is not enabled.
* tag 'imx-soc-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: imx8mq: select PM support
arm64: imx8mq: select GPCv2 irqchip driver
ARM: imx: add i.MX7ULP SoC revision support
ARM: imx: add i.MX7ULP cpuidle support
ARM: imx: don't build ssi-fiq if not required
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Contains a few DT updates on top of part 1 of the pull:
- MSMC RAM support (on-chip SRAM)
- Main system control module support
- USB support
- ADC support
There is an extra dt-binding update included, which has been acked
by Rob.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCAAuFiEEtQ6szHmfiBT7fujkyvq9MXlQGhEFAlxme1MQHHQta3Jpc3Rv
QHRpLmNvbQAKCRDK+r0xeVAaESgdD/9aZCR4YX27oQV5YmIsT0DkleOve48MIK9A
ex2Qk5dtZM8GRPTKQPfI1i8kHMya9Hlwb3NRAjCrZnnNRjge5LvTcDWbvSeUzlc1
BjyygctF2Sb9zKKyCoqV9UklpXisqw3QTxwmtUkdHNAzeyiQe71MM8XCEeBHcjUu
7EZJUzBPX4fABo560/1phubG4PrLA7eNG8gPl0p0LFf91ug5c+QO0jv+3p7K9pvn
o4TxyKgEXwADfx4px6y6u4uEuO3OXtYWNGbRhAaGXUAgEFiOYz5gJlgti7M16kXb
D1YeE4oKl3aXbCjb2V5FzoNw08zgQZgRT3QltyQnAZ/kYs1CFX4ooXUMx9GuCaJ3
T2UZ33t2lm4zVoYhlpKlZlZlk7bO4U9ZaOeSv+daKitpxvZPyJM7NLRTawCc3yyZ
08RJmYAf9Rl6MmNbrhyX3XQ5VC9/O26L1Gx+92bRFvdNL3Uwoi6T8bWFxbWrdr76
cL2aF9rYzVq3dQetNiqozg0GB/sCgEO1luGgkfIMLS9CpNxLPNa6orysRfMfkdJh
b1R51dUq80cl5v2lagTquFKb1T+/GRgEv/hi9aIR/Yfl2ASufFFQGkCKUPyFnPoX
BhH7Izg47x8HwAPU2s20nMJmaZ7hJ0PW1MUqidXgIdto9X82QWLcUCoeGXG1PAJR
uWFlyqaNag==
=L6dq
-----END PGP SIGNATURE-----
Merge tag 'am654-for-v5.1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into HEAD
AM654x SoC updates for v5.1 (part 2)
Contains a few DT updates on top of part 1 of the pull:
- MSMC RAM support (on-chip SRAM)
- Main system control module support
- USB support
- ADC support
There is an extra dt-binding update included, which has been acked
by Rob.
* tag 'am654-for-v5.1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
arm64: dts: ti: k3-am65-mcu: Add ADC nodes
dt-bindings: input: ti-tsc-adc: Add new compatible for AM654 SoCs
arm64: dts: ti: k3-am654-base-board: enable USB1
arm64: dts: ti: k3-am6: add USB support
arm64: dts: ti: am654: Add Main System Control Module node
arm64: dts: ti: k3-am65: Add MSMC RAM node
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch fixes a dependency issue with the RPMPD dt bindings. This
temporarily removes the include file and adds hardcoded values for the
OPPs until the other changes full land. This will be addressed in 5.2.
Fixes: 5b6f186f0a ("arm64: dts: sdm845: Add rpmh powercontroller node")
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
* 'for-next/perf' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux:
perf: xgene: Remove set but not used variable 'config'
arm64: perf: remove misleading comment
dt-bindings: arm: Convert PMU binding to json-schema
Two new additions to arm64's defconfig to support A64 boards.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXF1a8wAKCRDj7w1vZxhR
xYvJAQCpobGf96IZw2tNgyrz/7hd54ZjpYkkvAJuLK5wMHhHuAD/d2IBBVQ2yu5q
IX6Z40PXrKz43QFFszDThZy9tMqdng0=
=TfND
-----END PGP SIGNATURE-----
Merge tag 'sunxi-config64-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/defconfig
Allwinner arm64 defconfig changes for 5.1
Two new additions to arm64's defconfig to support A64 boards.
* tag 'sunxi-config64-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: defconfig: Enable SUN6I Camera sensor interface
arm64: defconfig: Enable I2C_GPIO
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable:
* PCM3168A support which is required for audio on Kingfisher daughterboards
* R-Car thermal support
* Gen3 PCIe PHY support
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAlxdXgkACgkQ189kaWo3
T77HRw//YxTxVtb9NR3o+z5+XtCg1FtCOuoFcS0kDm1frR8pmZAFYZWuwMoki6Q8
lESlWlCXPL5yJ505jlICqiano24Q/WnTs0aZj7TvbvtsWHqalG3C5dQRWVVq/7DP
Qvnr4p/EGEWjgKx1UHCNGLS7xHaYVePTCT4Opq+53vnx4ZQGf5wlnbJtuhZZYaEp
JCPbLCftVVSAgNh0E9P559Ww9eZ1B7Xs1ZdM4CXPr22j7HMAj2cvUv87rZ3B57to
DdOOWbAD6JOSdBQ338grppPJX9DlyVb8oYeJtmYcCRw7jK0zz0nlCTs/gsCu75ej
FKdfAEchkD6ZYQ9h8j+7LTuGwkkSOmVYH+OubwY9eoykgoBkaIWIw7q4PTIu2LNG
wAAqm7X0iPYpaT+z/52E1dTZY044+GyYqf0hNjK/3v3fj6nrTCoWZnuqj+waQR8c
HeeDtawg1/oolhYZKgdi7d6CkFvzBM87Yuta075E/25G2QWkWwP79juUWOUgC7FZ
NdVtRyUdaANjdDBpXGLE/q/E/WyXrzo7eDTEY74RnfLLOcNvc7bC9HP3hd5DES57
W9Oss9msOpMhl9l3539/kHA9HetjiqpAFtJEKKB53MrzZW9BqLjmKAUshOOndsUz
0WisNZo1jmq/uFRMzcSHcsye/IeeIH7m4TRIe2tqqeUrlgSAHy4=
=gf/c
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm64-defconfig-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/defconfig
Renesas ARM64 Based SoC Defconfig Updates for v5.1
Enable:
* PCM3168A support which is required for audio on Kingfisher daughterboards
* R-Car thermal support
* Gen3 PCIe PHY support
* tag 'renesas-arm64-defconfig-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: defconfig: select Kingfisher Sound related configs
arm64: defconfig: Enable R-Car thermal driver
arm64: defconfig: Enable CONFIG_PHY_RCAR_GEN3_PCIE
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enables the TCU driver to be built into the kernel, so that the TCU can
be used as debug serial on Jetson Xavier. This also enables the MAX8973
regulator driver that is required for CPU frequency scaling on Tegra210.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlxdmbgTHHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zoZgtD/wNXlW8b6EsETNmXRDbDuzn/+C7h8l+
Vs+8FdIenjY5/ZaxcYJLjIy3/KV0phB8dS56KaiuXJJAogzi3vCSSQWhzRtw53J1
F8bOweXCQT3vDAcwziL44pNjxXRtXENcywqAhhKBAxmNQ/84W9dtB+ZcBZLJWBDg
pMSJ/kPJggnwOoSkMREP46z6EoleaD+K+nnfX5Lp14W+wOwl65YfFA+WdJRsiYlF
2kPGotmWOXUTj2rIDMBGmDLgWOsBwOVhi3TS7psWNtFflrCFPuTwUchHWyL4cTO0
h/4/4149ZrXIEcba1rkZKfH6uHaPZhMEKDFA0Nt4RKnxPHcbYMpWqxC1dmvWWHeJ
eHjStTb1UFOEyBG7LgbIkdBGXa07zHw3amCyKao6CCVVpfCfzfQ/XqMd5CYWDHc2
Gb+kFnLBiUkvDh5hLV5h6RpatJMWAlFneNUESFjURhVWRJZUfy/4hPEECaiZ/1h7
x7Yu/nTY5sSPHMkZIikxatJZfhh0rYeojf4GPkMbhNzUL+HTgjYT2aVBfsj8eZOG
4wWWFqxRugneOKpRAtu+CQSBjpX+ZxDJ91O4ov0oiWrict89Mlljp5hKGApZ2AJs
luEWJbfNm1L7oxqjg+Znhw0sMfYa2F031PQZxSWhJjaTYLTAcArBGPVbc6ucwFln
aBcs1xUAuigSEg==
=Xuyn
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-5.1-arm64-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/defconfig
arm64: tegra: Default configuration changes for v5.1-rc1
Enables the TCU driver to be built into the kernel, so that the TCU can
be used as debug serial on Jetson Xavier. This also enables the MAX8973
regulator driver that is required for CPU frequency scaling on Tegra210.
* tag 'tegra-for-5.1-arm64-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: defconfig: Enable Tegra TCU
arm64: defconfig: Enable MAX8973 regulator
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Enable a number of i.MX SoC and driver options in arm64 defconfig.
The built-in drivers include: clock, pinctrl, power domain, serial,
MBox, SCU, Ethernet, MMC, regulator and watchdog, which are mostly
essential for building an useful kernel image for i.MX8 platform,
booting with rootfs on NFS or eMMC.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJcYqUwAAoJEFBXWFqHsHzOJnkH/2R0OT6zLykAAvG2grUjD73x
5VTEbvlSnSrOur0vBXEZfTi6l3mvtuXj3L9wEpIB9dKgOAgGflAOqRlib0xrwFXW
JRnzgckooeEpeMbj482gN2xUIbkAg7V8P15lhrkPIGKcGDwtc2o2uTfPRMyRKxRB
szH3xl+OR38snzqtuaPEvxdguE2ZW1fMRm8CqDq3nKYD21wYW6WB6S9MLlaYfD6k
RxtjEBCbUCV7OaN90HlXi/u7fkzwDgd9dN4M18DTgP59qWkZNmZ+HGj2Wf8a3Vgc
7E/cBL+W1fbcGto+j5H2wNHYzT4C9O9EKbskKOs/HW2zojxVfNXsBrXOLMreWMk=
=dPMN
-----END PGP SIGNATURE-----
Merge tag 'imx-defconfig-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/defconfig
i.MX defconfig updates for 5.1:
- Enable a number of i.MX SoC and driver options in arm64 defconfig.
The built-in drivers include: clock, pinctrl, power domain, serial,
MBox, SCU, Ethernet, MMC, regulator and watchdog, which are mostly
essential for building an useful kernel image for i.MX8 platform,
booting with rootfs on NFS or eMMC.
* tag 'imx-defconfig-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: defconfig: Add IMX2+ watchdog
arm64: defconfig: Enable PFUZE100 regulator
arm64: defconfig: enable NXP FlexSPI driver
arm64: defconfig: Add i.MX8MQ boot necessary configs
arm64: defconfig: add imx8qxp support
arm64: defconfig: add i.MX system controller RTC support
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Extend timeout for wifi to power up on Ultra96
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlxiwJUACgkQykllyylKDCGTFQCgkxFLqTdsRVpcXbwdVZbI0TBL
CukAn3kkFlyUv/OE8z3K1u32tHKTDqyK
=2Qw6
-----END PGP SIGNATURE-----
Merge tag 'zynqmp-dt-for-v5.1' of https://github.com/Xilinx/linux-xlnx into arm/dt
arm64: dts: zynqmp: DT changes for v5.1
- Extend timeout for wifi to power up on Ultra96
* tag 'zynqmp-dt-for-v5.1' of https://github.com/Xilinx/linux-xlnx:
arm64: dts: zcu100-revC: Give wifi some time after power-on
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Interrupt support to Armada 7K/8K thermal nodes
- Armada 37xx related patches allowing to enable suspend to RAM
(USB2, USB3, PCIe, SATA, DSA)
- uDPU board support (Armada-3720 based):single-port FTTdp
distribution point unit
- Fixes for EspressoBin Ethernet support when using U-Boot mainline
- cleanup for partitions under flashes nodes
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCXF3x1wAKCRALBhiOFHI7
1ZtFAJ4pn8nIeHqWgYEUmWmCpQXnUoc4eQCgninj7JcAFV8KNLKhRCkKdlkeO38=
=Wt6S
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt64-5.1-1' of git://git.infradead.org/linux-mvebu into arm/dt
mvebu dt64 for 5.1 (part 1)
- Interrupt support to Armada 7K/8K thermal nodes
- Armada 37xx related patches allowing to enable suspend to RAM
(USB2, USB3, PCIe, SATA, DSA)
- uDPU board support (Armada-3720 based):single-port FTTdp
distribution point unit
- Fixes for EspressoBin Ethernet support when using U-Boot mainline
- cleanup for partitions under flashes nodes
* tag 'mvebu-dt64-5.1-1' of git://git.infradead.org/linux-mvebu:
arm64: dts: marvell: armada-37xx: link USB hosts with their PHYs
arm64: dts: marvell: armada-3720-espressobin: declare SATA PHY property
arm64: dts: marvell: armada-3720-espressobin: declare PCIe PHY
arm64: dts: marvell: armada-37xx: declare the COMPHY node
arm64: dts: marvell: Remove unnecessary #address-cells/#size-cells under flashes
arm64: dts: armada-3720-espressobin: Set mv88e6341 cpu port as RGMII-ID
arm64: dts: armada-3720-espressobin: Configure RGMII and SMI pins
arm64: dts: marvell: Add device tree for uDPU board
arm64: dts: marvell: armada-3720-espressobin: declare PCIe warm reset pin
arm64: dts: marvell: armada-37xx: declare PCIe reset pin
arm64: dts: marvell: armada-37xx: declare USB2 UTMI PHYs
arm64: dts: marvell: armada-37xx: fix USB2 memory region
arm64: dts: marvell: armada-37xx: declare SATA clock
arm64: dts: marvell: armada-37xx: fix SATA node scope
arm64: dts: marvell: add interrupt support to cp110 thermal node
arm64: dts: marvell: add interrupt support to ap806 thermal node
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add device nodes for usb3, iommu, smi, i2c, spi, pwm,
mmc, NAND flash and PCIe
mt6797:
add pinctrl node
enable uart pins on x20 board
enable uart pins on EVB
mt7622:
Add all CPUs to the cooling maps
mt7623a:
Remove unused binding description
mt7629:
Add binding description for the SoC and the BananaPi
based on this chip
mt8173:
Add all CPUs to the cooling maps
mt8183:
Add binding description for the SoC
-----BEGIN PGP SIGNATURE-----
iQJLBAABCAA1FiEEiUuSfQSYnG8EMsBltDliWyzx00MFAlxd2gYXHG1hdHRoaWFz
LmJnZ0BnbWFpbC5jb20ACgkQtDliWyzx00MXBg//VKQgMqIWshMhu7hrD0wkPXZw
B0BJVlWhywTEisv3oduSL5HOVzKU6pQrWnF+X9PYokwNxz3VkNh3RixaLGsY3JOr
mkGtx3zAi1qsKYoKH6PNBhJVNCdX8D9SFlBSNOGkK0P5s0kjuPqzk28QU3ehwzdo
pFjbNadNDL9ySoybFtWGR8UwNkqq0w9acuiZbuRrqzdqkZLdxQ6zDry9P9s+97lA
WxFQEm+yhGHkpOb1XG75Zw3JBG55L3KymZV+h60wqHvdVCszINZZ9C2c/PqsWGVd
JzWMJPx2cghfLZdGlr5HQhKD5xM2Swmy2b5co4yRwsSmXdiK2RDkHkkli5CMpiIG
bt/6v3YffIVV07p/pzWrcOhJex4tCs0w3w24T03FxfCWVNXwb2kIV0Sv8dSBhUku
aESCBSrU0XAaKmhOPv49ys1oACpvPA9v/QyR+YyQPnK/4c4YezPidhCStvzhoxFG
a64OID6B1cmhI8PBCecRG22fEmDxktTj/FJ/0nsdbUgwbMXubr2vr9RzJW3B/M+G
z2ykW6q2K736EWWfKTpzXxfghVSaE90F1leQ3hjIv7h4AuribDw4IJ6ye+uI4Hb/
jiVHy6TSk8C07jMsvjifs1dL7UF6GIisD+90psuaiYngjilQkaHeDkosybe4qA6n
+r/pe4bCWvajl37DMXs=
=xm9P
-----END PGP SIGNATURE-----
Merge tag 'v5.0-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt
mt2712:
Add device nodes for usb3, iommu, smi, i2c, spi, pwm,
mmc, NAND flash and PCIe
mt6797:
add pinctrl node
enable uart pins on x20 board
enable uart pins on EVB
mt7622:
Add all CPUs to the cooling maps
mt7623a:
Remove unused binding description
mt7629:
Add binding description for the SoC and the BananaPi
based on this chip
mt8173:
Add all CPUs to the cooling maps
mt8183:
Add binding description for the SoC
* tag 'v5.0-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
dt-bindings: arm: mediatek: add support for MT7622 BPI-R64 and MT7629 RFB
dt-bindings: arm: mediatek: remove unused "mediatek, mt7623a"
dt-bindings: arm: Add bindings for Mediatek MT8183 SoC Platform
arm64: dts: add pcie nodes for MT2712
arm64: dts: add nand nodes for MT2712
arm64: dts: add mmc nodes for MT2712
arm64: dts: add pwm nodes for MT2712
arm64: dts: add spi nodes for MT2712
arm64: dts: add i2c nodes for MT2712
arm64: dts: add iommu/smi nodes for MT2712
arm64: dts: Add USB3 related nodes for MT2712
ARM64: dts: mediatek: Add all CPUs in cooling maps
arm64: dts: Add uart for mt6797 EVB
arm64: dts: mediatek: x20: Add pinmux support for UART1
arm64: dts: mediatek: mt6797: Add pinctrl support
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This contains a couple of fixes to existing device trees, enables CPU
frequency scaling on various Tegra210 boards, enables the TCU as debug
serial port on Jetson Xavier, adds various improvements for SDMMC on
Tegra210, Tegra186 and Tegra194 boards and finally adds initial support
for the NVIDIA Shield TV.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlxdmX0THHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zob8+D/4oX6rlHS70H1CVhEF/2JejVBki5iX2
YGsjtywFGVU072OjQrIXARq/7LlH/4ykF8m8rNCTCzL1SewxpAhzTuyHSAitREjX
FMICa9bfv26J8n4n9SVOvuWmHc88rK3xaXgiKXIO/2viZsVDC7jeEfl/ztbSUWC7
KHx3moU3mzM0AqIX0z+tYg93uxYpx/sUgygLsJIneaj7b1g5sMZCAdLWQnvXmZKf
q5WTwbfUmhg2OrhnO6WXr6swmo7cXKO3zJcm/+b2adf01axMgCjA1RVFgO9yonqn
s2402oVRv/y7jsM7HGptlS6NqcurMnhlKCEUsVucXugWwbbAj/oFirYiCWW6fkq/
fgpOVbudjtF4jEiwxJ1KOVXlT34/Tt/Rksxr9uAht2L3KyDCT6mVKFVHq2jIFYVx
bIXT9HB3/ZjoVQzQKwRqKR8P9923avMmGvkGrDVXvvXx10hm7CK+UYJxOuwf80dQ
7ahfqSf34Pm3ezWpzr2TJxbd1DOFl57W2K/BjM3eUolwYXwIv8jANj87CqJj+llf
gtzMZS1bEdmFiP8DVnW0oQRS7quqSw0jo6qYLPV/dUBMPLFN8kdoWC9AfpQAaOxY
jJjpKBTkRcpc48TNAqcAuq53d1f+fsRptuIX2sLuSz7i3mQ80fJo+dET836Q0nYx
YYgVNWlJ5FTYyg==
=31KA
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-5.1-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
arm64: tegra: Device tree changes for v5.1-rc1
This contains a couple of fixes to existing device trees, enables CPU
frequency scaling on various Tegra210 boards, enables the TCU as debug
serial port on Jetson Xavier, adds various improvements for SDMMC on
Tegra210, Tegra186 and Tegra194 boards and finally adds initial support
for the NVIDIA Shield TV.
* tag 'tegra-for-5.1-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (25 commits)
arm64: tegra: Update compatible for Tegra186 I2C
arm64: tegra: Update compatible for Tegra210 I2C
arm64: tegra: Support 200 MHz for SDMMC on Tegra194
arm64: tegra: Add CQE Support for SDMMC4
arm64: tegra: Add SDMMC auto-calibration settings
arm64: tegra: Mark TCU as primary serial port on Tegra194 P2888
arm64: tegra: Add nodes for TCU on Tegra194
arm64: tegra: Enable DFLL clock on Smaug
arm64: tegra: Add CPU power rail regulator on Smaug
arm64: tegra: Enable DFLL clock on Jetson TX1
arm64: tegra: Add pinmux for PWM-based DFLL support on P2597
arm64: tegra: Add CPU clocks on Tegra210
arm64: tegra: Add DFLL clock on Tegra210
arm64: tegra: p2771-0000: Use TEGRA186_ prefix for GPIO names
arm64: tegra: p3310: Use TEGRA186_ prefix for GPIO names
arm64: tegra: p2597: Sort nodes by unit-address
arm64: tegra: p2972: Sort nodes properly
arm64: tegra: Add regulators for Tegra210 Darcy
arm64: tegra: Add pinmux for Darcy board
arm64: tegra: Add gpio-keys nodes for Darcy
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Our usual round of DT changes for the arm64 Allwinner SoCs:
- Enabling of the various power supplies on most a64 boards
- H6 SRAM controller support
- A64 CSI support
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXF1ZiQAKCRDj7w1vZxhR
xeeaAQCuII0MyMyRYhk4XPkjRncEks7A1Fp7u1kjR4VjbNq8JQD+OhCbKMAz4DVv
T7DeI92HwEO2Dx/ggNMVYDCUDyH55gI=
=Pd5b
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt64-for-5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Allwinner arm64 DT changes for 5.1, take 2
Our usual round of DT changes for the arm64 Allwinner SoCs:
- Enabling of the various power supplies on most a64 boards
- H6 SRAM controller support
- A64 CSI support
* tag 'sunxi-dt64-for-5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: dts: allwinner: a64: Enable PMIC power supplies on various boards
arm64: dts: allwinner: a64: teres-i: enable power supplies
arm64: dts: allwinner: h6: Add support for the SRAM C1 section
dt-bindings: sram: sunxi: Add compatible for the H6 SRAM C1
arm64: dts: allwinner: a64: Add A64 CSI controller
arm64: dts: allwinner: h6: Move GIC device node fix base address ordering
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Our usual round of DT changes shared between arm and arm64.
We have a bunch of changes for board, improving the eMMC support on the H5
variant of the All-H3-CC, enabling HDMI and reworking the CSI driver.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXF1X8QAKCRDj7w1vZxhR
xX9ZAP9KwFKKehrS1QJjTHKeowUKEnRHuDj2MlwTZJgCw/AMMgEAzgRZwY/VH/Os
aQIhJho9hWmBE0dePIZuWzzCp1giNw8=
=7jQV
-----END PGP SIGNATURE-----
Merge tag 'sunxi-h3-h5-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Allwinner H3 and H5 changes for 5.1
Our usual round of DT changes shared between arm and arm64.
We have a bunch of changes for board, improving the eMMC support on the H5
variant of the All-H3-CC, enabling HDMI and reworking the CSI driver.
* tag 'sunxi-h3-h5-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: dts: allwinner: h5: libretech-all-h3-cc: Mark eMMC HS-DDR 3.3V capable
ARM: dts: sunxi: h3/h5: Drop A31 fallback compatible for CSI controller
ARM: dts: sun8i-h3: nanopi-m1-plus: enable HDMI
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add SMMU node for Stratix10
- Add vendor prefix fo Novtech
- Add a new 96Boards Chameleon96 board that uses a Cyclone5 SoCFPGA
- Add missing reset properties for all IP on Cyclone5 and Arria10
-----BEGIN PGP SIGNATURE-----
iQJIBAABCgAyFiEEoHhMeiyk5VmwVMwNGZQEC4GjKPQFAlxYYAAUHGRpbmd1eWVu
QGtlcm5lbC5vcmcACgkQGZQEC4GjKPSfPA//a013n1vCV9Wz6RsbXNRODXzhV6FN
9uPWAdbkuWrCvDFAH+9s/0nMwxAj8f1HCEK9J07CPRcjcLPO7iHfIUeJ4lbCNCXZ
1ZuLDdK0Y4GjziJ4xlUP0JvUpJXtRKo+XDXVC+jNAMQy6wQpsEYdEwpeTPo94jrv
X0Zait3PeaY6ai6ImzV4QOYYmZ9GhRHjNY/Hc8jSsZeMWk+sMWygExlUngXlpO8c
dvK1Z4dfhrRZyJ/ewjjb/D0eekq8XiIfGmI4A2Cox3A73XAmtPEL3MT57BbPnq7f
jmNmlh7yRrxZHVErSt0dJTOJ6dNx+McuuwSmDL1vR19M44JUbVOjLjDUEwA7tSmr
eQXVhGuYHfxgJT0CeEBIHJAxPZfTqy68IijZYXv4aWimFdsbeAtraY7PKeZ/TnOP
3Aa9GDSks5NsAGVR5AltiNRmZujyQktbcNU8TcNt8tc19Kub8Q9GVhsmPUIKEov8
oAeXq4xbvGe6Ike6cfR1H+P14mgpbxJSZwGQoqky1T3lWqFBhl/93/ixpzt5jMWX
96tHA7VuZ7+in3BoqzHNxZ2PWpHScd3UScLxzxFEotW2nCofXCLCVkW+Zl8xWLa9
eu5GXE0ZzA04Elaagj2MM/rTsIgWFWqROq4A3Za6k5AB7quThr1yMoL+5Q5keOlO
4xAhCKudZb74BS4=
=8OgV
-----END PGP SIGNATURE-----
Merge tag 'socfpga_dts_for_v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt
SoCFPGA DTS updates for v5.1
- Add SMMU node for Stratix10
- Add vendor prefix fo Novtech
- Add a new 96Boards Chameleon96 board that uses a Cyclone5 SoCFPGA
- Add missing reset properties for all IP on Cyclone5 and Arria10
* tag 'socfpga_dts_for_v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: dts: socfpga: update more missing reset properties
ARM: dts: socfpga: update missing reset property peripherals
ARM: dts: Add support for 96Boards Chameleon96 board
dt-bindings: vendor-prefixes: Add Novtech Vendor Prefix
arm64: dts: stratix10: Add Stratix10 SMMU support
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
for 5.1, please pull the following:
- Stefan adds support for the Raspberry Pi 3 A+ by using the same
mechanism of creating a symbolic reference to the ARM 32-bit DTS file
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAlxV0bUACgkQh9CWnEQH
BwQ8Bw/6Anh/U7UiwqmxYCzEOUOE0Ry+v2Ar5CLSevUL2DbzP3fDEycRw4Cj2/0B
ZupHZFvCP4lYZEv1j679/nvcDz2XrfZ8+NED3ShHm9iIcXNtOodSGV7PYaeSdH6y
Ee63Cs7NlrwgHaSG8sDIvB3O7A+2Eq4/k7VuPPcGUIDF31TqqD9QgIA0qxGlq9dp
KheE7MsIklBk60OHq6rN+zRdgyxRYs0tuU8zv2SIT+8vK83NIV7t6ESRpj5Vw4x8
dCYYqCDJrormDlMV4cSC5nGo+7TrxZ2KvMQ/GxM/eDspDM0T+S+mYL8RrmEBLi+M
eUENDsLUt5pIjvXnyDXBIUTmWt+IFNCTdsyZ9WbGm/WES5+ktjRxe5VQOmezBfWV
U0uJ/chEZDz17zf2RpdQ4DuZT/QLqF1Uc2O+CyXNv3VwJ0L95+EyWlQ7TqR9ssDQ
KlPoEU6MOzVHtCTfXzTOv3+b1ndAAErYGV1bGjWPeaNeQllogMXHTMWzZnAkYWWO
zwl2+HtXgaVZN0oaU2voEDXB3DYKbNHyLqrQL/9IbbNXWWeswP/lIEYuOJ/h8l4j
u2Cq8PP6z6vb/oGWQGUCfWMPttaB5cyFeEYxb84q8MwizG0Yh/nEo5G4E8CI+dQT
5oqHlfvcnYap/Q796qcUxySmYMAWVlQA59xQ36WNzg+mRL3SdJw=
=iDFK
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-5.1/devicetree-arm64' of https://github.com/Broadcom/stblinux into arm/dt
This pull request contains Broadcom ARM64-based SoCs Device Tree updates
for 5.1, please pull the following:
- Stefan adds support for the Raspberry Pi 3 A+ by using the same
mechanism of creating a symbolic reference to the ARM 32-bit DTS file
* tag 'arm-soc/for-5.1/devicetree-arm64' of https://github.com/Broadcom/stblinux:
arm64: dts: broadcom: Add reference to RPi 3 A+
ARM: dts: add Raspberry Pi 3 A+
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
two being part of a family and sharing bigger parts of the devicetree.
rk3328 got sound-related upgrades and a wider patch drops mmc display-wp
fields from nodes which shouldn't use it.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlxTAa0QHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgYrMB/93qkhsRz6kGXyeGWLQFYVJZET1IsHIqRUl
HDu/NwvZRPheupjgk37lAbTvQ8TeE8zb8i5I3lbhSZr1m8GL1Bsc3XZc2l8FXA9f
jib3xCaykp/qZMjgqSsesZmwcMzpUdMuGvK4NLLIWNWW+u3jQzo8N4eyXexRzY29
4Z69GodfMbsvFfi9mJ63pb2iTJhU+h1pLm4X8Df5DE4i1QyL9+vOiVYFM7AaMhMC
bBHzkQiJZC5hlhKUcCCW22T62yPnCHQdRG7SNPVyh/zSl3GvtL1CP9CHFDsPHG/j
443k+McXCvRCSK1wjRJraffD8gluBa/QgjFZj7hvuooOX7aGlM2E
=Bc63
-----END PGP SIGNATURE-----
Merge tag 'v5.1-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
New boards are the Rock Pi 4, NanoPC-T4 and NanoPi-M4, with the last
two being part of a family and sharing bigger parts of the devicetree.
rk3328 got sound-related upgrades and a wider patch drops mmc display-wp
fields from nodes which shouldn't use it.
* tag 'v5.1-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: clean up the abuse of disable-wp
arm64: dts: rockchip: 'Fix' nanopi4 uSD card detect
arm64: dts: rockchip: Add NanoPC-T4 IR receiver
arm64: dts: rockchip: Refine nanopi4 differences
arm64: dts: rockchip: Add DT for NanoPi M4
arm64: dts: rockchip: add ROCK Pi 4 DTS support
arm64: dts: rockchip: Add devicetree for NanoPC-T4
arm64: dts: rockchip: enable analog audio node for rock64
arm64: dts: rockchip: move rk3328 #sound-dai-cells to the soc dtsi
arm64: dts: rockchip: add rk3328 ACODEC node
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
It contains a fix for i.MX8MQ EVK board device tree, which makes the
broken eMMC support work as expected.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJcVkZzAAoJEFBXWFqHsHzOjfwIALX4Sy/lU2X7M/ISKHwEIYP+
aRQ8ymXjRldTmCQusQVez8wRnphVqFI0Iyk6ktt/xzktmCCrhPDoUSKJWpwOuXj7
xTj5Rn13xNmanZ0Lox1d7w4dLEhWzYM+n2IAQT0UkcwQ6zhZQ+jx8dSbFVr15cd7
grlv5/a98IU7RvpdZzzIJvfHhey4R0diZicE6Gwha94JDGZkeyovdJ+5LvCiU7QU
lx632vsnIMWSlqNWmdKK8SvtduhRz099nhp+sZFrP/7CK8E+j1c6nV0rF2onUmkO
kvRLpw/IbBheQb9lBmcTrlf6f6Om03juy0Q682bX78qcMLvIAMczNsJNpfrNl8o=
=2/kD
-----END PGP SIGNATURE-----
Merge tag 'imx-fixes-5.0-3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
i.MX fixes for 5.0, 3rd round:
It contains a fix for i.MX8MQ EVK board device tree, which makes the
broken eMMC support work as expected.
* tag 'imx-fixes-5.0-3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: imx8mq: Fix boot from eMMC
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlxS/OQQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgbjLB/0XJqH9MerWA/J+OalNANjsXQemt8Vum4OA
4C5/ViMxMbzRQm+Sc2wCAzsq30Q6pqV74aTJYtUk6J2RalaiMCbkf8zRVZKzokbj
MKUdMmHu96ZA5LEqEEHK/eMOP4j70xz5VOnTBHQ2R759DkrS2U7rHIwx9ZX8XO9V
dI8rlHot9lgF1l8DDYLuPaLsILwHPhT/Y/wUv2Js5dZ5PFHS962I76sjYlngarT5
rd49Gv8ZvNDx1wftL4JtVMy/xuMKFRHhcxpF8TrdSS648U9Rvf9l2vXR6PErHfZP
poSG5jy1vn0aPmOEWjw1sDSXPcK7ImUNTM7k8ffTPecCmmC5gCIO
=qf0D
-----END PGP SIGNATURE-----
Merge tag 'v5.0-rockchip-dts64fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
Fix for new dtc graph warnings and a regulator fix for rock64.
* tag 'v5.0-rockchip-dts64fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: enable usb-host regulators at boot on rk3328-rock64
arm64: dts: rockchip: fix graph_port warning on rk3399 bob kevin and excavator