Commit Graph

36 Commits

Author SHA1 Message Date
Leo Yan
2158ab084b arm64: dts: register Hi6220's thermal sensor
Bind thermal sensor driver for Hi6220.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:58:55 +01:00
Guodong Xu
841478d4ae arm64: dts: add wifi nodes support for hi6220-hikey
Add wifi nodes support for hi6220-hikey

Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:43:10 +01:00
Xinwei Kong
d6b259d4fa arm64: dts: add dwmmc nodes for hi6220
Add all three dwmmc nodes description for hi6220

Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:43:07 +01:00
Chen Feng
a817137a6c arm64: dts: hikey: Add hi655x pmic dts node
Add the mfd hi655x dts node and regulator support on hi6220 platform.

Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Signed-off-by: Fei Wang <w.f@huawei.com>
Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Reviewed-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:43:04 +01:00
Guodong Xu
ad05f38ba9 arm64: dts: add LED nodes for hi6220-hikey
Add LED nodes for hi6220-hikey. There are total 6 LEDs on HiKey.
Four general purposed, one for WiFi activity, and one for Bluetooth
activity.

Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:22:10 +01:00
Guodong Xu
c2aad93200 arm64: dts: hi6220: add pinctrl for uarts and enable them
Add pinctrl for uart2 uart3 and uart4. Enable uart1 uart2 and uart3.

Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:22:09 +01:00
Leo Yan
9986054072 arm64: dts: add Hi6220's stub clock node
Enable SRAM node and stub clock node for Hi6220, which uses mailbox
channel 1 for CPU's frequency change.

Furthermore, add the CPU clock phandle in CPU's node and using
operating-points-v2 to register operating points. So can be used by
cpufreq-dt driver.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:22:03 +01:00
Leo Yan
8607357016 arm64: dts: add mailbox node for Hi6220
This patch add device mailbox node for Hi6220 in DT.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:21:58 +01:00
Zhangfei Gao
b4b31a7cd7 arm64: dts: Add hi6220 usb node
Add USB nodes for Hi6220

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:21:53 +01:00
Guodong Xu
0c2317512d arm64: dts: hikey: enable i2c0 and i2c1 for working with mezzanine boards
In HiKey board dts file, enable i2c0 and i2c1 for working with 96boards' LS
mezzanine.

Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:21:52 +01:00
Xinwei Kong
5ff3a4ddd1 arm64: dts: add all hi6220 i2c nodes
This patch adds all I2C nodes for the Hi6220 SoC. This hi6220 Soc
use this I2C IP of Synopsys Designware for HiKey board.

Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:21:52 +01:00
Zhong Kaihua
60dac1b19b arm64: dts: add Hi6220 spi configuration nodes
Add Hi6220 spi configuration nodes. Disable by default in hi6220.dtsi
and enable it in board dts for usage of 96boards LS mezzanine board.

Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:21:45 +01:00
Zhong Kaihua
379e9bf52d arm64: dts: add Hi6220 pinctrl configuration nodes
Add Hi6220 pinctrl configuration nodes

Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:21:45 +01:00
Zhong Kaihua
f2bfacf9dd arm64: dts: Add Hi6220 gpio configuration nodes
Add Hi6220 gpio configuration nodes

Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Signed-off-by: Kong Xinwei <kong.kongxinwei@hisilicon.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:21:24 +01:00
Leo Yan
58fa29bfbe arm64: dts: enable idle states for Hi6220
Add cpu and cluster level's low power state for Hi6220.

Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:11:32 +01:00
Leo Yan
9e92703165 arm64: dts: add sp804 timer node for Hi6220
Add sp804 timer for hi6220, so it can be used as broadcast timer.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:11:32 +01:00
Leo Yan
6da3aba6f0 arm64: dts: Reserve memory regions for hi6220
On Hi6220, below memory regions in DDR have specific purpose:

  0x05e0,0000 - 0x05ef,ffff: For MCU firmware using at runtime;
  0x06df,f000 - 0x06df,ffff: For mailbox message data;
  0x0740,f000 - 0x0740,ffff: For MCU firmware's section;
  0x3e00,0000 - 0x3fff,ffff: For OP-TEE.

This patch reserves these memory regions in DT.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:11:32 +01:00
Arnd Bergmann
047b2f6d7b ARM64: DT: Hisilicon Hip05 soc and D02 board updates for 4.6
- Add L2 cache topology
 - Use Cortex specific device node for pmu
 - Append all gicv3 ITS entries
 - Append gpio nodes
 - Append power button node for D02 board
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJWzv94AAoJEAvIV27ZiWZcMAgP/2SURsSAQz1m9CabPD78gqPx
 R4PUtAbcrz8f5BbYxGXEXdoDY7AExvjWkZoH5XIP2+xDSB26SRgdkvAqisMYD7RU
 FG78LKJ7vYbAAiJtoqkcwG6GdvdyXYhw3HqCsyfT8cH+PFy4QgiDexrzFgSTh1Sv
 x1CG69ddLjg0Uc0LQx7JUmzdxsZN+jt8lfLCAU9zZBzsVAtxadrxcT/y/V1SXNMI
 sblknpv3I5XPDsQd1Sho0cLU7sGI2rWz5HqXTrW1febw6AMCTkmljZhbq4ezjQG0
 GtB20LiuM3hYtZoQDAUAb/plABhfQOZ0nybjqDhGxvyUb6vuNHHLicA7CsrWsYgE
 5T5KR2nZv3fnYFW1dprgrpuirUdBSk125p7gTwBFmcWv2fMcNKVZROkrjP6I0cwB
 Qu9sUa8jQ0oQqKkPa8KVtNZMRSVwAI+G0aeoJAbAV8Zs7ux4kzkaRZOiROxklWtI
 HFIiFsKmgPcenYbyrH6/b60/GIKIUQBdEN1kbPHSqF6zIt/IoLZhfAL5DHBMuwWE
 aP4mFxPaLUrSNpXGFmSMs737oatHK4lvb2Z1F9YOHXHQ20ttTKFWwQi0SMc1iLEf
 E/KDZedI6aud2DheDl9P7+w9JhFflHMlL0ZT3KWSn7pJ5qelTgxhGE7aPEc2hPXt
 ojSxNrtTqI8Vx7FJdK6C
 =IxPW
 -----END PGP SIGNATURE-----

Merge tag 'hip05-dt-for-4.6' of git://github.com/hisilicon/linux-hisi into next/dt64

Merge "ARM64: DT: Hisilicon Hip05 soc and D02 board updates for 4.6" from Wei Xu:

- Add L2 cache topology
- Use Cortex specific device node for pmu
- Append all gicv3 ITS entries
- Append gpio nodes
- Append power button node for D02 board

* tag 'hip05-dt-for-4.6' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hip05: Append power button node for D02 board
  arm64: dts: hip05: Append gpio nodes
  arm64: dts: hip05: Append all gicv3 ITS entries
  arm64: dts: hip05: Use Cortex specific device node for pmu
  arm64: dts: hip05: Add L2 cache topology
2016-03-01 00:22:23 +01:00
Kefeng Wang
82a14b1e95 arm64: dts: hip05: Append power button node for D02 board
This patch adds poweroff button device node to support
poweroff feature on hip05 d02 board.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-02-25 21:15:58 +08:00
Kefeng Wang
8f41d122bf arm64: dts: hip05: Append gpio nodes
There are two dw GPIO controllers in hip05 peri sub, this patch
adds the corresponding device tree nodes.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-02-25 21:15:58 +08:00
Kefeng Wang
abf9c25d55 arm64: dts: hip05: Append all gicv3 ITS entries
There are four subsystems in hip05 soc, peri/m3/pcie/dsa,
each subsystem has one its, append them under gicv3 node.

They will be used by hisilicon mbigen.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-02-25 21:15:58 +08:00
Kefeng Wang
6897db62bb arm64: dts: hip05: Use Cortex specific device node for pmu
Instead of using the generic armv8-pmuv3 compatibility, use
the more specific Cortex A57 compatibility.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-02-25 21:15:58 +08:00
Kefeng Wang
dbb58d0f79 arm64: dts: hip05: Add L2 cache topology
The Hip05 SoC has four L2 cache for all 16 CPUs, every four cpus
share one L2 cache, add them to the dtsi file so that the cache
hierarchy can be probed.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-02-25 21:15:58 +08:00
Linus Torvalds
34229b2774 Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Pull networking fixes from David Miller:
 "This looks like a lot but it's a mixture of regression fixes as well
  as fixes for longer standing issues.

   1) Fix on-channel cancellation in mac80211, from Johannes Berg.

   2) Handle CHECKSUM_COMPLETE properly in xt_TCPMSS netfilter xtables
      module, from Eric Dumazet.

   3) Avoid infinite loop in UDP SO_REUSEPORT logic, also from Eric
      Dumazet.

   4) Avoid a NULL deref if we try to set SO_REUSEPORT after a socket is
      bound, from Craig Gallek.

   5) GRO key comparisons don't take lightweight tunnels into account,
      from Jesse Gross.

   6) Fix struct pid leak via SCM credentials in AF_UNIX, from Eric
      Dumazet.

   7) We need to set the rtnl_link_ops of ipv6 SIT tunnels before we
      register them, otherwise the NEWLINK netlink message is missing
      the proper attributes.  From Thadeu Lima de Souza Cascardo.

   8) Several Spectrum chip bug fixes for mlxsw switch driver, from Ido
      Schimmel

   9) Handle fragments properly in ipv4 easly socket demux, from Eric
      Dumazet.

  10) Don't ignore the ifindex key specifier on ipv6 output route
      lookups, from Paolo Abeni"

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (128 commits)
  tcp: avoid cwnd undo after receiving ECN
  irda: fix a potential use-after-free in ircomm_param_request
  net: tg3: avoid uninitialized variable warning
  net: nb8800: avoid uninitialized variable warning
  net: vxge: avoid unused function warnings
  net: bgmac: clarify CONFIG_BCMA dependency
  net: hp100: remove unnecessary #ifdefs
  net: davinci_cpdma: use dma_addr_t for DMA address
  ipv6/udp: use sticky pktinfo egress ifindex on connect()
  ipv6: enforce flowi6_oif usage in ip6_dst_lookup_tail()
  netlink: not trim skb for mmaped socket when dump
  vxlan: fix a out of bounds access in __vxlan_find_mac
  net: dsa: mv88e6xxx: fix port VLAN maps
  fib_trie: Fix shift by 32 in fib_table_lookup
  net: moxart: use correct accessors for DMA memory
  ipv4: ipconfig: avoid unused ic_proto_used symbol
  bnxt_en: Fix crash in bnxt_free_tx_skbs() during tx timeout.
  bnxt_en: Exclude rx_drop_pkts hw counter from the stack's rx_dropped counter.
  bnxt_en: Ring free response from close path should use completion ring
  net_sched: drr: check for NULL pointer in drr_dequeue
  ...
2016-02-01 15:56:08 -08:00
yankejian
48189d6aaf net: hns: enet specifies a reference to dsaf
This patch replace the assoication between dsaf and enet from string
matching to object reference. It requires the DTS to be updated within
BIOS. Thanks god it can be done for all released boards.

Signed-off-by: Kejian Yan <yankejian@huawei.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Yisen Zhuang <yisen.zhuang@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-01-21 12:02:31 -08:00
Linus Torvalds
9638685e32 ARM: SoC driver updates for v4.5
Driver updates for ARM SoCs. Some for SoC-family code under drivers/soc,
 but also some other driver updates that don't belong anywhere else. We also
 bring in the drivers/reset code through arm-soc.
 
 Some of the larger updates:
 
 - Qualcomm support for SMEM, SMSM, SMP2P. All used to communicate with other
   parts of the chip/board on these platforms, all proprietary protocols that
   don't fit into other subsystems and live in drivers/soc for now.
 
 - System bus driver for UniPhier
 - Driver for the TI Wakeup M3 IPC device
 
 - Power management for Raspberry PI
 
 + Again a bunch of other smaller updates and patches.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJWnsLfAAoJEIwa5zzehBx3KVcQAJS90XyeheS3LX+SUMsn5qAJ
 Q+NLzfYAAHZPafruOTcBATs9xUvuJM4KsdqXIWiA4gJig/ZFpF5dpDbrnhpdJFEK
 0ULSfZd9J4B4m7aBo6L8lVBEbd4i++updHpIYnmPx3tkLL0Win/VM8KlMpdOzMQN
 DncNFVIRJ80OxepdHgBu6yY7gv3Z8XhRrNukeG8EZTvHw5bJQHfjMOeAQNQWUmWa
 HLyO6uqYkca38XMJOhPhqt0mOpwh/X6ByUueIrIMpOksJcRnklrkjDnBuvp9dQ+8
 fU1sOjjYzQPiA6Oa3o/2ruBKj2FymLJ0OzONJb3xPiBO5bJbc1LJwK00tuIRC3hv
 r9Jqoqwae/AolqYephfao/LvUcoyHBaZ6aSbGQYms0Wy2FCkkkocfY2i7QP6S6Mz
 qtOCHxX+yF921AEZ1xTOKgBvBU931WM1MQOe4s1QVllRlLFJhrGqDDwsNlPwRa+6
 OkXmPJSEhsHGFaCdA3iOEy+/W2dvMbVOaGa9csNDpPcSJhhpxc5A4CYRlFSwGyM1
 oL20g1T3ybDP+EkNcdpavWdQ55toWGmm48PunIZImVSdgNRZZQJw107yA/UzQTNz
 kOg27kqtjpM4xcpxmwGlIj4Zoy1M390ACm+n79Awa9agvjOvfV4QE1tLB4tiXyuy
 0Pxy8WWL/G5Si8bKWsfc
 =khZ5
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Olof Johansson:
 "Driver updates for ARM SoCs.  Some for SoC-family code under
  drivers/soc, but also some other driver updates that don't belong
  anywhere else.  We also bring in the drivers/reset code through
  arm-soc.

  Some of the larger updates:

   - Qualcomm support for SMEM, SMSM, SMP2P.  All used to communicate
     with other parts of the chip/board on these platforms, all
     proprietary protocols that don't fit into other subsystems and live
     in drivers/soc for now.

   - System bus driver for UniPhier

   - Driver for the TI Wakeup M3 IPC device

   - Power management for Raspberry PI

  + Again a bunch of other smaller updates and patches"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (38 commits)
  bus: uniphier: allow only built-in driver
  ARM: bcm2835: clarify RASPBERRYPI_FIRMWARE dependency
  MAINTAINERS: Drop Kumar Gala from QCOM
  bus: uniphier-system-bus: add UniPhier System Bus driver
  ARM: bcm2835: add rpi power domain driver
  dt-bindings: add rpi power domain driver bindings
  ARM: bcm2835: Define two new packets from the latest firmware.
  drivers/soc: make mediatek/mtk-scpsys.c explicitly non-modular
  soc: mediatek: SCPSYS: Add regulator support
  MAINTAINERS: Change QCOM entries
  soc: qcom: smd-rpm: Add existing platform support
  memory/tegra: Add number of TLB lines for Tegra124
  reset: hi6220: fix modular build
  soc: qcom: Introduce WCNSS_CTRL SMD client
  ARM: qcom: select ARM_CPU_SUSPEND for power management
  MAINTAINERS: Add rules for Qualcomm dts files
  soc: qcom: enable smsm/smp2p modular build
  serial: msm_serial: Make config tristate
  soc: qcom: smp2p: Qualcomm Shared Memory Point to Point
  soc: qcom: smsm: Add driver for Qualcomm SMSM
  ...
2016-01-20 18:42:30 -08:00
Linus Torvalds
62c79bb3a9 ARM: 64-bit DT updates for v4.5
This is the first release where we split up the 64-bit contributions a
 bit more, and in particular we are having a separate DT branch for them.
 
 Contents:
 
 - New devices added to Broadcom NorthStar2
 - Misc fixes for Exynos7 boards
 - QCOM updates for MSM8916
 - Rockchip tweaks for rk3368 SoC and eval board
 - A series of fixes for APM X-Gene v1 and v2
 - Renesas R8A7795 CPU/PSCI additions
 - Marvell Berlin4CT PSCI, cpuidle, watchdog portions
 - Freescale LS1043a SoC and dev board support
 
 + some treewide or other misc changes
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJWnr//AAoJEIwa5zzehBx35r0P/jyMtxtcXn9v9Tsdcenu91B/
 wLVUHuVUtTQMq8nBHp3NUjFFPi51B7pKYT3uaPOE+r9TjHrwDgFP5rNVJwD3Jyn3
 BTmGTM/4HNPTc+eLFk7yn0j/4xR6Njwf7DI5tjK4Xq6UC+xVk7v7Gy0dOcLPGUs4
 x5hxSGSY6ncgEpABnK/w+GhxNfc6ua8TM3T7ZK9VeA9aZXFdp8lCWBGj4TyTT1By
 m2E/uwzhFeN2PQ4MLDI3MvDQoGWsOcsDLTB0oltdCSRdJoGn3Zbl+xG9/tMZTDiy
 pa8ItMb7VmQQdS/WNgAT3obgqvcfelSNvFaVWoLfjamb0bPVaz55bM+IjTqHr5kE
 ZjdDMq1kP4DdIPIFHs/4cmSkG7OUf+PO4/2BzqzroKCgZPXZX9NRr3aDQQYAzLlr
 yLUAGkY5O1cGP8CXP1zFZTiHjEmbCFX3XOpi6obTnyElxxxX3LDFsqrRSmFs41HF
 V7AKraWoEZ1GWWycRMC8SRo/OuEgx6aCRzNVR+0NwLk6AP6Kdxsb9naq3I2wfS5L
 +9KnNN7nNhRYMP0L53aMEhYrxkajeUrO3a8JbfowBlCwXlvLBPysGu11yWvI8flG
 9SLK/TMmsa1Yk+XDjjVSHn8BKsYI1iCGnrxXjb2ZYNimqSPliMNxGr8lKvJ1L1Bz
 ELq+CpJizQ4tzuJpk6xv
 =f4yG
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM 64-bit DT updates from Olof Johansson:
 "This is the first release where we split up the 64-bit contributions a
  bit more, and in particular we are having a separate DT branch for
  them.

  Contents:

   - New devices added to Broadcom NorthStar2
   - Misc fixes for Exynos7 boards
   - QCOM updates for MSM8916
   - Rockchip tweaks for rk3368 SoC and eval board
   - A series of fixes for APM X-Gene v1 and v2
   - Renesas R8A7795 CPU/PSCI additions
   - Marvell Berlin4CT PSCI, cpuidle, watchdog portions
   - Freescale LS1043a SoC and dev board support

  + some treewide or other misc changes"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (104 commits)
  dts/ls2080a: Update DTSI to add support of SP805 WDT
  Documentation: DT: Add entry for ARM SP805-WDT
  arm64: dts: X-Gene v2: I2C1 clock is always on
  arm64: dts: X-Gene v1: I2C0 clock is always on
  arm64: dts: Fix to use standard DT node names for X-Gene 1 and X-Gene 2 platforms
  arm64: dts: hikey: add label properties to UARTs
  arm64: dts: apq8016-sbc: add label properties for UART, I2C, and SPI
  arm64: dts: apq8016-sbc: enable UART0 on LS connector
  arm64: dts: juno: Add idle-states to device tree
  arm64: dts: Added syscon-reboot node for FSL's LS2080A SoC
  arm64: dts: add LS1043a-RDB board support
  arm64: dts: add Freescale LS1043a SoC support
  Documentation: DT: Add entry for Freescale LS1043a-RDB board
  arm64: dts: uniphier: add PH1-LD10 SoC/board support
  arm64: renesas: r8a7795: fix SATA clock assignment
  arm64: dts: salvator-x: Enable SATA controller
  arm64: dts: r8a7795: Add SATA controller node
  arm64: renesas: r8a7795: add internal delay for i2c IPs
  arm64: renesas: salvator-x: Add board part number to DT bindings
  arm64: dts: r8a7795: Add pmu device nodes
  ...
2016-01-20 18:21:32 -08:00
yankejian
b70ce2ab41 dts: hisi: fixes no syscon fault when init mdio
When linux start up, we get the log below:
"Hi-HNS_MDIO 803c0000.mdio: no syscon hisilicon,peri-c-subctrl
mdio_bus mdio@803c0000: mdio sys ctl reg has not maped"

The source code about the subctrl is dealt syscon, but dts doesn't.
It cause such fault, so this patch adds the syscon info on dts files to
fixes it.

Signed-off-by: Kejian Yan <yankejian@huawei.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-01-15 14:40:03 -05:00
Rob Herring
dd90caaca2 arm64: dts: hikey: add label properties to UARTs
Add label properties to provide a way to identify UARTs based on their
board or connector name. This follows naming convention in 96boards CE
spec. Ports without external connections are not labelled.

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
2015-12-22 11:25:43 -08:00
Chen Feng
3e14cd4c04 arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC
Add reset controller for hi6220 hikey-board.

Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-11-20 15:41:46 +01:00
Linus Torvalds
c0d6fe2f01 ARM: DT updates for v4.4
As usual, this is the massive branch we have for each release. Lots of
 various updates and additions of hardware descriptions on existing hardware,
 as well as the usual additions of new boards and SoCs.
 
 This is also the first release where we've started mixing 64- and 32-bit
 DT updates in one branch.
 
 (Specific details on what's actually here and new is pretty easy to tell
 from the diffstat, so there's little point in duplicating listing it here.)
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJWQT2WAAoJEIwa5zzehBx37tgQAIBe5eDJFXFihTlyOQ2plL3q
 vVH4OCzXIHELfM1J8CGZNah1wCQqNOts8RAmDCzxr+zSYuLOwJOEDZ6NKmErMxl0
 NTj3+BsqKO3NRym970ofPqU9JRLQmpZ8K7dzk8Nwj2+r1WZHFu/j6Jv44n/Ns0lw
 7+wxnG322lTm7SnvALCMD5lD4Y7VpThooWy5SdFtRoAetn+cLbVCJIeeQvO6Vxkp
 NooeJR0t2e8cpbAND5Jwu6eeWRcIbrvgjYDe0omhrIY05i9yNvIsC2HuQFGjF43z
 p2CnQvcKnhOXTZw3yse1Fx5igA7jqwVjjC/lVeDyxhusAtLpmuB6qbSaj7DpqkSQ
 nJxX1d49WKm68K+aknmee1kYRrvc4DE/kORI4IxXnsVNMu16ifTVLnxKgUhwzukb
 eZdTP6rsqgNozaYvh0k1vfSFd+CNSkBg+E9nrI3tU95yo3LOIhobVBCvBcWlmUvQ
 JdavRztqosChjIx3a9i1eCNKJtCg9p4m+gWjUqVVWsxBHe/3HojzjZnsBSynIQMA
 uGIVm0TKhNl1Svxl3oJo9257UCUK7+5PqJHK9IHrcWDULYx05JGSjuZcyvNS6Fo+
 u1DMf0ud4gXJYhecFBa7b3zRjk5YxptgCCTjeEEOTUJbbhZqDjGFZlNuFi6dmqD3
 ILJ2QMe/DGiPIlUmCfsx
 =qY1q
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM DT updates from Olof Johansson:
 "As usual, this is the massive branch we have for each release.  Lots
  of various updates and additions of hardware descriptions on existing
  hardware, as well as the usual additions of new boards and SoCs.

  This is also the first release where we've started mixing 64- and
  32-bit DT updates in one branch.

  (Specific details on what's actually here and new is pretty easy to
  tell from the diffstat, so there's little point in duplicating listing
  it here)"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (499 commits)
  ARM: dts: uniphier: add system-bus-controller nodes
  ARM64: juno: disable NOR flash node by default
  ARM: dts: uniphier: add outer cache controller nodes
  arm64: defconfig: Enable PCI generic host bridge by default
  arm64: Juno: Add support for the PCIe host bridge on Juno R1
  Documentation: of: Document the bindings used by Juno R1 PCIe host bridge
  ARM: dts: uniphier: add I2C aliases for ProXstream2 boards
  dts/Makefile: Add build support for LS2080a QDS & RDB board DTS
  dts/ls2080a: Add DTS support for LS2080a QDS & RDB boards
  dts/ls2080a: Update Simulator DTS to add support of various peripherals
  dts/ls2080a: Remove text about writing to Free Software Foundation
  dts/ls2080a: Update DTSI to add support of various peripherals
  doc: DTS: Update DWC3 binding to provide reference to generic bindings
  doc/bindings: Update GPIO devicetree binding documentation for LS2080A
  Documentation/dts: Move FSL board-specific bindings out of /powerpc
  Documentation: DT: Add entry for FSL LS2080A QDS and RDB boards
  arm64: Rename FSL LS2085A SoC support code to LS2080A
  arm64: Use generic Layerscape SoC family naming
  ARM: dts: uniphier: add ProXstream2 Vodka board support
  ARM: dts: uniphier: add ProXstream2 Gentil board support
  ...
2015-11-10 15:06:26 -08:00
yankejian
6d08f61787 net: hisilicon: updates HNS config and documents
updates the bindings documents and dtsi file according to the review
comments[https://lkml.org/lkml/2015/9/21/670] from Rob Herring <robh@kernel.org>

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: yankejian <yankejian@huawei.com>
Signed-off-by: huangdaode <huangdaode@hisilicon.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2015-10-27 20:20:24 -07:00
Tyler Baker
a362ec8f67 arm64: dts: add all hi6220 uart nodes
This patch adds all UART nodes for the Hi6220 SoC. Recently a board[1] has
been developed to standardize UART access across all the 96boards consumer
edition boards. To use this hardware on HiKey we must configure and enable
UART3. However, to ensure backward compatibility we must keep UART0 enabled
as well.

I have removed the hard coded clock index values in favor of using the ones
already defined in include/dt-bindings/clock/hi6220-clock.h.

Since UART0 needs to be soldered, it has been suggested to use the UART3 as
the default console.

This patch was boot tested on top of next-20150930, with both UART
configurations.

[1] http://www.seeedstudio.com/depot/96Boards-UART-p-2525.html?ref=newInBazaar

Signed-off-by: Tyler Baker <tyler.baker@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-10-06 16:34:40 +02:00
Ding Tianhong
fcab303c01 arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board
Add initial dtsi file to support Hisilicon Hip05-D02 Board with
support of CPUs in four clusters and each cluster has quard Cortex-A57.

Also add dts file to support Hip05-D02 development board.

Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2015-09-21 15:50:50 +01:00
huangdaode
fc7e37c6b2 net: add Hisilicon Network Subsystem support (config and documents)
The Hisilicon Network Subsystem is a long term evolution IP which is
supposed to be used in Hisilicon ICT SoC. The IP, which is called hns
for short, is a TCP/IP acceleration engine, which can directly decode
TCP/IP stream and distribute them to different ring buffers.

HNS can be configured to work on different mode for different scenario.
This patch make use only some of the mode to make it as standard
ethernet NIC. The other mode will be added soon.

The whole function has 4 kernel sub-modules:

hnae: the HNS acceleration engine framework. It provides a abstract
interface between the engine and the upper layers which make use of the
engine by ring buffer.

hns_enet_drv: a standard ethernet driver that base on the ring buffer.

hns_dsaf: one of the implementation of HNS acceleration engine, which is
applied on Hililicon hip05, Hi1610 and other later-on SoCs

hns_mdio: the mdio control to the PHY, used by acceleration engine

This submit add basic config and documents

Signed-off-by: huangdaode <huangdaode@hisilicon.com>
Signed-off-by: Kenneth Lee <liguozhu@huawei.com>
Signed-off-by: Yisen Zhuang <Yisen.Zhuang@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2015-09-20 21:42:57 -07:00
Bintian Wang
86e8f528ef arm64: dts: Add dts files for Hisilicon Hi6220 SoC
Add initial dtsi file to support Hisilicon Hi6220 SoC with
support of Octal core CPUs in two clusters and each cluster
has quard Cortex-A53.

Also add dts file to support HiKey development board which
based on Hi6220 SoC.

Signed-off-by: Bintian Wang <bintian.wang@huawei.com>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Yiping Xu <xuyiping@hisilicon.com>
Tested-by: Will Deacon <will.deacon@arm.com>
Tested-by: Tyler Baker <tyler.baker@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2015-06-05 15:30:06 +01:00