AuxXxilium/linux_dsm_epyc7002
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dbb58d0f79
linux_dsm_epyc7002/arch/arm64/boot/dts/hisilicon
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Kefeng Wang dbb58d0f79 arm64: dts: hip05: Add L2 cache topology 
The Hip05 SoC has four L2 cache for all 16 CPUs, every four cpus
share one L2 cache, add them to the dtsi file so that the cache
hierarchy can be probed.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-02-25 21:15:58 +08:00
..
hi6220-hikey.dts arm64: dts: hikey: add label properties to UARTs 2015-12-22 11:25:43 -08:00
hi6220.dtsi arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC 2015-11-20 15:41:46 +01:00
hip05_hns.dtsi dts: hisi: fixes no syscon fault when init mdio 2016-01-15 14:40:03 -05:00
hip05-d02.dts arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board 2015-09-21 15:50:50 +01:00
hip05.dtsi arm64: dts: hip05: Add L2 cache topology 2016-02-25 21:15:58 +08:00
Makefile arm64: dts: add dts files for Hisilicon Hip05-D02 Development Board 2015-09-21 15:50:50 +01:00