Commit Graph

519215 Commits

Author SHA1 Message Date
Arnd Bergmann
1b0c509733 Merge branch 'irq/for-arm' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip into next/soc
* 'irq/for-arm' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip: vf610-mscm: Support NVIC parent chip
  irqchip: nvic: Support hierarchy irq domain
  genirq: generic chip: Support hierarchy domain
  genirq: Add irq_chip_(enable/disable)_parent
  irqdomain: Add non-hierarchy helper irq_domain_set_info
2015-05-20 23:09:12 +02:00
Arnd Bergmann
e2a604eb46 Merge tag 'arm-soc/for-4.2/maintainers' of http://github.com/broadcom/stblinux into next/soc
This pull request for the MAINTAINERS file contains the following changes:

- Brian adds a general "brcmstb" regexp to catch Broadcom Set Top Box related
  changes throughout the Linux tree

* tag 'arm-soc/for-4.2/maintainers' of http://github.com/broadcom/stblinux:
  MAINTAINERS: add brcmstb regex
2015-05-20 22:37:26 +02:00
Arnd Bergmann
e0f8864fb4 arm: Xilinx Zynq SoC patches for v4.2
- Change SoC reset path
 - Fix SLCR unlock scheme
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.10 (GNU/Linux)
 
 iEYEABECAAYFAlVZ47oACgkQykllyylKDCFw2gCfcaUI+Sy9ewZ5IvbFPa36Kr9e
 1JUAn28Ze85ddkUNw/3XxVywSXPre7Ie
 =eDcD
 -----END PGP SIGNATURE-----

Merge tag 'zynq-soc-for-4.2' of https://github.com/Xilinx/linux-xlnx into next/soc

Merge "arm: Xilinx Zynq SoC patches for v4.2" from Michal Simek:

- Change SoC reset path
- Fix SLCR unlock scheme

* tag 'zynq-soc-for-4.2' of https://github.com/Xilinx/linux-xlnx:
  ARM: zynq: Drop use of slcr_unlock in zynq_slcr_system_restart
  ARM: zynq: Use restart_handler mechanism for slcr reset
2015-05-20 17:41:15 +02:00
Arnd Bergmann
80f3e6557e ARM: uniphier: only select TWD for SMP
This makes uniphier behave like all the other platforms that
support TWD, and only select this driver when SMP is enabled.
Without this, we get a compile error on UP builds:

arch/arm/kernel/smp_twd.c: In function 'twd_local_timer_of_register':
arch/arm/kernel/smp_twd.c:391:20: error: 'setup_max_cpus' undeclared (first use in this function)

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-05-20 17:21:30 +02:00
Joachim Eastwood
0aed6a37b5 ARM: lpc18xx: define low-level debug symbol for LPC18xx/43xx
Using a dedicated symbol for low-level debugging instead of the
arch symbol will make this platform play nice when enabled on a
kernel that supports multiple platforms.

Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-20 17:20:39 +02:00
Joachim Eastwood
3143875f35 MAINTAINERS: Add entry for NXP LPC18xx/43xx MCUs
Add a MAINTAINER entry covering all NXP LPC18xx/43xx
machine and drivers files.

Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-20 17:20:07 +02:00
Stefan Agner
b5cc5cbc11 irqchip: vf610-mscm: Support NVIC parent chip
Support the NVIC interrupt controller as node parent of the MSCM
interrupt router. On the dual-core variants of Vybird (VF6xx), the
NVIC interrupt controller is used by the Cortex-M4. To support
running Linux on this core too, MSCM needs NVIC parent support too.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Cc: marc.zyngier@arm.com
Cc: linux@arm.linux.org.uk
Cc: u.kleine-koenig@pengutronix.de
Cc: olof@lixom.net
Cc: arnd@arndb.de
Cc: daniel.lezcano@linaro.org
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: ijc+devicetree@hellion.org.uk
Cc: galak@codeaurora.org
Cc: mcoquelin.stm32@gmail.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: shawn.guo@linaro.org
Cc: kernel@pengutronix.de
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/1431769465-26867-6-git-send-email-stefan@agner.ch
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-05-18 23:58:10 +02:00
Stefan Agner
2d9f59f7bf irqchip: nvic: Support hierarchy irq domain
Add support for hierarchy irq domains. This is required to stack
the MSCM interrupt router and the NVIC controller found in Vybrid
SoC.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Cc: marc.zyngier@arm.com
Cc: linux@arm.linux.org.uk
Cc: u.kleine-koenig@pengutronix.de
Cc: olof@lixom.net
Cc: arnd@arndb.de
Cc: daniel.lezcano@linaro.org
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: ijc+devicetree@hellion.org.uk
Cc: galak@codeaurora.org
Cc: mcoquelin.stm32@gmail.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: shawn.guo@linaro.org
Cc: kernel@pengutronix.de
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/1431769465-26867-5-git-send-email-stefan@agner.ch
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-05-18 17:32:44 +02:00
Stefan Agner
c5863484c1 genirq: generic chip: Support hierarchy domain
Use the new helper function irq_domain_set_info to make sure the
function irq_domain_set_hwirq_and_chip is being called, which is
crucial to save irqdomain specific data to irq_data.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Cc: marc.zyngier@arm.com
Cc: linux@arm.linux.org.uk
Cc: u.kleine-koenig@pengutronix.de
Cc: olof@lixom.net
Cc: arnd@arndb.de
Cc: daniel.lezcano@linaro.org
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: ijc+devicetree@hellion.org.uk
Cc: galak@codeaurora.org
Cc: mcoquelin.stm32@gmail.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: shawn.guo@linaro.org
Cc: kernel@pengutronix.de
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/1431769465-26867-4-git-send-email-stefan@agner.ch
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-05-18 17:32:44 +02:00
Stefan Agner
3cfeffc265 genirq: Add irq_chip_(enable/disable)_parent
Add helper irq_chip_enable_parent and irq_chip_disable_parent. The
helper implement the default behavior in case irq_enable or irq_disable
is not implemented for the parent interrupt chip, which is calling the
irq_mask or irq_unmask respectively.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Cc: marc.zyngier@arm.com
Cc: linux@arm.linux.org.uk
Cc: u.kleine-koenig@pengutronix.de
Cc: olof@lixom.net
Cc: arnd@arndb.de
Cc: daniel.lezcano@linaro.org
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: ijc+devicetree@hellion.org.uk
Cc: galak@codeaurora.org
Cc: mcoquelin.stm32@gmail.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: shawn.guo@linaro.org
Cc: kernel@pengutronix.de
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/1431769465-26867-3-git-send-email-stefan@agner.ch
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-05-18 17:32:44 +02:00
Stefan Agner
5f22f5c668 irqdomain: Add non-hierarchy helper irq_domain_set_info
This adds the helper irq_domain_set_info() in a non-domain hierarchy
variant. This allows to use the helper for generic chip since not
all chips using generic chip support domain hierarchy.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Cc: marc.zyngier@arm.com
Cc: linux@arm.linux.org.uk
Cc: u.kleine-koenig@pengutronix.de
Cc: olof@lixom.net
Cc: arnd@arndb.de
Cc: daniel.lezcano@linaro.org
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: ijc+devicetree@hellion.org.uk
Cc: galak@codeaurora.org
Cc: mcoquelin.stm32@gmail.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: shawn.guo@linaro.org
Cc: kernel@pengutronix.de
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/1431769465-26867-2-git-send-email-stefan@agner.ch
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-05-18 17:32:43 +02:00
Josh Cartwright
ef6ca1a84a ARM: zynq: Drop use of slcr_unlock in zynq_slcr_system_restart
The SLCR is unconditionally unlocked early on boot in zynq_slcr_init()
and not ever re-locked. As such, it is not necessary to explicitly unlock in
the restart codepath.

Signed-off-by: Josh Cartwright <joshc@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-05-18 14:46:37 +02:00
Josh Cartwright
64e6861760 ARM: zynq: Use restart_handler mechanism for slcr reset
By making use of the restart_handler chain mechanism, the SLCR-based
reset mechanism can be prioritized amongst other mechanisms available on
a particular board.

Choose a default high-ish priority of 192 for this restart mechanism.

Signed-off-by: Josh Cartwright <joshc@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-05-18 14:46:36 +02:00
Maxime Coquelin
ee6e7879a4 MAINTAINERS: Add entry for STM32 MCUs
Add a MAINTAINER entry covering all STM32 machine and drivers files.

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-15 21:51:38 +02:00
Jun Nie
5ecc4b5352 MAINTAINERS: add entry for ARM ZTE architecture
Add entry for ZTE ARM architecture

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-15 21:51:23 +02:00
Jun Nie
71bc724300 ARM: zx: enable SMP and hotplug for zx296702
Bring up the secondary core. Enable hotplug with supporting
powering off secondary core.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-15 21:49:51 +02:00
Jun Nie
58d0398535 ARM: zx: add low level debug support for zx296702
Use the UART0 peripheral for low level debug. Only the UART port 0 is
currently supported.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-15 21:49:27 +02:00
Jun Nie
acede515b3 ARM: zx: add basic support for ZTE ZX296702
Add basic code for ZTE ZX296702 platform.

[arnd: removed unused zx296702_init_machine function, and changed
       l2c aux val to default]

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-15 21:49:02 +02:00
Joachim Eastwood
e8d235d4d8 ARM: lpc18xx: add basic support for NXP LPC18xx/43xx SoCs
Add support for NXP's LPC18xx (Cortex-M3) and LPC43xx (Cortex-M4)
SoCs. These SoCs are NXP's high preformance MCU line and can run at
clock speeds up to 180 MHz for LPC18xx and 204 MHz for LPC43xx.

LPC43xx is more or less a LPC18xx with a Cortex-M4F core and a few
extra peripherals. The LPC43xx series also features one or two
Cortex-M0 cores that can be used to offload the main M4 core.

Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-15 21:43:56 +02:00
Maxime Coquelin
9b799b7837 ARM: Add STM32 family machine
STMicrolectronics's STM32 series is a family of Cortex-M
microcontrollers. It is used in various applications, and
proposes a wide range of peripherals.

Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-15 21:43:23 +02:00
Arnd Bergmann
7448adca93 This is the pxa changes for v4.2 cycle.
The main and only feature is the conversion of all pxa variants to clock
 framework. This encompasses pxa25x, pxa27x and pxa3xx, for all boards.
 
 This should be a disruptive cycle in the normally quiet pxa history, as
 the change can break any platform, and the test were performed on only 4
 boards (lubbock, zylonite, mioa701, cm-x300).
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJVU6BbAAoJEAP2et0duMsSBYYP/14D6mb8ayh9Arz4ewfihGBF
 7utbgdTHCJqhkAMVOgbBqogokrhLXdz/D7p2wWPE5CndDfyyGLhynzI0ZK3yLlTk
 GSIN99F/OsIpfZ4PpnZeWYe7YvMo3b6cB1uu0qCqLyxky/P8bu2zhTip15IKUWyq
 V5WLOpFVGX1FALkLqK0fzg9nwJnbojXRyDdgsAOhZVdTqr7jLR4O/e0RSPZIokBU
 tQ6gR/QnlHktTCIN5dVBatiTQDJrTR7sRvEfPfKCSaiC86QfCbiQZ2wXJp32rIvT
 kOrfBunvH6y1etgZXiAczwCWnQ2GmvG44i/HQ9wKQsBFrrXveuI18Z9CJTl3MKrO
 lDsD0sYZ1F0ufykfKCDgRZobhIdtoBG5jv3MLP7ZV1o07weWdtj+yy3Mb72ULX5I
 c0EjgWfx6KqqT1gYTNOgrarM+WJe00aqQlGP39AIzpcp9AwyrjuchvXb6kabKWo1
 wgPxtNw3I012qkPJ3ve/hi2Wwt7nfCst52r9l8ZKo/xHpbQ/HhUY/RciYygNMFsz
 7R4NqKhbYQvLjDQY8sCbgWxj8Q3loT54zqSDDUqXZAf/oLmxjafEHtbIr5nXxevk
 jygV+OSZwXDG7LXuJmFtYqsyWYU7Ow33BMyfWFJKuS1eJC/ZRDnkQUxLqCfkQiRC
 bIwbdTkKFrDHvyttbMn0
 =Gv7n
 -----END PGP SIGNATURE-----

Merge tag 'pxa-for-4.2' of https://github.com/rjarzmik/linux into next/soc

Merge "pxa changes for v4.2 cycle" from Robert Jarzmik:

The main and only feature is the conversion of all pxa variants to clock
framework. This encompasses pxa25x, pxa27x and pxa3xx, for all boards.

This should be a disruptive cycle in the normally quiet pxa history, as
the change can break any platform, and the test were performed on only 4
boards (lubbock, zylonite, mioa701, cm-x300).

* tag 'pxa-for-4.2' of https://github.com/rjarzmik/linux:
  ARM: pxa: Constify irq_domain_ops
  ARM: pxa: Transition pxa25x, pxa27x, pxa3xx to clk framework
  ARM: pxa: convert eseries to clock framework
  ARM: pxa: Transition pxa25x and pxa27x to clk framework
  ARM: pxa: pxa27x skip default device initialization with DT
  clk: pxa: add missing pxa27x clocks for Irda and sa1100-rtc
  ARM: pxa: move gpio11 clock to board files
  ARM: pxa: change clocks init sequence
2015-05-15 17:40:15 +02:00
Arnd Bergmann
e3abcb25d2 RaspberryPi SoC (mach) changes due for v4.2
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJVVGbzAAoJEFGvii+H/HdhXnsP/ihOP9xB24jBHgEWsZ9PaekZ
 YePv9Gxsxc9CvHIUJlWnwbvF/+Th+2Z2q2b2cAFjQutreEPYyi1g4HkhkVn/aXG7
 VgkBhdeSFwWX/VZAun/r3wZdzfzMKOHphoyejKAClAPSM2lQAYCdxCx+wzEFMMNv
 HtIeUCtpRaR+eycqkLMobhO0PO4BW4eIo8+F3cDHcAmR5q7MTmoHyFa9l/V/WjfK
 M0YV8a12m/8itfItzisloaFgMWOpxS6/8sUI7EEbD3dUK7XfCr0+rpzJ/ALNHrKr
 3V7StS1XOLxa7F1dKoi10r7SxSxaeXxmKTU84Y9YZSImeNBNdvtYs0E198jgA0mN
 OUkkd/6InhM3+5OCnNmwH2GAhQKbem+5lZgUu5W7hG3fyO1mMjZW7IxiqXgj4nGu
 6jlT5evdPTuvTw+1n5dC6AJtUrI40YRZDadtNLXBq/LqEsyO0+EcmVQlrsSTzrxS
 rxbSayXEQbwzL18L0iPC0KAFNm62VlG1eOcbdaFU2H0WK8wKimm+Hj9m9SkResfp
 npNT/bgLuuW+hUeuWAbzmqSuLxreWTFvt2N5801vdtG/tnX3nO9lNUYQH7Zj8u7s
 qZN391m6W5Mr+N6cMqMxKIFe+4Ea9o5eUmOX7g8KvGAzapRfOLdoPo3wR5vA04s3
 FEmDv7Ah4T2SpexAKq8U
 =TUcB
 -----END PGP SIGNATURE-----

Merge tag 'rpi-soc-for-armsoc-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi into next/soc

Merge "RaspberryPi SoC (mach) changes due for v4.2" from Lee Jones:

* tag 'rpi-soc-for-armsoc-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi:
  ARM: bcm2835: Move the restart/power_off handling to the WDT driver
  ARM: bcm2835: Drop the init_irq() hook
  ARM: bcm2835: Skip doing our own iotable_init() initialization
2015-05-15 17:38:05 +02:00
Eric Anholt
33a9f5bc15 ARM: bcm2835: Move the restart/power_off handling to the WDT driver
Since the WDT is what's used to drive restart and power off, it makes
more sense to keep it there, where the regs are already mapped and
definitions for them provided.  Note that this means you may need to
add CONFIG_BCM2835_WDT to retain functionality of your kernel.

Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2015-05-14 10:04:19 +01:00
Eric Anholt
ba9acf9c0f ARM: bcm2835: Drop the init_irq() hook
This is the default function that gets called if the hook is NULL.

Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2015-05-14 10:04:18 +01:00
Eric Anholt
2383321183 ARM: bcm2835: Skip doing our own iotable_init() initialization
The only thing we were using this 16MB mapping of IO peripherals for
was the uart's early debug mapping.  If we just drop the map_io hook,
the kernel will call debug_ll_io_init() for us, which maps the single
page needed for the device.

Signed-off-by: Eric Anholt <eric@anholt.net>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2015-05-14 10:04:17 +01:00
Brian Norris
5009a289cc MAINTAINERS: add brcmstb regex
This could probably consolidate a few file listings. And it satisfies
the spirit of the highly annoying [1] checkpatch warning for every new
file, though it sadly won't quash it.

[1] https://lkml.org/lkml/2014/12/17/24

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-05-13 10:53:32 -07:00
Arnd Bergmann
2516a932ef ARM: tegra: Core SoC changes for v4.2-rc1
A couple of changes to the core SoC support code. Perhaps the most
 important part is a fix for a regression in LP1 suspend/resume code that
 was introduced a while back.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABCAAGBQJVU1HFAAoJEN0jrNd/PrOhZNQP/ji9c+i3NPHn8Ll1bd9G8ppB
 Mv3SCjRqen1FVgrjuduGGlw+d6iJxVQvYM9tZ09ciFBLEsYzardiPpWeTau7stbn
 AKehXQQLoaj8ZZDJta09aLSjwddm9OkYGfceRykPnRoSRNDiWxGA71KXiYTN3TxZ
 A1mEJ7oIUZhZvltcriNeU9R/54/slLq00tPaD6XsH32l6GTdlS591mDgPBVia8TC
 HkcbXhutHInXtaP0IAaWHYrS2hp0Gy5/bIabKgjmK1bd1tBgf8g3hxe1YkUIaeWf
 j9F3Pb6SV54GSTV0p6hDsX/FnD7j9/ly3XQasdMp/+YOMCG+RfQjPhri2q32NIBm
 QDeG7BYUQJ8ktAFuGgOiwxpp9plTUBSMDDYOraHSJf2FVqH2NTlLkm9vamm5d6wb
 edlkyTmy5xeUCX4+hADgEbSTxSagXzSiZ4mLPtCL656ASwGriEg/HoyVnzHWNvJa
 6il5eEg6qaTYh2Ui+4z6BYZx8DQ8tQ51sg9lW/Y+QL71jopAHqS3wjnKJ/RlcePQ
 TD4tYhf6ALMLGZWGB/VYRwKPxYuI+owzf7P7mBzX0NtbY1PxsiQA2ximO7Y+XegE
 Ou2rO2lQVofH3WbzhfYgT4/+c0NtDpdI2FGsEMhsPYE3zLTyO+d8gsEQsI6oGkrU
 I/soe1xKK/4BZT6IZTP7
 =BR2n
 -----END PGP SIGNATURE-----

Merge tag 'tegra-for-4.2-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc

Merge "ARM: tegra: Core SoC changes for v4.2-rc1" from Thierry Reding:

A couple of changes to the core SoC support code. Perhaps the most
important part is a fix for a regression in LP1 suspend/resume code that
was introduced a while back.

* tag 'tegra-for-4.2-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: pmc: move to using a restart handler
  ARM: tegra20: Store CPU "resettable" status in IRAM
  soc/tegra: Watch wait_for_completion_timeout() return type
2015-05-13 18:01:18 +02:00
Arnd Bergmann
94db5b98d0 SoCFPGA updates for v4.2
- Add big endian support
 - Add earlyprintk support on UART1 that is used on Arria10
 - Remove the need to map uart_io_desc
 - Use of_iomap to map the SCU
 - Remove socfpga_smp_init_cpus as arm_dt_init_cpu_maps is already doing
   the CPU mapping.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABAgAGBQJVU1X6AAoJEBmUBAuBoyj0ixoP/3l2MxAxQt+SRz70y3ceFqx+
 IVbGpcDQdm7RohCFQVV7PVtpjm+RllYjjlRYWN/5/xfUEgjUgCiYlEPch+zFBDvA
 u9jpK7EdXHUYjAYmlti+Rw4jXXsYy+DzkZeMm6t/MlSj61exKW9iRU+/cdhXDyLx
 m81fGf+M8V/2xMIbHC6f/6xk2+a8WtTwCoh1FaCJLp+qkedQ4QOJPDjYSWBiubXH
 g7ydcuIiBpOuc57E1rzFWHeJgQu9VO+hLrNrazrfN/awbonPEL7hMJR2+odrDzHw
 wnwijqQCRDW1dZOAKNulH7h/9IzxjFyyIjdAbUF8ZplxIT0vtLbYPldd/435XJFX
 9VCUzVfAc0Vu5sfl3InbcRNoJDkCPavqcug1pYJkJlE8TeHcV8ylC7uzhWWrIRWa
 mzJq+j3p/E2pbvfv9YHccNaGRL4p9icN0eojM3fSwAlG9rAsDGFGNJH3Qb4tuwem
 H3MyhrIr9eveVBSkvz71sPy+ZHRL7EcPVFggpyXG2kNptb/K1P6cdDBO+mfl7ymM
 oVaKaGfpm3sCF9h/vLDWlsZUVF9eEsWO4qx5b0852T94WPkG+qg8p+MCYX2/7lGO
 41nKAWZpKRQj/9LvQpxlPnZSUhqcOPuHVVgMCDaXbwN9tGo7hJuaHpq4abElH3Ha
 h1lu5YGA9V0wf+zbK3S/
 =60ig
 -----END PGP SIGNATURE-----

Merge tag 'socfpga_updates_for_v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/soc

Merge "SoCFPGA updates for v4.2" from Dinh Nguyen:

- Add big endian support
- Add earlyprintk support on UART1 that is used on Arria10
- Remove the need to map uart_io_desc
- Use of_iomap to map the SCU
- Remove socfpga_smp_init_cpus as arm_dt_init_cpu_maps is already doing
  the CPU mapping.

* tag 'socfpga_updates_for_v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: socfpga: use of_iomap to map the SCU
  ARM: socfpga: remove the need to map uart_io_desc
  ARM: socfpga: Add support for UART1 debug uart for earlyprintk
  ARM: socfpga: support big endian for socfpga
  ARM: socfpga: enable big endian for secondary core(s)
  ARM: debug: fix big endian operation for 8250 word mode
2015-05-13 17:49:03 +02:00
Dinh Nguyen
122694a0c7 ARM: socfpga: use of_iomap to map the SCU
Use of_iomap to map the "arm,cortex-a9-scu". By doing this, we can remove
map_io in socfpga.c.

Also, we can remove socfpga_smp_init_cpus, as arm_dt_init_cpu_maps is
already doing the CPU mapping.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-13 08:41:35 -05:00
Krzysztof Kozlowski
64227114c6 ARM: pxa: Constify irq_domain_ops
The irq_domain_ops are not modified by the driver and the irqdomain core
code accepts pointer to a const data.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2015-05-12 23:26:46 +02:00
Robert Jarzmik
a1c0a6adbc ARM: pxa: Transition pxa25x, pxa27x, pxa3xx to clk framework
Transition the PXA25x, PXA27x and PXA3xx CPUs to the clock framework.
This transition still enables legacy platforms to run without device
tree as before, ie relying on platform data encoded in board specific
files.

This is the last step of clock framework transition for pxa
platforms. It was tested on lubbock (pxa25x), mioa701 (pxa27x) and
zylonite (pxa3xx).

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2015-05-12 23:26:46 +02:00
Robert Jarzmik
8e3afafe99 ARM: pxa: convert eseries to clock framework
As pxa architecture transitions to clock framework, the previously
available INIT_CLKREG is no more. Use the fixed clock rate initializer
to declare the "fake" CLK_CK32K in eseries.

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2015-05-12 23:26:45 +02:00
Robert Jarzmik
48a17db28c ARM: pxa: Transition pxa25x and pxa27x to clk framework
Transition the PXA25x and PXA27x CPUs to the clock framework.
This transition still enables legacy platforms to run without device
tree as before, ie relying on platform data encoded in board specific
files.

The transition breaks the previous clocks activation of pin
control (gpio11 and gpio12). Machine files should be amended to take
that into account.

This is the last step of clock framework transition for pxa25x and
pxa27x, leaving only pxa3xx for further work.

Reviewed-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2015-05-12 23:26:40 +02:00
Robert Jarzmik
24e32a5528 ARM: pxa: pxa27x skip default device initialization with DT
When booting via DT, the default PXA devices must not have been probed
before, otherwise the augmented information from the device tree is
ignored.

This is the twin commit of commit 82ce44d104 ("ARM: pxa3xx: skip
default device initialization when booting via DT").

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Daniel Mack <daniel@zonque.org>
2015-05-12 23:26:39 +02:00
Robert Jarzmik
8b6d10345e clk: pxa: add missing pxa27x clocks for Irda and sa1100-rtc
Add 2 clocks which were erronously forgotten by the clock framework
port, namely :
 - sa1100-rtc
 - irda for pxa2xx-ir:UARTCLK

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Michael Turquette <mturquette@linaro.org>
2015-05-12 23:26:39 +02:00
Robert Jarzmik
70d64048c4 ARM: pxa: move gpio11 clock to board files
The pxa25x gpio11 clock output was previously selected on its pin by the
clock enabling, toggling the pin function.

As we transition to common clock framework, the pin function is moved to
board file for the 2 users, ie. lubbock and eseries.

Reviewed-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2015-05-12 23:26:32 +02:00
Robert Jarzmik
5e1d012851 ARM: pxa: change clocks init sequence
Since pxa clocks were ported to the clock framework, an ordering issue
appears between clocks and clocksource initialization. As a consequence,
the pxa timer clock cannot be acquired in pxa_timer, and is disabled by
clock framework because it is "unused".

The ordering issue is that in the kernel boot sequence :
  start_kernel()
    ...
    time_init()
      -> pxa_timer()
        -> here the clocksource is initialized
    ...
    rest_init()
      kernel_init()
	initcalls
	  -> here the clocks are initialized

In the current sequence, the clocks are initialized way after pxa_timer,
which cannot acquire the OSTIMER0 clock.

To solve this issue, the clocks initialization is moved to pxa_timer(),
so that clocks are initialized before clocksource for non device-tree.
For device-tree, the standard arm time_init() will take care of the
ordering.

Reviewed-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2015-05-12 23:26:25 +02:00
Arnd Bergmann
73e601ea57 Allwinner core additions for 4.2
This pull request contains only the changes needed to support the SMP on
 the Allwinner A23.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJVUQFvAAoJEBx+YmzsjxAgzZEQAIvJbHSZKtuI7gVgD+74oa7A
 yigsnhdoOTMtWlgWWZHuN56CjEZNSosZoa9NLJhEDBAPEbDr74SoegW7knW6/xkD
 B6s/TV4zGCciZ6AWa7zJEwwvibzdhw+9fGTIWZ4ZLr5fiaPPOE4jN3+O2Cu/oydC
 7kD0buhh2QJpQp9ryy8L0S9pafAp8iBaux2zP1xZElG0s52xyNKtZlKD7B8SywFH
 UFhJmjhL0Fq7APi1SUtLbESyIZWmvgE7G8Oh9l/N7VXnkb6R4eiKb/Q3QO8FXpKh
 qO26A0k5cPtnAwMCYbXWimGh/X/2bY+eY8YPa/yUj19Pz770kT6loZRhvGEmkhDy
 aSbJFC49/sco9FIkgNMNNFyPi6rCsrmj4CGOI67cDqomARUCxiQmg3Lr71NS5rtN
 m6drF/6B9EzDochK9k/P/uAW0I/HJtR9Lbh/TZYLEb0SbL+j+s4s7iFhHhI3S0zh
 hB9mfWvbse+2vLyjyoyT58igZAf9gg/QJFnHWDFPAc3D15zxg9xQObGQ68d6CNDB
 1OvjDUBCwQBOdRQgFW2YUl70lm7Sm/rDFvWR/cY6+9QSEBeDeEglP0ji+BdHynAl
 QPdUiiTs5tuz6WtLDX3mRYGfocUCRbPxPQ2BNZtn9gpAx4N9eCDQQuX3f937Ur9F
 zMhuV7zfQ3X87beuUMWx
 =RNcV
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-core-for-4.2' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/soc

Merge "Allwinner core additions for 4.2" from Maxime Ripard:

This pull request contains only the changes needed to support the SMP on
the Allwinner A23.

* tag 'sunxi-core-for-4.2' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
  ARM: sun8i: Add SMP support for the Allwinner A23
2015-05-12 22:04:54 +02:00
Masahiro Yamada
3d00d04f60 MAINTAINERS: add myself as ARM/UniPhier maintainer
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-12 16:56:09 +02:00
Masahiro Yamada
ba56a9876d ARM: UniPhier: add basic support for UniPhier architecture
Initial commit for a new SoC family, UniPhier, developed by
Socionext Inc. (formerly, System LSI Business Division of
Panasonic Corporation).

This commit includes a minimal set of components for booting the
kernel, including SMP support.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-12 16:55:37 +02:00
Dinh Nguyen
65ce7a37ec ARM: socfpga: remove the need to map uart_io_desc
All the necessary debug uart mapping is already being done in
debug_ll_io_init, there's no need for it here.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11 13:59:53 -05:00
Dinh Nguyen
de73c162fc ARM: socfpga: Add support for UART1 debug uart for earlyprintk
Add support for hardware uart1 for earlyprintk support on Arria10 devkit.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11 13:59:52 -05:00
Ben Dooks
3c5ac3f392 ARM: socfpga: support big endian for socfpga
Now the debug and platsmp.S are fixed for big endian, the
architecture can now advertise big endian support.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11 13:59:23 -05:00
Ben Dooks
bf55e0a48f ARM: socfpga: enable big endian for secondary core(s)
Update the secondary code to allow the secondary boot to work when the
system is running big endian.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11 13:59:23 -05:00
Ben Dooks
6ef4e47926 ARM: debug: fix big endian operation for 8250 word mode
If the 8250 debug code is used in word mode on an big endian
host then the writes need to be change into little endian for
the bus.

Note, we have to re-convert the value back as the debug code
will inspect the value after writing it to see if a newline
has been written.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11 13:59:23 -05:00
Linus Torvalds
030bbdbf4c Linux 4.1-rc3 2015-05-10 15:12:29 -07:00
Linus Torvalds
01d07351f2 Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
 "I really need to get back to sending these on my Friday, instead of my
  Monday morning, but nothing too amazing in here: a few amdkfd fixes, a
  few radeon fixes, i915 fixes, one tegra fix and one core fix"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
  drm: Zero out invalid vblank timestamp in drm_update_vblank_count.
  drm/tegra: Don't use vblank_disable_immediate on incapable driver.
  drm/radeon: stop trying to suspend UVD sessions
  drm/radeon: more strictly validate the UVD codec
  drm/radeon: make UVD handle checking more strict
  drm/radeon: make VCE handle check more strict
  drm/radeon: fix userptr lockup
  drm/radeon: fix userptr BO unpin bug v3
  drm/amdkfd: Initialize sdma vm when creating sdma queue
  drm/amdkfd: Don't report local memory size
  drm/amdkfd: allow unregister process with queues
  drm/i915: Drop PIPE-A quirk for 945GSE HP Mini
  drm/i915: Sink rate read should be saved in deca-kHz
  drm/i915/dp: there is no audio on port A
  drm/i915: Add missing MacBook Pro models with dual channel LVDS
  drm/i915: Assume dual channel LVDS if pixel clock necessitates it
  drm/radeon: don't setup audio on asics that don't support it
  drm/radeon: disable semaphores for UVD V1 (v2)
2015-05-10 14:58:53 -07:00
Dave Airlie
332545b301 Merge tag 'drm-intel-fixes-2015-05-08' of git://anongit.freedesktop.org/drm-intel into drm-fixes
misc i915 fixes.

* tag 'drm-intel-fixes-2015-05-08' of git://anongit.freedesktop.org/drm-intel:
  drm/i915: Drop PIPE-A quirk for 945GSE HP Mini
  drm/i915: Sink rate read should be saved in deca-kHz
  drm/i915/dp: there is no audio on port A
  drm/i915: Add missing MacBook Pro models with dual channel LVDS
  drm/i915: Assume dual channel LVDS if pixel clock necessitates it
2015-05-11 06:06:22 +10:00
Mario Kleiner
fdb68e09bb drm: Zero out invalid vblank timestamp in drm_update_vblank_count.
Since commit 844b03f277 we make
sure that after vblank irq off, we return the last valid
(vblank count, vblank timestamp) pair to clients, e.g., during
modesets, which is good.

An overlooked side effect of that commit for kms drivers without
support for precise vblank timestamping is that at vblank irq
enable, when we update the vblank counter from the hw counter, we
can't update the corresponding vblank timestamp, so now we have a
totally mismatched timestamp for the new count to confuse clients.

Restore old client visible behaviour from before Linux 3.17, but
zero out the timestamp at vblank counter update (instead of disable
as in original implementation) if we can't generate a meaningful
timestamp immediately for the new vblank counter. This will fix
this regression, so callers know they need to retry again later
if they need a valid timestamp, but at the same time preserves
the improvements made in the commit mentioned above.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: <stable@vger.kernel.org> #v3.17+

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-05-11 06:02:38 +10:00
Linus Torvalds
41f2a93cc6 Merge branch 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm
Pull ARM fixes from Russell King:
 "A set of ARM fixes:

   - fix an off-by-one error in the iommu DMA ops, which caused errors
     with a 4GiB size.

   - remove comments mentioning the non-existent CONFIG_CPU_ARM1020_CPU_IDLE
     macro.

   - remove useless CONFIG_CPU_ICACHE_STREAMING_DISABLE blocks, where
     this symbol never appeared in any Kconfig.

   - fix Feroceon code to cope with a previous change correctly (it
     incorrectly left an additional word in an assembly structure
     definition)

   - avoid a misleading IRQ affinity warning in the ARM PMU code for
     IRQs which are already affine to their CPUs.

   - fix the node name printed in the IRQ affinity warning"

* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
  ARM: 8352/1: perf: Fix the pmu node name in warning message
  ARM: 8351/1: perf: don't warn about missing interrupt-affinity property for PPIs
  ARM: 8350/1: proc-feroceon: Fix feroceon_proc_info macro
  ARM: 8349/1: arch/arm/mm/proc-arm925.S: remove dead #ifdef block
  ARM: 8348/1: remove comments on CPU_ARM1020_CPU_IDLE
  ARM: 8347/1: dma-mapping: fix off-by-one check in arm_setup_iommu_dma_ops
2015-05-10 11:16:48 -07:00