Commit Graph

11526 Commits

Author SHA1 Message Date
Linus Torvalds
d47ebd6842 ARM: SoC defconfig updates for v5.4
As usual, a bunch of commits, mostly adding drivers and other
 options to defconfigs after the code was merged through another
 tree.
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'armsoc-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC defconfig updates from Arnd Bergmann:
 "As usual, a bunch of commits, mostly adding drivers and other options
  to defconfigs after the code was merged through another tree"

* tag 'armsoc-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (32 commits)
  arm64: defconfig: Enable Qualcomm QUSB2 PHY
  arm64: defconfig: Enable the EFI Framebuffer
  arm64: defconfig: Enable Qualcomm GENI based I2C controller
  ARM: multi_v7_defconfig: Make MAX77802 regulator driver built-in
  arm64: defconfig: Enable CPU clock drivers for Qualcomm msm8916
  arm64: defconfig: Add DRM_MSM to defconfigs with ARCH_QCOM
  ARM: multi_v7_defconfig: Add DRM_MSM to defconfigs with ARCH_QCOM
  ARM: qcom_defconfig: Add DRM_MSM to defconfigs with ARCH_QCOM
  ARM: configs: aspeed_g5: Enable AST2600
  ARM: configs: multi_v7: Add ASPEED G6
  arm64: defconfig: Enable SM8150 GCC and pinctrl driver
  arm64: defconfig: Enable CONFIG_ACPI_APEI_PCIEAER
  arm64: defconfig: Enable the DesignWare watchdog
  ARM: multi_v7_defconfig: Enable SPI_STM32_QSPI support
  ARM: imx_v6_v7_defconfig: Enable the PSCI CPUidle driver
  arm64: defconfig: Enable the PSCI CPUidle driver
  arm64: defconfig: Enable Sun4i SPDIF module
  ARM: exynos_defconfig: Enable AHCI-platform SATA driver
  arm64: defconfig: CONFIG_DRM_ETNAVIV=m
  ARM: imx_v6_v7_defconfig: Select the OV5645 camera driver
  ...
2019-09-16 15:55:06 -07:00
Linus Torvalds
2b97c39514 ARM: SoC platform updates for v5.4
The main change this time around is a cleanup of some of the oldest
 platforms based on the XScale and ARM9 CPU cores, which are between 10
 and 20 years old.
 
 The Kendin/Micrel/Microchip KS8695, Winbond/Nuvoton W90x900 and Intel
 IOP33x/IOP13xx platforms are removed after we determined that nobody is
 using them any more.
 
 The TI Davinci and NXP LPC32xx platforms on the other hand are still in
 active use and are converted to the ARCH_MULTIPLATFORM build, meaning
 that we can compile a kernel that works on these along with most other
 ARMv5 platforms. Changes toward that goal are also merged for IOP32x,
 but additional work is needed to complete this. Patches for the
 remaining ARMv5 platforms have started but need more work and some
 testing.
 
 Support for the new ASpeed AST2600 gets added, this is based on the
 Cortex-A7 ARMv7 core, and is a newer version of the existing ARMv5 and
 ARMv6 chips in the same family.
 
 Other changes include a cleanup of the ST-Ericsson ux500 platform
 and the move of the TI Davinci platform to a new clocksource driver.
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC platform updates from Arnd Bergmann:
 "The main change this time around is a cleanup of some of the oldest
  platforms based on the XScale and ARM9 CPU cores, which are between 10
  and 20 years old.

  The Kendin/Micrel/Microchip KS8695, Winbond/Nuvoton W90x900 and Intel
  IOP33x/IOP13xx platforms are removed after we determined that nobody
  is using them any more.

  The TI Davinci and NXP LPC32xx platforms on the other hand are still
  in active use and are converted to the ARCH_MULTIPLATFORM build,
  meaning that we can compile a kernel that works on these along with
  most other ARMv5 platforms. Changes toward that goal are also merged
  for IOP32x, but additional work is needed to complete this. Patches
  for the remaining ARMv5 platforms have started but need more work and
  some testing.

  Support for the new ASpeed AST2600 gets added, this is based on the
  Cortex-A7 ARMv7 core, and is a newer version of the existing ARMv5 and
  ARMv6 chips in the same family.

  Other changes include a cleanup of the ST-Ericsson ux500 platform and
  the move of the TI Davinci platform to a new clocksource driver"

[ The changes had marked INTEL_IOP_ADMA and USB_LPC32XX as being
  buildable on other platforms through COMPILE_TEST, but that causes new
  warnings that I most definitely do not want to see during the merge
  window as that could hide other issues.

  So the COMPILE_TEST option got disabled for them again   - Linus ]

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (61 commits)
  ARM: multi_v5_defconfig: make DaVinci part of the ARM v5 multiplatform build
  ARM: davinci: support multiplatform build for ARM v5
  arm64: exynos: Enable exynos-chipid driver
  ARM: OMAP2+: Delete an unnecessary kfree() call in omap_hsmmc_pdata_init()
  ARM: OMAP2+: move platform-specific asm-offset.h to arch/arm/mach-omap2
  ARM: davinci: dm646x: Fix a typo in the comment
  ARM: davinci: dm646x: switch to using the clocksource driver
  ARM: davinci: dm644x: switch to using the clocksource driver
  ARM: aspeed: Enable SMP boot
  ARM: aspeed: Add ASPEED AST2600 architecture
  ARM: aspeed: Select timer in each SoC
  dt-bindings: arm: cpus: Add ASPEED SMP
  ARM: imx: stop adjusting ar8031 phy tx delay
  mailmap: map old company name to new one @microchip.com
  MAINTAINERS: at91: remove the TC entry
  MAINTAINERS: at91: Collect all pinctrl/gpio drivers in same entry
  ARM: at91: move platform-specific asm-offset.h to arch/arm/mach-at91
  MAINTAINERS: Extend patterns for Samsung SoC, Security Subsystem and clock drivers
  ARM: s3c64xx: squash samsung_usb_phy.h into setup-usb-phy.c
  ARM: debug-ll: Add support for r7s9210
  ...
2019-09-16 15:48:14 -07:00
Linus Torvalds
e77fafe9af arm64 updates for 5.4:
- 52-bit virtual addressing in the kernel
 
 - New ABI to allow tagged user pointers to be dereferenced by syscalls
 
 - Early RNG seeding by the bootloader
 
 - Improve robustness of SMP boot
 
 - Fix TLB invalidation in light of recent architectural clarifications
 
 - Support for i.MX8 DDR PMU
 
 - Remove direct LSE instruction patching in favour of static keys
 
 - Function error injection using kprobes
 
 - Support for the PPTT "thread" flag introduced by ACPI 6.3
 
 - Move PSCI idle code into proper cpuidle driver
 
 - Relaxation of implicit I/O memory barriers
 
 - Build with RELR relocations when toolchain supports them
 
 - Numerous cleanups and non-critical fixes
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Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 updates from Will Deacon:
 "Although there isn't tonnes of code in terms of line count, there are
  a fair few headline features which I've noted both in the tag and also
  in the merge commits when I pulled everything together.

  The part I'm most pleased with is that we had 35 contributors this
  time around, which feels like a big jump from the usual small group of
  core arm64 arch developers. Hopefully they all enjoyed it so much that
  they'll continue to contribute, but we'll see.

  It's probably worth highlighting that we've pulled in a branch from
  the risc-v folks which moves our CPU topology code out to where it can
  be shared with others.

  Summary:

   - 52-bit virtual addressing in the kernel

   - New ABI to allow tagged user pointers to be dereferenced by
     syscalls

   - Early RNG seeding by the bootloader

   - Improve robustness of SMP boot

   - Fix TLB invalidation in light of recent architectural
     clarifications

   - Support for i.MX8 DDR PMU

   - Remove direct LSE instruction patching in favour of static keys

   - Function error injection using kprobes

   - Support for the PPTT "thread" flag introduced by ACPI 6.3

   - Move PSCI idle code into proper cpuidle driver

   - Relaxation of implicit I/O memory barriers

   - Build with RELR relocations when toolchain supports them

   - Numerous cleanups and non-critical fixes"

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (114 commits)
  arm64: remove __iounmap
  arm64: atomics: Use K constraint when toolchain appears to support it
  arm64: atomics: Undefine internal macros after use
  arm64: lse: Make ARM64_LSE_ATOMICS depend on JUMP_LABEL
  arm64: asm: Kill 'asm/atomic_arch.h'
  arm64: lse: Remove unused 'alt_lse' assembly macro
  arm64: atomics: Remove atomic_ll_sc compilation unit
  arm64: avoid using hard-coded registers for LSE atomics
  arm64: atomics: avoid out-of-line ll/sc atomics
  arm64: Use correct ll/sc atomic constraints
  jump_label: Don't warn on __exit jump entries
  docs/perf: Add documentation for the i.MX8 DDR PMU
  perf/imx_ddr: Add support for AXI ID filtering
  arm64: kpti: ensure patched kernel text is fetched from PoU
  arm64: fix fixmap copy for 16K pages and 48-bit VA
  perf/smmuv3: Validate groups for global filtering
  perf/smmuv3: Validate group size
  arm64: Relax Documentation/arm64/tagged-pointers.rst
  arm64: kvm: Replace hardcoded '1' with SYS_PAR_EL1_F
  arm64: mm: Ignore spurious translation faults taken from the kernel
  ...
2019-09-16 14:31:40 -07:00
David S. Miller
aa2eaa8c27 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
Minor overlapping changes in the btusb and ixgbe drivers.

Signed-off-by: David S. Miller <davem@davemloft.net>
2019-09-15 14:17:27 +02:00
Andrey Smirnov
007b3cf0af arm64: dts: imx8mq: Add CAAM node
Add node for CAAM - Cryptographic Acceleration and Assurance Module.

Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Cory Tusar <cory.tusar@zii.aero>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Iuliana Prodan <iuliana.prodan@nxp.com>
Cc: linux-crypto@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-09-13 21:15:38 +10:00
Christoph Hellwig
5489c8e0cf arm64: use asm-generic/dma-mapping.h
Now that the Xen special cases are gone nothing worth mentioning is
left in the arm64 <asm/dma-mapping.h> file, so switch to use the
asm-generic version instead.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Will Deacon <will@kernel.org>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
2019-09-11 12:43:27 +02:00
Christoph Hellwig
0e0d26e779 xen/arm: remove xen_dma_ops
arm and arm64 can just use xen_swiotlb_dma_ops directly like x86, no
need for a pointer indirection.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
2019-09-11 12:43:26 +02:00
Christoph Hellwig
a8e6d950cd xen/arm: use dev_is_dma_coherent
Use the dma-noncoherent dev_is_dma_coherent helper instead of the home
grown variant.  Note that both are always initialized to the same
value in arch_setup_dma_ops.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
2019-09-11 12:43:26 +02:00
Christoph Hellwig
bef4d2037d xen/arm: consolidate page-coherent.h
Shared the duplicate arm/arm64 code in include/xen/arm/page-coherent.h.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
2019-09-11 12:43:22 +02:00
Marc Zyngier
084b5a80e8 arm64: KVM: Kill hyp_alternate_select()
hyp_alternate_select() is now completely unused. Goodbye.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
2019-09-09 18:16:32 +01:00
Marc Zyngier
aa979fa899 arm64: KVM: Replace hyp_alternate_select with has_vhe()
Given that the TLB invalidation path is pretty rarely used, there
was never any advantage to using hyp_alternate_select() here.
has_vhe(), being a glorified static key, is the right tool for
the job.

Off you go.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
2019-09-09 18:16:32 +01:00
Marc Zyngier
b6749e20d5 arm64: KVM: Drop hyp_alternate_select for checking for ARM64_WORKAROUND_834220
There is no reason for using hyp_alternate_select when checking
for ARM64_WORKAROUND_834220, as each of the capabilities is
also backed by a static key. Just replace the KVM-specific
construct with cpus_have_const_cap(ARM64_WORKAROUND_834220).

Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
2019-09-09 18:16:32 +01:00
Marc Zyngier
92f35b751c KVM: arm/arm64: vgic: Allow more than 256 vcpus for KVM_IRQ_LINE
While parts of the VGIC support a large number of vcpus (we
bravely allow up to 512), other parts are more limited.

One of these limits is visible in the KVM_IRQ_LINE ioctl, which
only allows 256 vcpus to be signalled when using the CPU or PPI
types. Unfortunately, we've cornered ourselves badly by allocating
all the bits in the irq field.

Since the irq_type subfield (8 bit wide) is currently only taking
the values 0, 1 and 2 (and we have been careful not to allow anything
else), let's reduce this field to only 4 bits, and allocate the
remaining 4 bits to a vcpu2_index, which acts as a multiplier:

  vcpu_id = 256 * vcpu2_index + vcpu_index

With that, and a new capability (KVM_CAP_ARM_IRQ_LINE_LAYOUT_2)
allowing this to be discovered, it becomes possible to inject
PPIs to up to 4096 vcpus. But please just don't.

Whilst we're there, add a clarification about the use of KVM_IRQ_LINE
on arm, which is not completely conditionned by KVM_CAP_IRQCHIP.

Reported-by: Zenghui Yu <yuzenghui@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
2019-09-09 12:29:09 +01:00
Ard Biesheuvel
67cfa5d3b7 crypto: arm64/aes-neonbs - implement ciphertext stealing for XTS
Update the AES-XTS implementation based on NEON instructions so that it
can deal with inputs whose size is not a multiple of the cipher block
size. This is part of the original XTS specification, but was never
implemented before in the Linux kernel.

Since the bit slicing driver is only faster if it can operate on at
least 7 blocks of input at the same time, let's reuse the alternate
path we are adding for CTS to process any data tail whose size is
not a multiple of 128 bytes.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-09-09 17:35:39 +10:00
Ard Biesheuvel
7cceca8b25 crypto: arm64/aes - implement support for XTS ciphertext stealing
Add the missing support for ciphertext stealing in the implementation
of AES-XTS, which is part of the XTS specification but was omitted up
until now due to lack of a need for it.

The asm helpers are updated so they can deal with any input size, as
long as the last full block and the final partial block are presented
at the same time. The glue code is updated so that the common case of
operating on a sector or page is mostly as before. When CTS is needed,
the walk is split up into two pieces, unless the entire input is covered
by a single step.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-09-09 17:35:39 +10:00
Ard Biesheuvel
7c9d65c40a crypto: arm64/aes-cts-cbc - move request context data to the stack
Since the CTS-CBC code completes synchronously, there is no point in
keeping part of the scratch data it uses in the request context, so
move it to the stack instead.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-09-09 17:35:39 +10:00
Ard Biesheuvel
0cfd507c83 crypto: arm64/aes-cts-cbc-ce - performance tweak
Optimize away one of the tbl instructions in the decryption path,
which turns out to be unnecessary.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-09-09 17:35:38 +10:00
Ard Biesheuvel
69b6f2e817 crypto: arm64/aes-neon - limit exposed routines if faster driver is enabled
The pure NEON AES implementation predates the bit-slicing one, and is
generally slower, unless the algorithm in question can only execute
sequentially.

So advertising the skciphers that the bit-slicing driver implements as
well serves no real purpose, and we can just disable them. Note that the
bit-slicing driver also has a link time dependency on the pure NEON
driver, for CBC encryption and for XTS tweak calculation, so we still
need both drivers on systems that do not implement the Crypto Extensions.

At the same time, expose those modaliases for the AES instruction based
driver. This is necessary since otherwise, we may end up loading the
wrong driver when any of the skciphers are instantiated before the CPU
capability based module loading has completed.

Finally, add the missing modalias for cts(cbc(aes)) so requests for
this algorithm will autoload the correct module.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-09-09 17:35:38 +10:00
Ard Biesheuvel
7a3b1c6ee7 crypto: arm64/aes-neonbs - replace tweak mask literal with composition
Replace the vector load from memory sequence with a simple instruction
sequence to compose the tweak vector directly.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-09-09 17:35:28 +10:00
zhong jiang
7b865ec15e crypto: arm64/aes - Use PTR_ERR_OR_ZERO rather than its implementation.
PTR_ERR_OR_ZERO contains if(IS_ERR(...)) + PTR_ERR. It is better to
use it directly. hence just replace it.

Signed-off-by: zhong jiang <zhongjiang@huawei.com>
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-09-09 17:35:27 +10:00
Bjorn Andersson
3e303a42a3 scsi: arm64: dts: qcom: sdm845: Specify UFS device-reset GPIO
Specify the UFS device-reset gpio for db845c and mtp, so that the
controller will issue a reset of the UFS device.

Link: https://lore.kernel.org/r/20190828191756.24312-4-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Avri Altman <Avri.Altman@wdc.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2019-09-07 16:36:03 -04:00
David S. Miller
1e46c09ec1 Merge git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next
Daniel Borkmann says:

====================
The following pull-request contains BPF updates for your *net-next* tree.

The main changes are:

1) Add the ability to use unaligned chunks in the AF_XDP umem. By
   relaxing where the chunks can be placed, it allows to use an
   arbitrary buffer size and place whenever there is a free
   address in the umem. Helps more seamless DPDK AF_XDP driver
   integration. Support for i40e, ixgbe and mlx5e, from Kevin and
   Maxim.

2) Addition of a wakeup flag for AF_XDP tx and fill rings so the
   application can wake up the kernel for rx/tx processing which
   avoids busy-spinning of the latter, useful when app and driver
   is located on the same core. Support for i40e, ixgbe and mlx5e,
   from Magnus and Maxim.

3) bpftool fixes for printf()-like functions so compiler can actually
   enforce checks, bpftool build system improvements for custom output
   directories, and addition of 'bpftool map freeze' command, from Quentin.

4) Support attaching/detaching XDP programs from 'bpftool net' command,
   from Daniel.

5) Automatic xskmap cleanup when AF_XDP socket is released, and several
   barrier/{read,write}_once fixes in AF_XDP code, from Björn.

6) Relicense of bpf_helpers.h/bpf_endian.h for future libbpf
   inclusion as well as libbpf versioning improvements, from Andrii.

7) Several new BPF kselftests for verifier precision tracking, from Alexei.

8) Several BPF kselftest fixes wrt endianess to run on s390x, from Ilya.

9) And more BPF kselftest improvements all over the place, from Stanislav.

10) Add simple BPF map op cache for nfp driver to batch dumps, from Jakub.

11) AF_XDP socket umem mapping improvements for 32bit archs, from Ivan.

12) Add BPF-to-BPF call and BTF line info support for s390x JIT, from Yauheni.

13) Small optimization in arm64 JIT to spare 1 insns for BPF_MOD, from Jerin.

14) Fix an error check in bpf_tcp_gen_syncookie() helper, from Petar.

15) Various minor fixes and cleanups, from Nathan, Masahiro, Masanari,
    Peter, Wei, Yue.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
2019-09-06 16:49:17 +02:00
Arnd Bergmann
13212a648f Second Round of Renesas ARM Based SoC Fixes for v5.3
* RZ/G2M based HiHope main board
   - Re-enabled accidently disabled SDHI3 (eMMC) support
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Merge tag 'renesas-fixes2-for-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/fixes

Second Round of Renesas ARM Based SoC Fixes for v5.3

* RZ/G2M based HiHope main board
  - Re-enabled accidently disabled SDHI3 (eMMC) support

* tag 'renesas-fixes2-for-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: dts: renesas: hihope-common: Fix eMMC status

Link: https://lore.kernel.org/r/cover.1567675986.git.horms+renesas@verge.net.au
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-05 17:56:30 +02:00
Bjorn Andersson
44acee2078 arm64: dts: qcom: Add Lenovo Yoga C630
The Lenovo Yoga C630 is built on the SDM850 from Qualcomm, but this seem
to be similar enough to the SDM845 that we can reuse the sdm845.dtsi.

Supported by this patch is: keyboard, battery monitoring, UFS storage,
USB host and Bluetooth.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
[Lee] Reorder, change licence, remove non-upstream device node
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-05 17:55:29 +02:00
Arnd Bergmann
eac68a768a RK3328 mmc clockrate limit and addition of vpu node as well
as a regulator fix for the rk3328-rock64.
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Merge tag 'v5.4-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

RK3328 mmc clockrate limit and addition of vpu node as well
as a regulator fix for the rk3328-rock64.

* tag 'v5.4-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: limit clock rate of MMC controllers for RK3328
  arm64: dts: rockchip: add rk3328 VPU node
  arm64: dts: rockchip: fix vcc_host_5v regulator for usb3 host

Link: https://lore.kernel.org/r/43564855.cWDBQSyQMS@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-05 17:53:08 +02:00
Hans de Goede
8f373bf493 crypto: arm64 - Rename functions to avoid conflict with crypto/sha256.h
Rename static / file-local functions so that they do not conflict with
the functions declared in crypto/sha256.h.

This is a preparation patch for folding crypto/sha256.h into crypto/sha.h.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-09-05 14:37:30 +10:00
Pankaj Dubey
a6fe8c77c5 arm64: exynos: Enable exynos-chipid driver
Enable Exynos Chipid driver for accessing SoC related information.

Link: https://lore.kernel.org/r/20190904175002.10487-6-krzk@kernel.org
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-04 22:43:26 +02:00
Arnd Bergmann
49826a68b5 mvebu dt64 for 5.4 (part 2)
Add support for Turris Mox board (Armada 3720 SoC based)
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Merge tag 'mvebu-dt64-5.4-2' of git://git.infradead.org/linux-mvebu into arm/late

mvebu dt64 for 5.4 (part 2)

Add support for Turris Mox board (Armada 3720 SoC based)

* tag 'mvebu-dt64-5.4-2' of git://git.infradead.org/linux-mvebu: (53 commits)
  arm64: dts: marvell: add DTS for Turris Mox
  dt-bindings: marvell: document Turris Mox compatible
  arm64: dts: marvell: armada-37xx: add SPI CS1 pinctrl
  arm64: dts: marvell: Add cpu clock node on Armada 7K/8K
  arm64: dts: marvell: Convert 7k/8k usb-phy properties to phy-supply
  arm64: dts: marvell: Add 7k/8k PHYs in PCIe nodes
  arm64: dts: marvell: Add 7k/8k PHYs in USB3 nodes
  arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes
  arm64: dts: marvell: Add CP110 COMPHY clocks
  arm64: dts: marvell: armada-37xx: add mailbox node
  dt-bindings: gpio: Document GPIOs via Moxtet bus
  drivers: gpio: Add support for GPIOs over Moxtet bus
  bus: moxtet: Add sysfs and debugfs documentation
  dt-bindings: bus: Document moxtet bus binding
  bus: Add support for Moxtet bus
  reset: Add support for resets provided by SCMI
  firmware: arm_scmi: Add RESET protocol in SCMI v2.0
  dt-bindings: arm: Extend SCMI to support new reset protocol
  firmware: arm_scmi: Make use SCMI v2.0 fastchannel for performance protocol
  firmware: arm_scmi: Add discovery of SCMI v2.0 performance fastchannels
  ...

Link: https://lore.kernel.org/r/87h85two0r.fsf@FE-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-04 17:28:47 +02:00
Arnd Bergmann
65ab0dba3c Texas Instruments K3 SoC family changes for 5.4
- Typo fixes for gic-its unit addresses for both am654 and j721e
 - HW spinlock nodes added for both am654 and j721e
 - GPIO support for j721e
 - power-domain cells update for both am654 / j721e for exclusive only
   access
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Merge tag 'ti-k3-soc-for-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into arm/late

Texas Instruments K3 SoC family changes for 5.4

- Typo fixes for gic-its unit addresses for both am654 and j721e
- HW spinlock nodes added for both am654 and j721e
- GPIO support for j721e
- power-domain cells update for both am654 / j721e for exclusive only
  access

* tag 'ti-k3-soc-for-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
  arm64: dts: ti: k3-j721e-main: Fix gic-its node unit-address
  arm64: dts: ti: k3-am65-main: Fix gic-its node unit-address
  arm64: dts: ti: k3-j721e-main: Add hwspinlock node
  arm64: dts: ti: k3-am65-main: Add hwspinlock node
  arm64: dts: k3-j721e: Add gpio-keys on common processor board
  dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721E
  arm64: dts: ti: k3-j721e-common-proc-board: Disable unused gpio modules
  arm64: dts: ti: k3-j721e: Add gpio nodes in wakeup domain
  arm64: dts: ti: k3-j721e: Add gpio nodes in main domain
  arm64: dts: ti: k3-j721e: Update the power domain cells
  arm64: dts: ti: k3-am654: Update the power domain cells
  soc: ti: ti_sci_pm_domains: Add support for exclusive and shared access
  dt-bindings: ti_sci_pm_domains: Add support for exclusive and shared access
  firmware: ti_sci: Allow for device shared and exclusive requests

Link: https://lore.kernel.org/r/b838d666-ab3b-7d41-67d4-09d606c732da@ti.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-04 17:22:43 +02:00
Lee Jones
bf59c96f33 arm64: defconfig: Enable Qualcomm QUSB2 PHY
Tested on the Lenovo Yoga C630 where this patch enables USB.
Without it USB devices are not enumerated.

Link: https://lore.kernel.org/r/20190903192625.14775-3-lee.jones@linaro.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-04 17:15:29 +02:00
Lee Jones
9b266318b9 arm64: defconfig: Enable the EFI Framebuffer
Tested on the Lenovo Yoga C630 where this patch enables the
framebuffer (screen/monitor).  Without it the device appears
not to boot.

Link: https://lore.kernel.org/r/20190903192625.14775-2-lee.jones@linaro.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-04 17:15:22 +02:00
Lee Jones
878f2e4804 arm64: defconfig: Enable Qualcomm GENI based I2C controller
Tested on the Lenovo Yoga C630 where this patch enables the
keyboard, touchpad and touchscreen.

Link: https://lore.kernel.org/r/20190903192625.14775-1-lee.jones@linaro.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-04 17:15:14 +02:00
Arnd Bergmann
3563b7830f Qualcomm ARM64 Updates for v5.4
* Add Lenovo Miix 630, HP Envy x2, and Asus Novago TP370QL support
 * Assorted cleanups for SDM845 nodes
 * Add video nodes, cpu coefficients, adsp, csdp, and
   fastrpc nodes for SDM845
 * Add coresight for MSM8996, SDM845, and MSM8998
 * Misc cleanups on QCS404 and PMS405
 * Update memory map for QCS404
 * Add wifi rails, update WCSS clocks, and add ADS unit names on QCS404
 * Add Longcheer and Samsung Galaxy A3U/A5U support
 * Add initial support for SM8150 and PM8150
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Merge tag 'qcom-arm64-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

Qualcomm ARM64 Updates for v5.4

* Add Lenovo Miix 630, HP Envy x2, and Asus Novago TP370QL support
* Assorted cleanups for SDM845 nodes
* Add video nodes, cpu coefficients, adsp, csdp, and
  fastrpc nodes for SDM845
* Add coresight for MSM8996, SDM845, and MSM8998
* Misc cleanups on QCS404 and PMS405
* Update memory map for QCS404
* Add wifi rails, update WCSS clocks, and add ADS unit names on QCS404
* Add Longcheer and Samsung Galaxy A3U/A5U support
* Add initial support for SM8150 and PM8150

* tag 'qcom-arm64-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (39 commits)
  arm64: dts: sdm845: Add parent clock for rpmhcc
  arm64: dts: qcom: sm8150: Add apps shared nodes
  arm64: dts: qcom: sm8150: Add reserved-memory regions
  arm64: dts: qcom: sm8150-mtp: Add regulators
  arm64: dts: qcom: sm8150-mtp: Add base dts file
  arm64: dts: qcom: pm8150l: Add base dts file
  arm64: dts: qcom: pm8150b: Add base dts file
  arm64: dts: qcom: pm8150: Add base dts file
  arm64: dts: qcom: sm8150: Add base dts file
  arm64: sdm845: add adsp and cdsp fastrpc nodes
  arm64: dts: sdm845: Add dynamic CPU power coefficients
  arm64: dts: qcom: qcs404: Update memory map to v3
  arm64: dts: qcom: qcs404-evb: Mark WCSS clocks protected
  arm64: dts: qcom: Add device tree for Longcheer L8150
  arm64: dts: qcom: Add device tree for Samsung Galaxy A3U/A5U
  dt-bindings: qcom: Document bindings for new MSM8916 devices
  dt-bindings: vendor-prefixes: Add Longcheer Technology Co., Ltd.
  arm64: dts: qcom: msm8996: Add Venus video codec DT node
  arm64: dts: qcom: Extend AOSS QMP node
  arm64: dts: qcom: msm8996: Add Coresight support
  ...
2019-09-04 17:01:12 +02:00
Arnd Bergmann
6fb0706ec8 Qualcomm ARM64 Based defconfig Updates for v5.4
* Enable Qualcomm MSM8916 clock drivers
 * Add DRM_MSM to ARCH_QCOM defconfigs
 * Enable Qualcomm SM8150 clock and pinctrl drivers
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Merge tag 'qcom-arm64-defconfig-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/defconfig

Qualcomm ARM64 Based defconfig Updates for v5.4

* Enable Qualcomm MSM8916 clock drivers
* Add DRM_MSM to ARCH_QCOM defconfigs
* Enable Qualcomm SM8150 clock and pinctrl drivers

* tag 'qcom-arm64-defconfig-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  arm64: defconfig: Enable CPU clock drivers for Qualcomm msm8916
  arm64: defconfig: Add DRM_MSM to defconfigs with ARCH_QCOM
  arm64: defconfig: Enable SM8150 GCC and pinctrl driver
2019-09-04 16:58:41 +02:00
Arnd Bergmann
6729303cb6 This pull request contains Broadcom ARM64-based SoCs defconfig updates
for 5.4, please pull the following:
 
 - Nicolas enables the Raspberry Pi CPUFREQ driver in the ARM64 defconfig file
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Merge tag 'arm-soc/for-5.4/defconfig-arm64' of https://github.com/Broadcom/stblinux into arm/defconfig

This pull request contains Broadcom ARM64-based SoCs defconfig updates
for 5.4, please pull the following:

- Nicolas enables the Raspberry Pi CPUFREQ driver in the ARM64 defconfig file

* tag 'arm-soc/for-5.4/defconfig-arm64' of https://github.com/Broadcom/stblinux:
  arm64: defconfig: enable cpufreq support for RPi3
2019-09-04 15:00:06 +02:00
Arnd Bergmann
58324066aa Bitmain SoC changes for v5.4:
Most of the basic infrastructure is completed for BM1880 SoC except
 common clock support. We are still couple of patchset away from
 booting a distro from eMMC/SD with mainline. Below are the changes
 for this cycle:
 
 - Added Reset controller support to BM1880 SoC based on reset-simple
   driver.
 - Modified pinctrl memory map for BM1880 SoC. The initial pinctrl support
   included the PWM registers as a part of the pinctrl memory map. But this
   turned out to be useless as PWM registers are not handling any pin muxing
   at all. So removed the PWM registers from pinctrl memory map.
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Merge tag 'bitmain-soc-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-bitmain into arm/dt

Bitmain SoC changes for v5.4:

Most of the basic infrastructure is completed for BM1880 SoC except
common clock support. We are still couple of patchset away from
booting a distro from eMMC/SD with mainline. Below are the changes
for this cycle:

- Added Reset controller support to BM1880 SoC based on reset-simple
  driver.
- Modified pinctrl memory map for BM1880 SoC. The initial pinctrl support
  included the PWM registers as a part of the pinctrl memory map. But this
  turned out to be useless as PWM registers are not handling any pin muxing
  at all. So removed the PWM registers from pinctrl memory map.

* tag 'bitmain-soc-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-bitmain:
  arm64: dts: bitmain: Modify pin controller memory map
  arm64: dts: bitmain: Add reset controller support for BM1880 SoC

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-04 14:45:51 +02:00
Arnd Bergmann
d9a2b63ca9 Renesas ARM Based SoC Fixes for v5.3
* R-Car D3 (r8a77995) based Draak Board
   - Correct backlight regulator name in device tree
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Merge tag 'renesas-fixes-for-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/fixes

Renesas ARM Based SoC Fixes for v5.3

* R-Car D3 (r8a77995) based Draak Board
  - Correct backlight regulator name in device tree

* tag 'renesas-fixes-for-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: dts: renesas: r8a77995: draak: Fix backlight regulator name

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-04 14:38:47 +02:00
Christoph Hellwig
e376897f42 arm64: remove __iounmap
No need to indirect iounmap for arm64.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Will Deacon <will@kernel.org>
2019-09-04 13:12:26 +01:00
Arnd Bergmann
f02bd65a5b arm64: dts: Amlogic updates for v5.4 (round 2)
- new board: Khadas VIM3L (SM1/S905D3 SoC)
 - support power domains on G12[AB] and SM1 SoCs
 - DT binding fixups based on YAML schema
 - add a bunch of remote control keymap
 - enable DVFS on SM1/SEI610 board
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Merge tag 'amlogic-dt64-2.1' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt

arm64: dts: Amlogic updates for v5.4 (round 2)
- new board: Khadas VIM3L (SM1/S905D3 SoC)
- support power domains on G12[AB] and SM1 SoCs
- DT binding fixups based on YAML schema
- add a bunch of remote control keymap
- enable DVFS on SM1/SEI610 board

* tag 'amlogic-dt64-2.1' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (44 commits)
  arm64: dts: meson-sm1-sei610: add stdout-path property back
  arm64: dts: meson-sm1-sei610: enable DVFS
  arm64: dts: khadas-vim3: add support for the SM1 based VIM3L
  dt-bindings: arm: amlogic: add Amlogic SM1 based Khadas VIM3L bindings
  arm64: dts: khadas-vim3: move common nodes into meson-khadas-vim3.dtsi
  arm64: dts: meson: g12a: add reset to tdm formatters
  arm64: dts: meson: g12a: audio clock controller provides resets
  arm64: dts: meson-sm1-sei610: enable DVFS
  arm64: dts: meson-gxm-khadas-vim2: use rc-khadas keymap
  arm64: dts: meson-gxl-s905w-tx3-mini: add rc-tx3mini keymap
  arm64: dts: meson-gxl-s905x-khadas-vim: use rc-khadas keymap
  arm64: dts: meson-gxbb-wetek-play2: add rc-wetek-play2 keymap
  arm64: dts: meson-gxbb-wetek-hub: add rc-wetek-hub keymap
  arm64: dts: meson-g12a-x96-max: add rc-x96max keymap
  arm64: dts: meson-g12b-odroid-n2: add rc-odroid keymap
  arm64: dts: meson-sm1-sei610: add USB support
  arm64: dts: meson-sm1-sei610: add HDMI display support
  arm64: dts: meson-g12: add Everything-Else power domain controller
  arm64: dts: meson: fix boards regulators states format
  arm64: dts: meson-gxbb-p201: fix snps, reset-delays-us format
  ...

Link: https://patchwork.kernel.org/patch/11122331/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03 23:16:39 +02:00
Arnd Bergmann
e29de963e8 i.MX defconfig update for 5.4:
- Enable pinctrl and clock driver support for i.MX8MN SoC.
  - Enable SDMA support for i.MX8MQ and i.MX8MM SoC, including
    FW_LOADER_USER_HELPER and FW_LOADER_USER_HELPER_FALLBACK to support
    SDMA firmware loading via udev.
  - Enable module build of i.MX8 DDR PMU driver and ETNAVIV GPU driver.
  - Enable module build of OV5645 camera driver in imx_v6_v7_defconfig.
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Merge tag 'imx-defconfig-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/defconfig

i.MX defconfig update for 5.4:
 - Enable pinctrl and clock driver support for i.MX8MN SoC.
 - Enable SDMA support for i.MX8MQ and i.MX8MM SoC, including
   FW_LOADER_USER_HELPER and FW_LOADER_USER_HELPER_FALLBACK to support
   SDMA firmware loading via udev.
 - Enable module build of i.MX8 DDR PMU driver and ETNAVIV GPU driver.
 - Enable module build of OV5645 camera driver in imx_v6_v7_defconfig.

* tag 'imx-defconfig-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: defconfig: CONFIG_DRM_ETNAVIV=m
  ARM: imx_v6_v7_defconfig: Select the OV5645 camera driver
  arm64: defconfig: Build imx8 ddr pmu as module
  arm64: defconfig: Select CONFIG_CLK_IMX8MN by default
  arm64: defconfig: Select CONFIG_PINCTRL_IMX8MN by default
  arm64: defconfig: Enable SDMA on i.mx8mq/8mm

Link: https://lore.kernel.org/r/20190825153237.28829-7-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03 19:00:10 +02:00
Arnd Bergmann
9414d65d8b Allwinner arm64 defconfig changes for 5.4
Two patches to enable the IR receiver and the SPDIF transceiver found on
 the Allwinner SoCs.
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Merge tag 'sunxi-config64-for-5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/defconfig

Allwinner arm64 defconfig changes for 5.4

Two patches to enable the IR receiver and the SPDIF transceiver found on
the Allwinner SoCs.

* tag 'sunxi-config64-for-5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: defconfig: Enable Sun4i SPDIF module
  arm64: defconfig: Enable IR SUNXI option

Link: https://lore.kernel.org/r/24f215ca-f3a8-4497-bf98-9ba1808b37be.lettre@localhost
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03 18:54:34 +02:00
Arnd Bergmann
77319e88df arm64 defconfig for v5.4
- Add CONFIG_DW_WATCHDOG to support the Designware watchdog driver
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Merge tag 'arm64_defconfig_watchdog_for_v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/defconfig

arm64 defconfig for v5.4
- Add CONFIG_DW_WATCHDOG to support the Designware watchdog driver

* tag 'arm64_defconfig_watchdog_for_v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  arm64: defconfig: Enable the DesignWare watchdog

Link: https://lore.kernel.org/r/20190819141659.26414-2-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03 17:15:52 +02:00
Arnd Bergmann
a9c48eabe6 ARM64: hisilicon: defconfig updates for v5.4
- Enable ACPI_APEI_PCIEAER for the hisilicon D06 board to
   support PCIe AER error report
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Merge tag 'hisi-arm64-defconfig-for-5.4' of git://github.com/hisilicon/linux-hisi into arm/defconfig

ARM64: hisilicon: defconfig updates for v5.4

- Enable ACPI_APEI_PCIEAER for the hisilicon D06 board to
  support PCIe AER error report

* tag 'hisi-arm64-defconfig-for-5.4' of git://github.com/hisilicon/linux-hisi:
  arm64: defconfig: Enable CONFIG_ACPI_APEI_PCIEAER

Link: https://lore.kernel.org/r/5D562573.5030604@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03 17:10:27 +02:00
Arnd Bergmann
b1761ebea6 mvebu dt64 for 5.4 (part 1)
- Add mailbox support on Armada 37xx
  - Add cpu clock node needed for CPU freq on Armada 7K/8K
  - Enhance CP110 COMPHY support used by PCIe, USB3 and SATA
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Merge tag 'mvebu-dt64-5.4-1' of git://git.infradead.org/linux-mvebu into arm/dt

mvebu dt64 for 5.4 (part 1)

 - Add mailbox support on Armada 37xx
 - Add cpu clock node needed for CPU freq on Armada 7K/8K
 - Enhance CP110 COMPHY support used by PCIe, USB3 and SATA

* tag 'mvebu-dt64-5.4-1' of git://git.infradead.org/linux-mvebu:
  arm64: dts: marvell: Add cpu clock node on Armada 7K/8K
  arm64: dts: marvell: Convert 7k/8k usb-phy properties to phy-supply
  arm64: dts: marvell: Add 7k/8k PHYs in PCIe nodes
  arm64: dts: marvell: Add 7k/8k PHYs in USB3 nodes
  arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes
  arm64: dts: marvell: Add CP110 COMPHY clocks
  arm64: dts: marvell: armada-37xx: add mailbox node

Link: https://lore.kernel.org/r/875zmhzjml.fsf@FE-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03 16:16:51 +02:00
Arnd Bergmann
e8e39a2026 i.MX arm64 device tree update for 5.4:
- New board support: i.MX8MQ Nitrogen8m, Hummingboard Pulse,
    PICO-PI-IMX8M, i.MX8QXP AI_ML, and LS1046A FRWY board.
  - Add gpio-ranges for GPIO devices on i.MX8MQ and i.MX8MM.
  - Update OPP table according to latest data sheet and add opp-suspend
    to OPP table for i.MX8MQ and i.MX8MM.
  - Add IDEL states for i.MX8MM SoC.
  - Correct I2C clock divider for Layerscape SoCs.
  - Add series alias and LPUART baud clock for i.MX8QXP SoC.
  - Add MIPI D-PHY device for i.MX8MQ and enable it on imx8mq-librem5
    board.
  - Enable USB1 and Type-C support for i.MX8MM EVK board.
  - Add Thermal Monitor Unit support for LS1028A SoC.
  - Misc small update and correction on Layerscape and i.MX8 support.
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Merge tag 'imx-dt64-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX arm64 device tree update for 5.4:
 - New board support: i.MX8MQ Nitrogen8m, Hummingboard Pulse,
   PICO-PI-IMX8M, i.MX8QXP AI_ML, and LS1046A FRWY board.
 - Add gpio-ranges for GPIO devices on i.MX8MQ and i.MX8MM.
 - Update OPP table according to latest data sheet and add opp-suspend
   to OPP table for i.MX8MQ and i.MX8MM.
 - Add IDEL states for i.MX8MM SoC.
 - Correct I2C clock divider for Layerscape SoCs.
 - Add series alias and LPUART baud clock for i.MX8QXP SoC.
 - Add MIPI D-PHY device for i.MX8MQ and enable it on imx8mq-librem5
   board.
 - Enable USB1 and Type-C support for i.MX8MM EVK board.
 - Add Thermal Monitor Unit support for LS1028A SoC.
 - Misc small update and correction on Layerscape and i.MX8 support.

* tag 'imx-dt64-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (41 commits)
  arm64: dts: imx8mq: Add mux controller to iomuxc_gpr
  arm64: dts: fsl: add support for Hummingboard Pulse
  arm64: dts: ls1088a: update gpio compatible
  arm64: dts: imx: Add i.mx8mq nitrogen8m basic dts support
  arm64: dts: ls1088a-qds: Add the spi-flash nodes under the DSPI controller
  arm64: dts: ls1088a: Add the DSPI controller node
  arm64: dts: imx8mm: Enable cpu-idle driver
  arm64: dts: ls1028a: Add esdhc node in dts
  arm64: dts: ls1028a: Add properties node for Display output pixel clock
  arm64: dts: lx2160a: Fix incorrect I2C clock divider
  arm64: dts: ls1028a: Fix incorrect I2C clock divider
  arm64: dts: ls1012a: Fix incorrect I2C clock divider
  arm64: dts: ls1088a: Fix incorrect I2C clock divider
  arm64: dts: ls1028a: fix gpio nodes
  arm64: dts: ls1028a: Add Thermal Monitor Unit node
  arm64: dts: imx8mq-evk: Unbypass audio_pll1
  arm64: dts: imx8mm: Add opp-suspend property to OPP table
  arm64: dts: imx8mq: Add opp-suspend property to OPP table
  arm64: dts: ls1088a: Revise gpio registers to little-endian
  arm64: dts: add the console node for DPAA2 platforms
  ...

Link: https://lore.kernel.org/r/20190825153237.28829-6-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03 16:10:53 +02:00
Arnd Bergmann
89e4acf7a3 i.MX device tree update with new clocks:
- A series from Anson Huang to add i.MX8MN SoC and DDR4 EVK board
    device tree support.
  - Add DSP device tree support for i.MX8QXP SoC.
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Merge tag 'imx-dt-clkdep-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX device tree update with new clocks:
 - A series from Anson Huang to add i.MX8MN SoC and DDR4 EVK board
   device tree support.
 - Add DSP device tree support for i.MX8QXP SoC.

* tag 'imx-dt-clkdep-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: imx8qxp: Add DSP DT node
  arm64: dts: imx8mn: Add cpu-freq support
  arm64: dts: imx8mn-ddr4-evk: Add rohm,bd71847 PMIC support
  arm64: dts: imx8mn-ddr4-evk: Add i2c1 support
  arm64: dts: freescale: Add i.MX8MN DDR4 EVK board support
  arm64: dts: imx8mn: Add gpio-ranges property
  arm64: dts: freescale: Add i.MX8MN dtsi support
  clk: imx8: Add DSP related clocks
  clk: imx: Add support for i.MX8MN clock driver
  clk: imx: Add API for clk unregister when driver probe fail
  clk: imx8mm: Make 1416X/1443X PLL macro definitions common for usage
  dt-bindings: imx: Add clock binding doc for i.MX8MN

Link: https://lore.kernel.org/r/20190825153237.28829-4-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03 16:06:08 +02:00
Arnd Bergmann
369291a4ca mt8183:
- fix pwrap interrupt number
 - add i2c notes
 
 dt-bindings:
 - add compatible for mt6779
 - add mt6779 uart and sysirq compatible
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Merge tag 'v5.3-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

mt8183:
- fix pwrap interrupt number
- add i2c notes

dt-bindings:
- add compatible for mt6779
- add mt6779 uart and sysirq compatible

* tag 'v5.3-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  dt-bindings: irq: mtk, sysirq: add support for mt6779
  dt-bindings: mtk-uart: add mt6779 uart bindings
  dt-bindings: mediatek: add support for mt6779 reference board
  arm64: dts: mt8183: add I2C nodes
  arm64: dts: mt8183: fix pwrap gic number

Link: https://lore.kernel.org/r/def8fb77-fce4-097d-7ae2-8c4670bc09c1@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03 15:59:42 +02:00
Arnd Bergmann
db2f7fe562 Allwinner DT changes for 5.4
Our usual pile of patches for the next release, which include mostly:
   - More fixes thanks to the DT validation using the YAML bindings
   - IR receiver support on the H6
   - SPDIF support on the H6
   - I2C Support on the H6
   - CSI support on the A20
   - RTC support on the H6
   - New Boards: Lichee Zero Plus, Tanix TX6, A64-Olinuxino-eMMC
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Merge tag 'sunxi-dt-for-5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt

Allwinner DT changes for 5.4

Our usual pile of patches for the next release, which include mostly:
  - More fixes thanks to the DT validation using the YAML bindings
  - IR receiver support on the H6
  - SPDIF support on the H6
  - I2C Support on the H6
  - CSI support on the A20
  - RTC support on the H6
  - New Boards: Lichee Zero Plus, Tanix TX6, A64-Olinuxino-eMMC

* tag 'sunxi-dt-for-5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (40 commits)
  arm64: dts: allwinner: orange-pi-3: Enable WiFi
  ARM: dts: sunxi: Add missing watchdog clocks
  ARM: dts: sunxi: Add missing watchdog interrupts
  arm64: dts: allwinner: h6: Add support for RTC and fix the clock tree
  ARM: dts: sun7i: Add CSI0 controller
  arm64: dts: allwinner: a64: Add A64 OlinuXino board (with eMMC)
  dt-bindings: arm: sunxi: Add compatible for A64 OlinuXino with eMMC
  ARM: dts: v3s: Change the timers compatible
  ARM: dts: h3: Change the timers compatible
  ARM: dts: a83t: Change the timers compatible
  ARM: dts: a23/a33: Change the timers compatible
  ARM: dts: sun6i: Add missing timers interrupts
  ARM: dts: sun5i: Add missing timers interrupts
  ARM: dts: sun4i: Add missing timers interrupts
  dt-bindings: mfd: Convert Allwinner GPADC bindings to a schema
  arm64: dts: allwinner: h6: Introduce Tanix TX6 board
  dt-bindings: arm: sunxi: Add compatible for Tanix TX6 board
  arm64: allwinner: h6: add I2C nodes
  dt-bindings: i2c: mv64xxx: Add compatible for the H6 i2c node.
  ARM: dts: sunxi: Add mdio bus sub-node to GMAC
  ...

Link: https://lore.kernel.org/r/d97e6252-9dd7-4cf5-a3cf-56f78b0ca455.lettre@localhost
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03 15:55:51 +02:00
Jerin Jacob
504792e07a arm64: bpf: optimize modulo operation
Optimize modulo operation instruction generation by
using single MSUB instruction vs MUL followed by SUB
instruction scheme.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
2019-09-03 15:44:40 +02:00
Arnd Bergmann
f2a3d36cca Renesas ARM64 DT updates for v5.4 (take two)
- Sort nodes in various SoC and board DTSes,
   - HDMI sound for HiHope RZ/G2M and R-Car M3-N Salvator-X(S) boards,
   - Limit EtherAVB to 100Mbps on the Ebisu and Draak boards,
   - Small fixes and improvements.
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Merge tag 'renesas-arm64-dt-for-v5.4-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM64 DT updates for v5.4 (take two)

  - Sort nodes in various SoC and board DTSes,
  - HDMI sound for HiHope RZ/G2M and R-Car M3-N Salvator-X(S) boards,
  - Limit EtherAVB to 100Mbps on the Ebisu and Draak boards,
  - Small fixes and improvements.

* tag 'renesas-arm64-dt-for-v5.4-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (21 commits)
  arm64: dts: renesas: Update 'vsps' properties for readability
  arm64: dts: renesas: r8a77965-salvator-x(s): Enable HDMI sound
  arm64: dts: renesas: r8a774c0: Fix register range of display node
  arm64: dts: renesas: r8a77970: Sort nodes
  arm64: dts: renesas: r8a7796: Sort nodes
  arm64: dts: renesas: r8a774c0: Sort nodes
  arm64: dts: renesas: r8a774c0: cat874: Sort nodes
  arm64: dts: renesas: r8a774a1: Sort nodes
  arm64: dts: renesas: r8a77980: Fix IPMMU-VC0 base address
  arm64: dts: renesas: ebisu, draak: Limit EtherAVB to 100Mbps
  arm64: dts: renesas: hihope-common: Add HDMI audio support
  arm64: dts: renesas: r8a774c0: cat874: Add definition for 12V regulator
  arm64: dts: renesas: r8a774c0: Point LVDS0 to its companion LVDS1
  arm64: dts: renesas: r8a77995: Sort nodes
  arm64: dts: renesas: r8a77995: draak: Sort nodes
  arm64: dts: renesas: r8a77990: Sort nodes
  arm64: dts: renesas: r8a77990: ebisu: Sort nodes
  arm64: dts: renesas: r8a77980: v3hsk: Sort nodes
  arm64: dts: renesas: r8a77980: condor: Sort nodes
  arm64: dts: renesas: r8a77970: v3msk: Sort nodes
  ...

Link: https://lore.kernel.org/r/20190823123643.18799-4-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03 15:37:06 +02:00
Arnd Bergmann
1c92b32649 arm64: dts: Amlogic updates for v5.4
Highlights
 - new SoCs (G12B family): S922X, A311D
 - new SoCs (SM1 family): S905X3
 - new board: SEI Robotics SEI610 (SM1/S905X3)
 - new board: Khadas VIM3 (G12B/A311D)
 - DVFS/CPUfreq support on G12[AB] family
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Merge tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt

arm64: dts: Amlogic updates for v5.4

Highlights
- new SoCs (G12B family): S922X, A311D
- new SoCs (SM1 family): S905X3
- new board: SEI Robotics SEI610 (SM1/S905X3)
- new board: Khadas VIM3 (G12B/A311D)
- DVFS/CPUfreq support on G12[AB] family

* tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (40 commits)
  arm64: dts: add support for SM1 based SEI Robotics SEI610
  dt-bindings: arm: amlogic: add SEI Robotics SEI610 bindings
  dt-bindings: arm: amlogic: add SM1 bindings
  arm64: dts: meson-g12b-odroid-n2: enable DVFS
  arm64: dts: meson-g12b-khadas-vim3: add initial device-tree
  dt-bindings: arm: amlogic: fix x96-max/sei510 section in amlogic.yaml
  arm64: dts: amlogic: g12 CPU timers stop in suspend
  arm64: dts: meson-g12b: support a311d and s922x cpu operating points
  dt-bindings: arm: amlogic: add support for the Khadas VIM3
  dt-bindings: arm: amlogic: add bindings for the Amlogic G12B based A311D SoC
  dt-bindings: arm: amlogic: add bindings for G12B based S922X SoC
  arm64: dts: meson: add video decoder entries
  arm64: dts: meson-gx: add video decoder entry
  dt-bindings: media: amlogic,vdec: add default compatible
  arm64: dts: meson: add ethernet fifo sizes
  arm64: dts: meson-g12b: add cpus OPP tables
  arm64: dts: meson-g12a: enable DVFS on G12A boards
  arm64: dts: meson-g12a: add cpus OPP table
  arm64: dts: meson-g12-common: add pwm_a on GPIOE_2 pinmux
  arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi
  ...

Link: https://lore.kernel.org/r/7hr25fbi4v.fsf@baylibre.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03 15:14:54 +02:00
Arnd Bergmann
aa85a28663 SoCFPGA DTS updates for v5.4
- Add reset properties for various peripherals
 	- QSPI OCP and DMA on Arria10
 	- DMA on Agilex/Stratix10
 - Update NAND controller bindings to match driver update
 - Add NAND controller to Stratix10
 - VINING FPGA board fixups
 	- Update button mapping
 	- Adjust GMAC1 clock and TXD skew settings
 - Add missing reset-names for dma controller
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Merge tag 'socfpga_dts_updates_for_v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt

SoCFPGA DTS updates for v5.4
- Add reset properties for various peripherals
	- QSPI OCP and DMA on Arria10
	- DMA on Agilex/Stratix10
- Update NAND controller bindings to match driver update
- Add NAND controller to Stratix10
- VINING FPGA board fixups
	- Update button mapping
	- Adjust GMAC1 clock and TXD skew settings
- Add missing reset-names for dma controller

* tag 'socfpga_dts_updates_for_v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: dts: socfpga: add missing reset-names for dma
  ARM: dts: socfpga: Adjust GMAC1 clock and TXD lines skew on VINING FPGA
  ARM: dts: socfpga: Fix up button mapping on VINING FPGA
  arm64: dts: stratix10: Add NAND device node
  ARM: dts: socfpga: update to new Denali NAND binding
  arm64: dts: agilex/stratix10: Add reset properties for DMA
  ARM: dts: socfpga: add reset properties for DMA
  ARM: dts: socfpga: add the QSPI OCP reset property on arria10

Link: https://lore.kernel.org/r/20190819141659.26414-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03 15:10:33 +02:00
Arnd Bergmann
2c70bcf72d PWM-Fan and nor-flash for the RockPro64, a better display mode for
the Kevin Chromebook and a new board the Leez P710 SBC.
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Merge tag 'v5.4-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

PWM-Fan and nor-flash for the RockPro64, a better display mode for
the Kevin Chromebook and a new board the Leez P710 SBC.

* tag 'v5.4-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: Add dts for Leez RK3399 P710 SBC
  arm64: dts: rockchip: enable internal SPI flash for RockPro64.
  arm64: dts: rockchip: Add PWM fan for RockPro64
  arm64: dts: rockchip: Specify override mode for kevin panel

Link: https://lore.kernel.org/r/20190819141659.26414-1-dinguyen@kernel.org
Link: https://lore.kernel.org/r/2362486.gYoCZEsBuK@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03 15:09:56 +02:00
Arnd Bergmann
e6dde5cc39 i.MX SoC changes for 5.4:
- Drop AR8031 PHY TX delay adjusting from i.MX7D machine code, as
    it's superfluous due to the recent changes to Atheros AT803X driver.
  - Select TIMER_IMX_SYS_CTR for arm64 ARCH_MXC platform, since the
    system counter is needed as broadcast timer for cpuidle support.
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Merge tag 'imx-soc-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/soc

i.MX SoC changes for 5.4:
 - Drop AR8031 PHY TX delay adjusting from i.MX7D machine code, as
   it's superfluous due to the recent changes to Atheros AT803X driver.
 - Select TIMER_IMX_SYS_CTR for arm64 ARCH_MXC platform, since the
   system counter is needed as broadcast timer for cpuidle support.

* tag 'imx-soc-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: imx: stop adjusting ar8031 phy tx delay
  arm64: Enable TIMER_IMX_SYS_CTR for ARCH_MXC platforms

Link: https://lore.kernel.org/r/20190825153237.28829-2-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03 14:21:52 +02:00
David S. Miller
765b7590c9 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
r8152 conflicts are the NAPI fixes in 'net' overlapping with
some tasklet stuff in net-next

Signed-off-by: David S. Miller <davem@davemloft.net>
2019-09-02 11:20:17 -07:00
Marc Gonzalez
fcee7de608 arm64: defconfig: Enable CPU clock drivers for Qualcomm msm8916
QCOM_A53PLL and QCOM_CLK_APCS_MSM8916 used to be enabled by default in
drivers/clk/qcom/Kconfig. A recent patch changed that by dropping the
'default ARCH_QCOM' directive.

Add the two options explicitly in the arm64 defconfig, to avoid
functional regressions.

Acked-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
[bjorn: Rewrote subject]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-09-01 00:42:53 -05:00
Jordan Crouse
6377910c5c arm64: defconfig: Add DRM_MSM to defconfigs with ARCH_QCOM
Now that CONFIG_DRM_MSM is no longer default 'y' add it as a module to all
ARCH_QCOM enabled defconfigs to restore the previous expected build
behavior.

I split this off from the original patch to separate out the ARM64 portions.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
2019-09-01 00:42:39 -05:00
Shawn Lin
03e61929c0 arm64: dts: rockchip: limit clock rate of MMC controllers for RK3328
150MHz is a fundamental limitation of RK3328 Soc, w/o this limitation,
eMMC, for instance, will run into 200MHz clock rate in HS200 mode, which
makes the RK3328 boards not always boot properly. By adding it in
rk3328.dtsi would also obviate the worry of missing it when adding new
boards.

Fixes: 52e02d377a ("arm64: dts: rockchip: add core dtsi file for RK3328 SoCs")
Cc: stable@vger.kernel.org
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Liang Chen <cl@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-09-01 03:00:17 +02:00
Steven Rostedt (VMware)
f7edb451fa tracing/arm64: Have max stack tracer handle the case of return address after data
Most archs (well at least x86) store the function call return address on the
stack before storing the local variables for the function. The max stack
tracer depends on this in its algorithm to display the stack size of each
function it finds in the back trace.

Some archs (arm64), may store the return address (from its link register)
just before calling a nested function. There's no reason to save the link
register on leaf functions, as it wont be updated. This breaks the algorithm
of the max stack tracer.

Add a new define ARCH_FTRACE_SHIFT_STACK_TRACER that an architecture may set
if it stores the return address (link register) after it stores the
function's local variables, and have the stack trace shift the values of the
mapped stack size to the appropriate functions.

Link: 20190802094103.163576-1-jiping.ma2@windriver.com

Reported-by: Jiping Ma <jiping.ma2@windriver.com>
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
2019-08-31 12:19:40 -04:00
Fabrizio Castro
ae688e1720 arm64: dts: renesas: hihope-common: Fix eMMC status
SDHI3 got accidentally disabled while adding USB 2.0 support,
this patch fixes it.

Fixes: 734d277f41 ("arm64: dts: renesas: hihope-common: Add USB 2.0 support")
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-08-31 11:23:18 +02:00
Marek Behún
7109d817db arm64: dts: marvell: add DTS for Turris Mox
This adds support for the Turris Mox board from CZ.NIC.

Turris Mox is as modular router based on the Armada 3720 SOC (same as
EspressoBin).

The basic board can be extended by different modules.
If those are connected, U-Boot lets the kernel know via device-tree.

Since modules can be connected in different order and some modules can
be connected multiple times (up to three modules containing 8-port
ethernet switch in DSA configuration can be connected) we decided
against using device-tree overlays, because it got complicated rather
quickly. (For example the SFP module can be connected directly to the
CPU, or after a switch module. There are four cases and all would need
different SFP overlay. There are two types of switch modules (8-port
with pass-through and 4-port with no pass-through). For those we would
again need at least 6 more overlays.)

We therefore decided to put all the possibly connected devices in one
device-tree and disable them by default. When U-Boot finds out which
modules are connected, it fixes the loaded device-tree accordingly just
before boot. By Rob Herring's suggestion we also made it so that U-Boot
completely removes nodes which are disabled after this fixup.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Rob Herring <robh@kernel.org>
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-08-31 09:24:31 +02:00
Marek Behún
8ef75105b5 arm64: dts: marvell: armada-37xx: add SPI CS1 pinctrl
This adds pinctrl node for the GPIO to be used as SPI chip select 1.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-08-31 09:24:31 +02:00
Linus Torvalds
e8d6766f3c ARM: SoC fixes
The majority of the fixes this time are for OMAP hardware,
 here is a breakdown of the significant changes:
 
 Various device tree bug fixes:
 - TI am57xx boards need a voltage level fix to avoid damaging SD cards
 - vf610-bk4 fails to detect its flash due to an incorrect description
 - meson-g12a USB phy configuration fails
 - meson-g12b reboot should not power off the SD card
 - Some corrections for apparently harmless differences from the
   documentation.
 
 Regression fixes:
 - ams-delta FIQ interrupts broke in 5.3
 - TI am3/am4 mmc controllers broke in 5.2
 
 The logic_pio driver (used on some Huawei ARM servers) needs a few
 bug fixes for reliability.
 
 A couple of compile-time warning fixes
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
 "The majority of the fixes this time are for OMAP hardware, here is a
  breakdown of the significant changes:

  Various device tree bug fixes:
   - TI am57xx boards need a voltage level fix to avoid damaging SD
     cards
   - vf610-bk4 fails to detect its flash due to an incorrect description
   - meson-g12a USB phy configuration fails
   - meson-g12b reboot should not power off the SD card
   - Some corrections for apparently harmless differences from the
     documentation.

  Regression fixes:
   - ams-delta FIQ interrupts broke in 5.3
   - TI am3/am4 mmc controllers broke in 5.2

  The logic_pio driver (used on some Huawei ARM servers) got a few bug
  fixes for reliability.

  And a couple of compile-time warning fixes"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (26 commits)
  soc: ixp4xx: Protect IXP4xx SoC drivers by ARCH_IXP4XX || COMPILE_TEST
  soc: ti: pm33xx: Make two symbols static
  soc: ti: pm33xx: Fix static checker warnings
  ARM: OMAP: dma: Mark expected switch fall-throughs
  ARM: dts: Fix incomplete dts data for am3 and am4 mmc
  bus: ti-sysc: Simplify cleanup upon failures in sysc_probe()
  ARM: OMAP1: ams-delta-fiq: Fix missing irq_ack
  ARM: dts: dra74x: Fix iodelay configuration for mmc3
  ARM: dts: am335x: Fix UARTs length
  ARM: OMAP2+: Fix omap4 errata warning on other SoCs
  bus: hisi_lpc: Add .remove method to avoid driver unbind crash
  bus: hisi_lpc: Unregister logical PIO range to avoid potential use-after-free
  lib: logic_pio: Add logic_pio_unregister_range()
  lib: logic_pio: Avoid possible overlap for unregistering regions
  lib: logic_pio: Fix RCU usage
  arm64: dts: amlogic: odroid-n2: keep SD card regulator always on
  arm64: dts: meson-g12a-sei510: enable IR controller
  arm64: dts: meson-g12a: add missing dwc2 phy-names
  ARM: dts: vf610-bk4: Fix qspi node description
  ARM: dts: Fix incorrect dcan register mapping for am3, am4 and dra7
  ...
2019-08-30 10:53:12 -07:00
Will Deacon
61b7cddfe8 Merge branch 'for-next/atomics' into for-next/core
* for-next/atomics: (10 commits)
  Rework LSE instruction selection to use static keys instead of alternatives
2019-08-30 12:55:39 +01:00
Will Deacon
ac12cf85d6 Merge branches 'for-next/52-bit-kva', 'for-next/cpu-topology', 'for-next/error-injection', 'for-next/perf', 'for-next/psci-cpuidle', 'for-next/rng', 'for-next/smpboot', 'for-next/tbi' and 'for-next/tlbi' into for-next/core
* for-next/52-bit-kva: (25 commits)
  Support for 52-bit virtual addressing in kernel space

* for-next/cpu-topology: (9 commits)
  Move CPU topology parsing into core code and add support for ACPI 6.3

* for-next/error-injection: (2 commits)
  Support for function error injection via kprobes

* for-next/perf: (8 commits)
  Support for i.MX8 DDR PMU and proper SMMUv3 group validation

* for-next/psci-cpuidle: (7 commits)
  Move PSCI idle code into a new CPUidle driver

* for-next/rng: (4 commits)
  Support for 'rng-seed' property being passed in the devicetree

* for-next/smpboot: (3 commits)
  Reduce fragility of secondary CPU bringup in debug configurations

* for-next/tbi: (10 commits)
  Introduce new syscall ABI with relaxed requirements for pointer tags

* for-next/tlbi: (6 commits)
  Handle spurious page faults arising from kernel space
2019-08-30 12:46:12 +01:00
Will Deacon
03adcbd996 arm64: atomics: Use K constraint when toolchain appears to support it
The 'K' constraint is a documented AArch64 machine constraint supported
by GCC for matching integer constants that can be used with a 32-bit
logical instruction. Unfortunately, some released compilers erroneously
accept the immediate '4294967295' for this constraint, which is later
refused by GAS at assembly time. This had led us to avoid the use of
the 'K' constraint altogether.

Instead, detect whether the compiler is up to the job when building the
kernel and pass the 'K' constraint to our 32-bit atomic macros when it
appears to be supported.

Signed-off-by: Will Deacon <will@kernel.org>
2019-08-30 11:18:40 +01:00
Will Deacon
5aad6cdabb arm64: atomics: Undefine internal macros after use
We use a bunch of internal macros when constructing our atomic and
cmpxchg routines in order to save on boilerplate. Avoid exposing these
directly to users of the header files.

Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2019-08-30 11:18:37 +01:00
Will Deacon
b32baf91f6 arm64: lse: Make ARM64_LSE_ATOMICS depend on JUMP_LABEL
Support for LSE atomic instructions (CONFIG_ARM64_LSE_ATOMICS) relies on
a static key to select between the legacy LL/SC implementation which is
available on all arm64 CPUs and the super-duper LSE implementation which
is available on CPUs implementing v8.1 and later.

Unfortunately, when building a kernel with CONFIG_JUMP_LABEL disabled
(e.g. because the toolchain doesn't support 'asm goto'), the static key
inside the atomics code tries to use atomics itself. This results in a
mess of circular includes and a build failure:

In file included from ./arch/arm64/include/asm/lse.h:11,
                 from ./arch/arm64/include/asm/atomic.h:16,
                 from ./include/linux/atomic.h:7,
                 from ./include/asm-generic/bitops/atomic.h:5,
                 from ./arch/arm64/include/asm/bitops.h:26,
                 from ./include/linux/bitops.h:19,
                 from ./include/linux/kernel.h:12,
                 from ./include/asm-generic/bug.h:18,
                 from ./arch/arm64/include/asm/bug.h:26,
                 from ./include/linux/bug.h:5,
                 from ./include/linux/page-flags.h:10,
                 from kernel/bounds.c:10:
./include/linux/jump_label.h: In function ‘static_key_count’:
./include/linux/jump_label.h:254:9: error: implicit declaration of function ‘atomic_read’ [-Werror=implicit-function-declaration]
  return atomic_read(&key->enabled);
         ^~~~~~~~~~~

[ ... more of the same ... ]

Since LSE atomic instructions are not critical to the operation of the
kernel, make them depend on JUMP_LABEL at compile time.

Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2019-08-30 11:18:33 +01:00
Will Deacon
0533f97b43 arm64: asm: Kill 'asm/atomic_arch.h'
The contents of 'asm/atomic_arch.h' can be split across some of our
other 'asm/' headers. Remove it.

Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2019-08-30 11:18:29 +01:00
Will Deacon
0ca98b2456 arm64: lse: Remove unused 'alt_lse' assembly macro
The 'alt_lse' assembly macro has been unused since 7c8fc35dfc
("locking/atomics/arm64: Replace our atomic/lock bitop implementations
with asm-generic").

Remove it.

Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2019-08-30 11:18:14 +01:00
Ard Biesheuvel
735177ca14 crypto: arm64/aes - implement accelerated ESSIV/CBC mode
Add an accelerated version of the 'essiv(cbc(aes),sha256)' skcipher,
which is used by fscrypt or dm-crypt on systems where CBC mode is
signficantly more performant than XTS mode (e.g., when using a h/w
accelerator which supports the former but not the latter) This avoids
a separate call into the AES cipher for every invocation.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-08-30 18:05:27 +10:00
Ard Biesheuvel
65d0042b52 crypto: arm64/aes-cts-cbc - factor out CBC en/decryption of a walk
The plain CBC driver and the CTS one share some code that iterates over
a scatterwalk and invokes the CBC asm code to do the processing. The
upcoming ESSIV/CBC mode will clone that pattern for the third time, so
let's factor it out first.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-08-30 18:05:27 +10:00
Neil Armstrong
b09d116b78 arm64: dts: meson-sm1-sei610: add stdout-path property back
The commit d4609acce187 ("arm64: dts: meson-sm1-sei610: enable DVFS")
incorrectly removed the chosen node and the stdout-path property.

Add these back.

Fixes: d4609acce187 ("arm64: dts: meson-sm1-sei610: enable DVFS")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:18:38 -07:00
Neil Armstrong
488b0ffc0e arm64: dts: meson-sm1-sei610: enable DVFS
This enables DVFS for the Amlogic SM1 based SEI610 board by:
- Adding the SM1 SoC OPPs taken from the vendor tree
- Selecting the SM1 Clock controller instead of the G12A one
- Adding the CPU rail regulator, PWM and OPPs for each CPU nodes.

Each power supply can achieve 0.69V to 1.05V using a single PWM
output clocked at 666KHz with an inverse duty-cycle.

DVFS has been tested by running the arm64 cpuburn at [1] and cycling
between all the possible cpufreq translations of the cpu cluster and
checking the final frequency using the clock-measurer, script at [2].

[1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S
[2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:18:38 -07:00
Neil Armstrong
700ab8d839 arm64: dts: khadas-vim3: add support for the SM1 based VIM3L
Add the Amlogic SM1 based Khadas VIM3L, sharing all the same features
as the G12B based VIM3, but:
- a different DVFS support since only a single cluster is available
- audio is still not available on SM1

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:17:42 -07:00
Neil Armstrong
4f26cc1c96 arm64: dts: khadas-vim3: move common nodes into meson-khadas-vim3.dtsi
To prepare support of the Amlogic SM1 based Khadas VIM3, move the non-G12B
specific nodes (all except DVFS and Audio) to a new meson-khadas-vim3.dtsi

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:17:42 -07:00
Jerome Brunet
f403cbff74 arm64: dts: meson: g12a: add reset to tdm formatters
Add the reset to the TDM formatters of the g12a. This helps
with channel mapping when a playback/capture uses more than 1 lane.

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:17:42 -07:00
Jerome Brunet
8502fd5221 arm64: dts: meson: g12a: audio clock controller provides resets
The clock controller dedicated to audio clocks also provides reset lines
on the g12 SoC family

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:17:42 -07:00
Neil Armstrong
3d9e764830 arm64: dts: meson-sm1-sei610: enable DVFS
This enables DVFS for the Amlogic SM1 based SEI610 board by:
- Adding the SM1 SoC OPPs taken from the vendor tree
- Selecting the SM1 Clock controller instead of the G12A one
- Adding the CPU rail regulator, PWM and OPPs for each CPU nodes.

Each power supply can achieve 0.69V to 1.05V using a single PWM
output clocked at 666KHz with an inverse duty-cycle.

DVFS has been tested by running the arm64 cpuburn at [1] and cycling
between all the possible cpufreq translations of the cpu cluster and
checking the final frequency using the clock-measurer, script at [2].

[1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S
[2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:17:42 -07:00
Christian Hewitt
c9a4b25c3d arm64: dts: meson-gxm-khadas-vim2: use rc-khadas keymap
Swap to the rc-khadas keymap that maps the mouse button to KEY_MUTE.

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:17:42 -07:00
Christian Hewitt
06c739617a arm64: dts: meson-gxl-s905w-tx3-mini: add rc-tx3mini keymap
add the rc-tx3mini keymap to the ir node

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:17:42 -07:00
Christian Hewitt
c9ee1d25ef arm64: dts: meson-gxl-s905x-khadas-vim: use rc-khadas keymap
Swap to the rc-khadas keymap that maps the mouse button to KEY_MUTE.

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:17:41 -07:00
Christian Hewitt
625cb5b695 arm64: dts: meson-gxbb-wetek-play2: add rc-wetek-play2 keymap
add the rc-wetek-play2 keymap to the ir node

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:17:41 -07:00
Christian Hewitt
304bb5efa8 arm64: dts: meson-gxbb-wetek-hub: add rc-wetek-hub keymap
add the rc-wetek-hub keymap to the ir node

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:17:41 -07:00
Christian Hewitt
3e14618b52 arm64: dts: meson-g12a-x96-max: add rc-x96max keymap
add the rc-x96max keymap to the ir node

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:17:41 -07:00
Christian Hewitt
41ac5a4ca2 arm64: dts: meson-g12b-odroid-n2: add rc-odroid keymap
add the rc-odroid keymap to the ir node

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:17:41 -07:00
Neil Armstrong
24fe3e989e arm64: dts: meson-sm1-sei610: add USB support
Add the USB properties for the Amlogic SM1 Based SEI610 Board in order to
support the USB DRD Type-C port and the USB3 Type A port.

The USB DRD Type-C controller uses the ID signal to toggle the USB role
between the DWC3 Host controller and the DWC2 Device controller.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:17:41 -07:00
Neil Armstrong
96a386b6ed arm64: dts: meson-sm1-sei610: add HDMI display support
Add the HDMI support nodes for the Amlogic SM1 Based SEI610 Board.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:17:41 -07:00
Neil Armstrong
f4f1c8d9ac arm64: dts: meson-g12: add Everything-Else power domain controller
Replace the VPU-centric power domain controller by the generic system-wide
Everything-Else power domain controller and setup the right power-domains
properties on the VPU, Ethernet & USB nodes.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
[khilman: minor subject edit: add dts]
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:17:01 -07:00
Neil Armstrong
f9717178b9 arm64: dts: meson: fix boards regulators states format
This fixes the following DT schemas check errors:
meson-gxbb-odroidc2.dt.yaml: gpio-regulator-tf_io: states:0: Additional items are not allowed (1800000, 1 were unexpected)
meson-gxbb-odroidc2.dt.yaml: gpio-regulator-tf_io: states:0: [3300000, 0, 1800000, 1] is too long
meson-gxbb-nexbox-a95x.dt.yaml: gpio-regulator: states:0: Additional items are not allowed (3300000, 1 were unexpected)
meson-gxbb-nexbox-a95x.dt.yaml: gpio-regulator: states:0: [1800000, 0, 3300000, 1] is too long
meson-gxbb-p200.dt.yaml: gpio-regulator: states:0: Additional items are not allowed (3300000, 1 were unexpected)
meson-gxbb-p200.dt.yaml: gpio-regulator: states:0: [1800000, 0, 3300000, 1] is too long
meson-gxl-s905x-hwacom-amazetv.dt.yaml: gpio-regulator: states:0: Additional items are not allowed (3300000, 1 were unexpected)
meson-gxl-s905x-hwacom-amazetv.dt.yaml: gpio-regulator: states:0: [1800000, 0, 3300000, 1] is too long
meson-gxbb-p201.dt.yaml: gpio-regulator: states:0: Additional items are not allowed (3300000, 1 were unexpected)
meson-gxbb-p201.dt.yaml: gpio-regulator: states:0: [1800000, 0, 3300000, 1] is too long
meson-g12b-odroid-n2.dt.yaml: gpio-regulator-tf_io: states:0: Additional items are not allowed (1800000, 1 were unexpected)
meson-g12b-odroid-n2.dt.yaml: gpio-regulator-tf_io: states:0: [3300000, 0, 1800000, 1] is too long
meson-gxl-s905x-nexbox-a95x.dt.yaml: gpio-regulator: states:0: Additional items are not allowed (3300000, 1 were unexpected)
meson-gxl-s905x-nexbox-a95x.dt.yaml: gpio-regulator: states:0: [1800000, 0, 3300000, 1] is too long

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:13:35 -07:00
Neil Armstrong
31cad845e0 arm64: dts: meson-gxbb-p201: fix snps, reset-delays-us format
This fixes the following DT schemas check errors:
meson-gxbb-p201.dt.yaml: ethernet@c9410000: snps,reset-delays-us: [[0, 10000, 1000000]] is too short

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:13:35 -07:00
Neil Armstrong
591185c1ce arm64: dts: meson-gxbb-nanopi-k2: add missing model
This fixes the following DT schemas check errors:
meson-gxbb-nanopi-k2.dt.yaml: /: 'model' is a required property

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:13:35 -07:00
Neil Armstrong
b167b4731e arm64: dts: meson-g12a-x96-max: fix compatible
This fixes the following DT schemas check errors:
meson-g12a-x96-max.dt.yaml: /: compatible: ['amediatech,x96-max', 'amlogic,u200', 'amlogic,g12a'] is not valid under any of the given schemas

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:13:35 -07:00
Neil Armstrong
795e7de8c7 arm64: dts: meson-g12a: fix reset controller compatible
This fixes the following DT schemas check errors:
meson-g12a-u200.dt.yaml: reset-controller@1004: compatible:0: 'amlogic,meson-g12a-reset' is not one of ['amlogic,meson8b-reset', 'amlogic,meson-gxbb-reset', 'amlogic,meson-axg-reset']
meson-g12a-sei510.dt.yaml: reset-controller@1004: compatible:0: 'amlogic,meson-g12a-reset' is not one of ['amlogic,meson8b-reset', 'amlogic,meson-gxbb-reset', 'amlogic,meson-axg-reset']

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:13:35 -07:00
Neil Armstrong
01efc19cb9 arm64: dts: meson-axg: fix MHU compatible
This fixes the following DT schemas check errors:
meson-axg-s400.dt.yaml: mailbox@ff63c404: compatible:0: 'amlogic,meson-gx-mhu' is not one of ['amlogic,meson-gxbb-mhu']

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:13:35 -07:00
Neil Armstrong
49ee7f85a4 arm64: dts: meson-gxl: fix internal phy compatible
This fixes the following DT schemas check errors:
meson-gxl-s805x-libretech-ac.dt.yaml: ethernet-phy@8: compatible: ['ethernet-phy-id0181.4400', 'ethernet-phy-ieee802.3-c22'] is not valid under any of the given schemas

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:13:34 -07:00
Neil Armstrong
2e36480c93 arm64: dts: meson-gx: fix periphs bus node name
This fixes the following DT schemas check errors:
meson-gxbb-nanopi-k2.dt.yaml: periphs@c8834000: $nodename:0: 'periphs@c8834000' does not match '^(bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'
meson-gxl-s805x-libretech-ac.dt.yaml: periphs@c8834000: $nodename:0: 'periphs@c8834000' does not match '^(bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:13:34 -07:00
Neil Armstrong
59d370105d arm64: dts: meson-gx: fix mhu compatible
This fixes the following DT schemas check errors:
meson-gxbb-nanopi-k2.dt.yaml: mailbox@404: compatible:0: 'amlogic,meson-gx-mhu' is not one of ['amlogic,meson-gxbb-mhu']
meson-gxl-s805x-libretech-ac.dt.yaml: mailbox@404: compatible:0: 'amlogic,meson-gx-mhu' is not one of ['amlogic,meson-gxbb-mhu']

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:13:34 -07:00
Neil Armstrong
03c76b81ab arm64: dts: meson-gx: fix watchdog compatible
This fixes the following DT schemas check errors:
meson-gxbb-nanopi-k2.dt.yaml: watchdog@98d0: compatible:0: 'amlogic,meson-gx-wdt' is not one of ['amlogic,meson-gxbb-wdt']
meson-gxl-s805x-libretech-ac.dt.yaml: watchdog@98d0: compatible:0: 'amlogic,meson-gx-wdt' is not one of ['amlogic,meson-gxbb-wdt']

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:13:34 -07:00
Neil Armstrong
599bfd512e arm64: dts: meson-gx: fix spifc compatible
This fixes the following DT schemas check errors:
meson-gxl-s805x-libretech-ac.dt.yaml: spi@8c80: compatible:0: 'amlogic,meson-gx-spifc' is not one of ['amlogic,meson6-spifc', 'amlogic,meson-gxbb-spifc']

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:13:34 -07:00
Neil Armstrong
9632691e1b arm64: dts: meson-gx: fix reset controller compatible
This fixes the following DT schemas check errors:
meson-gxbb-nanopi-k2.dt.yaml: reset-controller@4404: compatible:0: 'amlogic,meson-gx-reset' is not one of ['amlogic,meson8b-reset', 'amlogic,meson-gxbb-reset', 'amlogic,meson-axg-reset']

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:13:34 -07:00
Neil Armstrong
5e975c5dab arm64: dts: meson-gx: drop the vpu dmc memory cell
This fixes the following DT schemas check errors:
meson-gxl-s805x-libretech-ac.dt.yaml: vpu@d0100000: reg-names: Additional items are not allowed ('dmc' was unexpected)
meson-gxl-s805x-libretech-ac.dt.yaml: vpu@d0100000: reg-names: ['vpu', 'hhi', 'dmc'] is too long

The 'dmc' register area was replaced by the amlogic,canvas property
which was introduced in commit f172604342 ("arm64: dts: meson-gx:
add dmcbus and canvas nodes.") and commit cf34287986 ("arm64: dts:
meson-gx: Add canvas provider node to the vpu")

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:13:33 -07:00
Neil Armstrong
3ad6c9e357 arm64: dts: meson: fix ethernet mac reg format
This fixes the following DT schemas check errors:
meson-axg-s400.dt.yaml: soc: ethernet@ff3f0000:reg:0: [0, 4282318848, 0, 65536, 0, 4284695872, 0, 8] is too long
meson-axg-s400.dt.yaml: ethernet@ff3f0000: reg: [[0, 4282318848, 0, 65536, 0, 4284695872, 0, 8]] is too short
meson-g12a-u200.dt.yaml: soc: ethernet@ff3f0000:reg:0: [0, 4282318848, 0, 65536, 0, 4284695872, 0, 8] is too long
meson-g12a-u200.dt.yaml: ethernet@ff3f0000: reg: [[0, 4282318848, 0, 65536, 0, 4284695872, 0, 8]] is too short
meson-gxbb-nanopi-k2.dt.yaml: soc: ethernet@c9410000:reg:0: [0, 3376480256, 0, 65536, 0, 3364046144, 0, 4] is too long
meson-gxl-s805x-libretech-ac.dt.yaml: soc: ethernet@c9410000:reg:0: [0, 3376480256, 0, 65536, 0, 3364046144, 0, 4] is too lon

while here, also drop the redundant reg property from meson-gxl.dtsi
because it had the same value as meson-gx.dtsi from which it inherits.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:13:33 -07:00
Kevin Hilman
a833a15e59 arm64: dts: meson: g12a-common: add VRTC
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-08-29 16:13:33 -07:00
Andrew Murray
eb3aabbfbf arm64: atomics: Remove atomic_ll_sc compilation unit
We no longer fall back to out-of-line atomics on systems with
CONFIG_ARM64_LSE_ATOMICS where ARM64_HAS_LSE_ATOMICS is not set.

Remove the unused compilation unit which provided these symbols.

Signed-off-by: Andrew Murray <andrew.murray@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2019-08-29 15:53:49 +01:00
Andrew Murray
3337cb5aea arm64: avoid using hard-coded registers for LSE atomics
Now that we have removed the out-of-line ll/sc atomics we can give
the compiler the freedom to choose its own register allocation.

Remove the hard-coded use of x30.

Signed-off-by: Andrew Murray <andrew.murray@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2019-08-29 15:53:48 +01:00
Andrew Murray
addfc38672 arm64: atomics: avoid out-of-line ll/sc atomics
When building for LSE atomics (CONFIG_ARM64_LSE_ATOMICS), if the hardware
or toolchain doesn't support it the existing code will fallback to ll/sc
atomics. It achieves this by branching from inline assembly to a function
that is built with special compile flags. Further this results in the
clobbering of registers even when the fallback isn't used increasing
register pressure.

Improve this by providing inline implementations of both LSE and
ll/sc and use a static key to select between them, which allows for the
compiler to generate better atomics code. Put the LL/SC fallback atomics
in their own subsection to improve icache performance.

Signed-off-by: Andrew Murray <andrew.murray@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2019-08-29 15:53:42 +01:00
Christoph Hellwig
3e4e1d3fb8 arm64: document the choice of page attributes for pgprot_dmacoherent
Based on an email from Will Deacon.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Will Deacon <will@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
2019-08-29 16:43:33 +02:00
Christoph Hellwig
8e3a68fb55 dma-mapping: make dma_atomic_pool_init self-contained
The memory allocated for the atomic pool needs to have the same
mapping attributes that we use for remapping, so use
pgprot_dmacoherent instead of open coding it.  Also deduct a
suitable zone to allocate the memory from based on the presence
of the DMA zones.

Signed-off-by: Christoph Hellwig <hch@lst.de>
2019-08-29 16:43:33 +02:00
Christoph Hellwig
419e2f1838 dma-mapping: remove arch_dma_mmap_pgprot
arch_dma_mmap_pgprot is used for two things:

 1) to override the "normal" uncached page attributes for mapping
    memory coherent to devices that can't snoop the CPU caches
 2) to provide the special DMA_ATTR_WRITE_COMBINE semantics on older
    arm systems and some mips platforms

Replace one with the pgprot_dmacoherent macro that is already provided
by arm and much simpler to use, and lift the DMA_ATTR_WRITE_COMBINE
handling to common code with an explicit arch opt-in.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>	# m68k
Acked-by: Paul Burton <paul.burton@mips.com>		# mips
2019-08-29 16:43:22 +02:00
Andrew Murray
580fa1b874 arm64: Use correct ll/sc atomic constraints
The A64 ISA accepts distinct (but overlapping) ranges of immediates for:

 * add arithmetic instructions ('I' machine constraint)
 * sub arithmetic instructions ('J' machine constraint)
 * 32-bit logical instructions ('K' machine constraint)
 * 64-bit logical instructions ('L' machine constraint)

... but we currently use the 'I' constraint for many atomic operations
using sub or logical instructions, which is not always valid.

When CONFIG_ARM64_LSE_ATOMICS is not set, this allows invalid immediates
to be passed to instructions, potentially resulting in a build failure.
When CONFIG_ARM64_LSE_ATOMICS is selected the out-of-line ll/sc atomics
always use a register as they have no visibility of the value passed by
the caller.

This patch adds a constraint parameter to the ATOMIC_xx and
__CMPXCHG_CASE macros so that we can pass appropriate constraints for
each case, with uses updated accordingly.

Unfortunately prior to GCC 8.1.0 the 'K' constraint erroneously accepted
'4294967295', so we must instead force the use of a register.

Signed-off-by: Andrew Murray <andrew.murray@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2019-08-29 15:10:18 +01:00
Suman Anna
d6dabd6f59 arm64: dts: ti: k3-j721e-main: Fix gic-its node unit-address
The gic-its node unit-address has an additional zero compared
to the actual reg value. Fix it.

Fixes: 2d87061e70 ("arm64: dts: ti: Add Support for J721E SoC")
Reported-by: Robert Tivy <rtivy@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-08-29 16:05:00 +03:00
Suman Anna
389ce1a7c5 arm64: dts: ti: k3-am65-main: Fix gic-its node unit-address
The gic-its node unit-address has an additional zero compared
to the actual reg value. Fix it.

Fixes: ea47eed33a ("arm64: dts: ti: Add Support for AM654 SoC")
Reported-by: Robert Tivy <rtivy@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-08-29 16:05:00 +03:00
Suman Anna
7b472ced17 arm64: dts: ti: k3-j721e-main: Add hwspinlock node
The Main NavSS block on J721E SoCs contains a HwSpinlock IP instance that
is same as the IP on AM65x SoCs and similar to the IP on some OMAP SoCs.
Add the DT node for this on J721E SoCs. The node is present within the
Main NavSS block, and is added as a child node under the cbass_main_navss
interconnect node.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-08-29 16:05:00 +03:00
Suman Anna
75f535d097 arm64: dts: ti: k3-am65-main: Add hwspinlock node
The Main NavSS block on AM65x SoCs contains a HwSpinlock IP instance
that is similar to the IP on some OMAP SoCs. Add the DT node for this
on AM65x SoCs. The node is present within the NavSS block, and is
added as a child node under the cbass_main_navss interconnect node.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-08-29 16:04:59 +03:00
Nikhil Devshatwar
2dc61b58ef arm64: dts: k3-j721e: Add gpio-keys on common processor board
Common processor board for K3 J721E platform has two push buttons
namely SW10 and SW11.
Add a gpio-keys device node to model them as input keys in Linux.
Add required pinmux nodes to set GPIO pins as input.

Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-08-29 16:04:59 +03:00
Lokesh Vutla
6431862acd arm64: dts: ti: k3-j721e-common-proc-board: Disable unused gpio modules
There are 10 gpio instances inside SoC with 3 groups as below:
- Group1: main_gpio0, main_gpio2, main_gpio4, main_gpio6
- Group2: main_gpio1, main_gpio3, main_gpio5, main_gpio7
- Group3: wkup_gpio0, wkup_gpio1

Only one instance can be used in each group at a time. So use main_gpio0,
main_gpio1 and wkup_gpio0 for the current linux context and mark other
gpio nodes as disabled.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-08-29 16:04:59 +03:00
Lokesh Vutla
caaaa1f844 arm64: dts: ti: k3-j721e: Add gpio nodes in wakeup domain
Similar to the gpio groups in main domain, there is one gpio group
in wakup domain with 2 module instances in it. This gpio group pins
out 84 lines(6 banks). Add DT node for these 2 gpio module instances.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-08-29 16:04:59 +03:00
Lokesh Vutla
248f3eae99 arm64: dts: ti: k3-j721e: Add gpio nodes in main domain
There are 8 instances of gpio modules in main domain divided into 2 groups:
- Group1: gpio0, gpio2, gpio4, gpio6
- Group2: gpio1, gpio3, gpio5, gpio7

Groups are created to provide protection between two different processor
virtual worlds. There are x gpio lines coming out of each group. Each module
in a group has equal x gpio lines pinned out. There is a top level mux for
selecting the module instance for each pin coming out of group. Exactly
one module can be selected to control the corresponding pin. This muxing
can be controlled along the pad mux configuration registers.

Group1 pins out 128 lines(8 banks). Group 2 pins out 36 lines(2 banks).

Add DT nodes for each module instance in the main domain. Users should
make sure that correct gpio instance is selected in their pad configuration.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-08-29 16:04:59 +03:00
Lokesh Vutla
bf146a1a7c arm64: dts: ti: k3-j721e: Update the power domain cells
Update the power-domain cells to 2 and mark all devices as
exclusive. Main uart 0 is the debug console for processor boards
and it is used by different software entities like u-boot, atf,
linux simultaneously. So just mark main_uart0 as shared device
for common processor board.

Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-08-29 15:40:49 +03:00
Lokesh Vutla
c68272cb7e arm64: dts: ti: k3-am654: Update the power domain cells
Update the power-domain cells to 2 and mark all devices as
exclusive. Main uart 0 is the debug console for based boards
and it is used by different software entities like u-boot, atf,
linux. So just mark main_uart0 as shared device for base board.

Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-08-29 15:40:49 +03:00
Mark Rutland
f32c7a8e45 arm64: kpti: ensure patched kernel text is fetched from PoU
While the MMUs is disabled, I-cache speculation can result in
instructions being fetched from the PoC. During boot we may patch
instructions (e.g. for alternatives and jump labels), and these may be
dirty at the PoU (and stale at the PoC).

Thus, while the MMU is disabled in the KPTI pagetable fixup code we may
load stale instructions into the I-cache, potentially leading to
subsequent crashes when executing regions of code which have been
modified at runtime.

Similarly to commit:

  8ec4198743 ("arm64: mm: ensure patched kernel text is fetched from PoU")

... we can invalidate the I-cache after enabling the MMU to prevent such
issues.

The KPTI pagetable fixup code itself should be clean to the PoC per the
boot protocol, so no maintenance is required for this code.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2019-08-28 13:40:08 +01:00
Mark Rutland
b333b0ba23 arm64: fix fixmap copy for 16K pages and 48-bit VA
With 16K pages and 48-bit VAs, the PGD level of table has two entries,
and so the fixmap shares a PGD with the kernel image. Since commit:

  f9040773b7 ("arm64: move kernel image to base of vmalloc area")

... we copy the existing fixmap to the new fine-grained page tables at
the PUD level in this case. When walking to the new PUD, we forgot to
offset the PGD entry and always used the PGD entry at index 0, but this
worked as the kernel image and fixmap were in the low half of the TTBR1
address space.

As of commit:

  14c127c957 ("arm64: mm: Flip kernel VA space")

... the kernel image and fixmap are in the high half of the TTBR1
address space, and hence use the PGD at index 1, but we didn't update
the fixmap copying code to account for this.

Thus, we'll erroneously try to copy the fixmap slots into a PUD under
the PGD entry at index 0. At the point we do so this PGD entry has not
been initialised, and thus we'll try to write a value to a small offset
from physical address 0, causing a number of potential problems.

Fix this be correctly offsetting the PGD. This is split over a few steps
for legibility.

Fixes: 14c127c957 ("arm64: mm: Flip kernel VA space")
Reported-by: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Tested-by: Marc Zyngier <maz@kernel.org>
Acked-by: Steve Capper <Steve.Capper@arm.com>
Tested-by: Steve Capper <Steve.Capper@arm.com>
Tested-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2019-08-28 12:10:03 +01:00
René van Dorst
bd69baaace dt-bindings: net: ethernet: Update mt7622 docs and dts to reflect the new phylink API
This patch the removes the recently added mediatek,physpeed property.
Use the fixed-link property speed = <2500> to set the phy in 2.5Gbit.
See mt7622-bananapi-bpi-r64.dts for a working example.

Signed-off-by: René van Dorst <opensource@vdorst.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-27 20:19:27 -07:00
James Morse
e8688ba387 arm64: KVM: Device mappings should be execute-never
Since commit 2f6ea23f63 ("arm64: KVM: Avoid marking pages as XN in
Stage-2 if CTR_EL0.DIC is set"), KVM has stopped marking normal memory
as execute-never at stage2 when the system supports D->I Coherency at
the PoU. This avoids KVM taking a trap when the page is first executed,
in order to clean it to PoU.

The patch that added this change also wrapped PAGE_S2_DEVICE mappings
up in this too. The upshot is, if your CPU caches support DIC ...
you can execute devices.

Revert the PAGE_S2_DEVICE change so PTE_S2_XN is always used
directly.

Fixes: 2f6ea23f63 ("arm64: KVM: Avoid marking pages as XN in Stage-2 if CTR_EL0.DIC is set")
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
2019-08-27 18:16:02 +01:00
Will Deacon
5c062ef415 arm64: kvm: Replace hardcoded '1' with SYS_PAR_EL1_F
Now that we have a definition for the 'F' field of PAR_EL1, use that
instead of coding the immediate directly.

Acked-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2019-08-27 17:38:41 +01:00
Will Deacon
42f91093b0 arm64: mm: Ignore spurious translation faults taken from the kernel
Thanks to address translation being performed out of order with respect to
loads and stores, it is possible for a CPU to take a translation fault when
accessing a page that was mapped by a different CPU.

For example, in the case that one CPU maps a page and then sets a flag to
tell another CPU:

	CPU 0
	-----

	MOV	X0, <valid pte>
	STR	X0, [Xptep]	// Store new PTE to page table
	DSB	ISHST
	ISB
	MOV	X1, #1
	STR	X1, [Xflag]	// Set the flag

	CPU 1
	-----

loop:	LDAR	X0, [Xflag]	// Poll flag with Acquire semantics
	CBZ	X0, loop
	LDR	X1, [X2]	// Translates using the new PTE

then the final load on CPU 1 can raise a translation fault because the
translation can be performed speculatively before the read of the flag and
marked as "faulting" by the CPU. This isn't quite as bad as it sounds
since, in reality, code such as:

	CPU 0				CPU 1
	-----				-----
	spin_lock(&lock);		spin_lock(&lock);
	*ptr = vmalloc(size);		if (*ptr)
	spin_unlock(&lock);			foo = **ptr;
					spin_unlock(&lock);

will not trigger the fault because there is an address dependency on CPU 1
which prevents the speculative translation. However, more exotic code where
the virtual address is known ahead of time, such as:

	CPU 0				CPU 1
	-----				-----
	spin_lock(&lock);		spin_lock(&lock);
	set_fixmap(0, paddr, prot);	if (mapped)
	mapped = true;				foo = *fix_to_virt(0);
	spin_unlock(&lock);		spin_unlock(&lock);

could fault. This can be avoided by any of:

	* Introducing broadcast TLB maintenance on the map path
	* Adding a DSB;ISB sequence after checking a flag which indicates
	  that a virtual address is now mapped
	* Handling the spurious fault

Given that we have never observed a problem due to this under Linux and
future revisions of the architecture are being tightened so that
translation table walks are effectively ordered in the same way as explicit
memory accesses, we no longer treat spurious kernel faults as fatal if an
AT instruction indicates that the access does not trigger a translation
fault.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2019-08-27 17:38:36 +01:00
Will Deacon
e8620cff99 arm64: sysreg: Add some field definitions for PAR_EL1
PAR_EL1 is a mysterious creature, but sometimes it's necessary to read
it when translating addresses in situations where we cannot walk the
page table directly.

Add a couple of system register definitions for the fault indication
field ('F') and the fault status code ('FST').

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2019-08-27 17:38:33 +01:00
Will Deacon
eb6a4dcce3 arm64: mm: Add ISB instruction to set_pgd()
Commit 6a4cbd63c25a ("Revert "arm64: Remove unnecessary ISBs from
set_{pte,pmd,pud}"") reintroduced ISB instructions to some of our
page table setter functions in light of a recent clarification to the
Armv8 architecture. Although 'set_pgd()' isn't currently used to update
a live page table, add the ISB instruction there too for consistency
with the other macros and to provide some future-proofing if we use it
on live tables in the future.

Reported-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2019-08-27 17:38:30 +01:00
Will Deacon
51696d346c arm64: tlb: Ensure we execute an ISB following walk cache invalidation
05f2d2f83b ("arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable")
added a new TLB invalidation helper which is used when freeing
intermediate levels of page table used for kernel mappings, but is
missing the required ISB instruction after completion of the TLBI
instruction.

Add the missing barrier.

Cc: <stable@vger.kernel.org>
Fixes: 05f2d2f83b ("arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable")
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2019-08-27 17:38:26 +01:00
Will Deacon
d0b7a302d5 Revert "arm64: Remove unnecessary ISBs from set_{pte,pmd,pud}"
This reverts commit 24fe1b0efa.

Commit 24fe1b0efa ("arm64: Remove unnecessary ISBs from
set_{pte,pmd,pud}") removed ISB instructions immediately following updates
to the page table, on the grounds that they are not required by the
architecture and a DSB alone is sufficient to ensure that subsequent data
accesses use the new translation:

  DDI0487E_a, B2-128:

  | ... no instruction that appears in program order after the DSB
  | instruction can alter any state of the system or perform any part of
  | its functionality until the DSB completes other than:
  |
  | * Being fetched from memory and decoded
  | * Reading the general-purpose, SIMD and floating-point,
  |   Special-purpose, or System registers that are directly or indirectly
  |   read without causing side-effects.

However, the same document also states the following:

  DDI0487E_a, B2-125:

  | DMB and DSB instructions affect reads and writes to the memory system
  | generated by Load/Store instructions and data or unified cache
  | maintenance instructions being executed by the PE. Instruction fetches
  | or accesses caused by a hardware translation table access are not
  | explicit accesses.

which appears to claim that the DSB alone is insufficient.  Unfortunately,
some CPU designers have followed the second clause above, whereas in Linux
we've been relying on the first. This means that our mapping sequence:

	MOV	X0, <valid pte>
	STR	X0, [Xptep]	// Store new PTE to page table
	DSB	ISHST
	LDR	X1, [X2]	// Translates using the new PTE

can actually raise a translation fault on the load instruction because the
translation can be performed speculatively before the page table update and
then marked as "faulting" by the CPU. For user PTEs, this is ok because we
can handle the spurious fault, but for kernel PTEs and intermediate table
entries this results in a panic().

Revert the offending commit to reintroduce the missing barriers.

Cc: <stable@vger.kernel.org>
Fixes: 24fe1b0efa ("arm64: Remove unnecessary ISBs from set_{pte,pmd,pud}")
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2019-08-27 17:38:15 +01:00
Will Deacon
ebef746543 arm64: smp: Treat unknown boot failures as being 'stuck in kernel'
When we fail to bring a secondary CPU online and it fails in an unknown
state, we should assume the worst and increment 'cpus_stuck_in_kernel'
so that things like kexec() are disabled.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2019-08-27 17:37:05 +01:00
Will Deacon
5b1cfe3a0b arm64: smp: Don't enter kernel with NULL stack pointer or task struct
Although SMP bringup is inherently racy, we can significantly reduce
the window during which secondary CPUs can unexpectedly enter the
kernel by sanity checking the 'stack' and 'task' fields of the
'secondary_data' structure. If the booting CPU gave up waiting for us,
then they will have been cleared to NULL and we should spin in a WFE; WFI
loop instead.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2019-08-27 17:37:02 +01:00
Will Deacon
0e1645557d arm64: smp: Increase secondary CPU boot timeout value
When many debug options are enabled simultaneously (e.g. PROVE_LOCKING,
KMEMLEAK, DEBUG_PAGE_ALLOC, KASAN etc), it is possible for us to timeout
when attempting to boot a secondary CPU and give up. Unfortunately, the
CPU will /eventually/ appear, and sit in the background happily stuck
in a recursive exception due to a NULL stack pointer.

Increase the timeout to 5s, which will of course be enough for anybody.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2019-08-27 17:36:50 +01:00
Gregory CLEMENT
c00bc38354 arm64: dts: marvell: Add cpu clock node on Armada 7K/8K
Add cpu clock node on AP

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-08-27 16:39:22 +02:00
Miquel Raynal
96018a6faf arm64: dts: marvell: Convert 7k/8k usb-phy properties to phy-supply
Update Aramda 7k/8k DTs to use the phy-supply property of the (recent)
generic PHY framework instead of the (legacy) usb-phy preperty. Both
enable the supply when the PHY is enabled.

The COMPHY nodes only provide SERDES lanes configuration. The power
supply that is represented by the phy-supply property is just a
regulator wired to the USB connector, hence the creation of connector
nodes as child of the COMPHY nodes and the supply attached to it.

Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-08-27 16:30:03 +02:00
Miquel Raynal
ce55522c03 arm64: dts: marvell: Add 7k/8k PHYs in PCIe nodes
Fill-in the missing PCIe phys/phy-names DT properties of Armada 7k/8k
based boards.

The MacchiatoBin is a bit particular as the Armada8k-PCI IP supports
x4 link widths and in this case the PHY for each lane must be
referenced.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-08-27 16:20:16 +02:00
Miquel Raynal
01d0deba28 arm64: dts: marvell: Add 7k/8k PHYs in USB3 nodes
Fill-in the missing USB3 phys/phy-names DT properties of Armada 7k/8k
based boards. Only update nodes actually enabling USB3 in the default
(mainline) configuration. A few USB nodes are enabled but there is
only USB2 working on them.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-08-27 16:19:28 +02:00
Miquel Raynal
d04abe999e arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes
Fill-in the missing SATA phys/phy-names DT properties of Armada 7k/8k
based boards.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-08-27 16:17:28 +02:00
Miquel Raynal
93ab25e6f5 arm64: dts: marvell: Add CP110 COMPHY clocks
Declare the three clocks feeding the COMPHY block.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-08-27 16:15:28 +02:00
Marek Behún
535462c244 arm64: dts: marvell: armada-37xx: add mailbox node
This adds the rWTM BIU mailbox node for communication with the secure
processor. The driver already exists in
drivers/mailbox/armada-37xx-rwtm-mailbox.c.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Gregory Clement <gregory.clement@bootlin.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-08-27 15:57:17 +02:00
Vinod Koul
1dd70853f8 arm64: dts: sdm845: Add parent clock for rpmhcc
RPM clock controller has parent as xo, so specify that in DT node for
rpmhcc

Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-08-26 17:43:23 -07:00
Anson Huang
24e8a5db8a arm64: dts: imx8mq: Add system counter node
Add i.MX8MQ system counter node to enable timer-imx-sysctr
broadcast timer driver.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2019-08-27 00:31:39 +02:00
Anson Huang
5b0221bf7b arm64: dts: imx8mm: Add system counter node
Add i.MX8MM system counter node to enable timer-imx-sysctr
broadcast timer driver.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2019-08-27 00:31:39 +02:00
Guido Günther
215701807e arm64: dts: imx8mq: Add mux controller to iomuxc_gpr
The only mux controls the MIPI DSI input selection.

Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-24 22:47:07 +02:00
Jon Nettleton
ffe0f9a0ba arm64: dts: fsl: add support for Hummingboard Pulse
The SolidRun Hummingboard Pulse carrier board carries the SolidRun
i.MX8MQ based SOM.

Notably missing is PCIe support that depends on analog PLLOUT clock.
Current imx clk driver does not support this clock.

Signed-off-by: Jon Nettleton <jon@solid-run.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-24 22:35:43 +02:00
Song Hui
afd3b35fdb arm64: dts: ls1088a: update gpio compatible
add ls1088a gpio specify compatible.

Signed-off-by: Song Hui <hui.song_1@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-24 21:13:21 +02:00
Gary Bisson
90771e50d5 arm64: dts: imx: Add i.mx8mq nitrogen8m basic dts support
Add basic dts support for i.MX8MQ NITROGEN8M.

Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
[Dafna: porting vendor's code to mainline]
Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-24 21:03:06 +02:00
Chuanhua Han
34a33ba609 arm64: dts: ls1088a-qds: Add the spi-flash nodes under the DSPI controller
This patch adds the spi-flash nodes under the DSPI controller for
ls1088a-qds boards.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-24 20:35:10 +02:00
Chuanhua Han
60ca9248e4 arm64: dts: ls1088a: Add the DSPI controller node
This patch adds the DSPI controller node for ls1088a boards.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-24 20:34:51 +02:00