mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 00:10:10 +07:00
arm64: dts: fsl: add support for Hummingboard Pulse
The SolidRun Hummingboard Pulse carrier board carries the SolidRun i.MX8MQ based SOM. Notably missing is PCIe support that depends on analog PLLOUT clock. Current imx clk driver does not support this clock. Signed-off-by: Jon Nettleton <jon@solid-run.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Jon Nettleton
Shawn Guo
parent
afd3b35fdb
commit
ffe0f9a0ba
@ -23,6 +23,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
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256
arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts
Normal file
256
arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts
Normal file
@ -0,0 +1,256 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2018 Jon Nettleton <jon@solid-run.com>
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*/
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/dts-v1/;
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#include "dt-bindings/usb/pd.h"
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#include "imx8mq-sr-som.dtsi"
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/ {
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model = "SolidRun i.MX8MQ HummingBoard Pulse";
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compatible = "solidrun,hummingboard-pulse", "fsl,imx8mq";
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chosen {
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stdout-path = &uart1;
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};
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reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
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};
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reg_v_5v0: regulator-v-5v0 {
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compatible = "regulator-fixed";
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regulator-name = "v_5v0";
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regulator-max-microvolt = <5000000>;
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regulator-min-microvolt = <5000000>;
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regulator-always-on;
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};
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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clock-frequency = <100000>;
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status = "okay";
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typec_ptn5100: usb-typec@50 {
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compatible = "nxp,ptn5110";
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reg = <0x50>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_typec>;
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interrupt-parent = <&gpio1>;
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interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
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connector {
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compatible = "usb-c-connector";
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label = "USB-C";
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data-role = "dual";
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power-role = "dual";
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try-power-role = "sink";
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source-pdos = <PDO_FIXED(5000, 2000,
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PDO_FIXED_USB_COMM |
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PDO_FIXED_SUSPEND |
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PDO_FIXED_EXTPOWER)>;
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sink-pdos = <PDO_FIXED(5000, 2000,
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PDO_FIXED_USB_COMM |
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PDO_FIXED_SUSPEND |
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PDO_FIXED_EXTPOWER)
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PDO_FIXED(9000, 2000,
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PDO_FIXED_USB_COMM |
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PDO_FIXED_SUSPEND |
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PDO_FIXED_EXTPOWER)>;
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op-sink-microwatt = <9000000>;
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port {
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typec1_dr_sw: endpoint {
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remote-endpoint = <&usb1_drd_sw>;
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};
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};
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};
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};
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};
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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clock-frequency = <100000>;
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status = "okay";
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rtc@69 {
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compatible = "abracon,ab1805";
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reg = <0x69>;
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abracon,tc-diode = "schottky";
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abracon,tc-resistor = <3>;
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};
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};
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&uart2 { /* J35 header */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
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assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
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status = "okay";
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};
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&uart3 { /* Mikrobus */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
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assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
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uart-has-rtscts;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&usb_dwc3_0 {
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dr_mode = "otg";
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status = "okay";
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port {
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usb1_drd_sw: endpoint {
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remote-endpoint = <&typec1_dr_sw>;
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};
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};
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};
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&usb_dwc3_1 {
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dr_mode = "host";
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status = "okay";
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};
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&usb3_phy0 {
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status = "okay";
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};
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&usb3_phy1 {
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl_hog: hoggrp {
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fsl,pins = <
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/* MikroBus Analog */
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MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x41
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/* MikroBus Reset */
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MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x41
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/*
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* The following 2 pins need to be commented out and
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* reconfigured to enable RTS/CTS on UART3
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*/
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/* MikroBus PWM */
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MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x41
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/* MikroBus INT */
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MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
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MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
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MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
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>;
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};
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pinctrl_typec: typecgrp {
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fsl,pins = <
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MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
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MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x17059
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
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MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
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MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
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/*
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* These pins are by default GPIO on the Mikro Bus
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* Header. To use RTS/CTS on UART3 comment them out
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* of the hoggrp and enable them here
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*/
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/* MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 */
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/* MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 */
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2grpgpio {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
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>;
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};
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pinctrl_usdhc2_vmmc: usdhc2vmmcgpio {
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fsl,pins = <
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MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x41
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
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MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
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MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf
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MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
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>;
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};
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};
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309
arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi
Normal file
309
arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi
Normal file
@ -0,0 +1,309 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2018 Jon Nettleton <jon@solid-run.com>
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*/
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#include "imx8mq.dtsi"
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/ {
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reg_vdd_3v3: regulator-vdd-3v3 {
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compatible = "regulator-fixed";
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regulator-always-on;
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regulator-name = "vdd_3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <2>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <4>;
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};
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};
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clock-frequency = <400000>;
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status = "okay";
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pmic: pmic@8 {
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compatible = "fsl,pfuze100";
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reg = <0x08>;
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regulators {
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sw1a_reg: sw1ab {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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};
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sw1c_reg: sw1c {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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};
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sw2_reg: sw2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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sw3a_reg: sw3ab {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1975000>;
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regulator-always-on;
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};
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sw4_reg: sw4 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-always-on;
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};
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vgen1_reg: vgen1 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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vgen2_reg: vgen2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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regulator-always-on;
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};
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vgen3_reg: vgen3 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen4_reg: vgen4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen5_reg: vgen5 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen6_reg: vgen6 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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};
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};
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&pgc_gpu{
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power-supply = <&sw1a_reg>;
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};
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&pgc_vpu {
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power-supply = <&sw1c_reg>;
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};
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&qspi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi>;
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status = "okay";
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/* SPI flash; not assembled by default */
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spi_flash: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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compatible = "micron,n25q256a", "jedec,spi-nor";
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spi-max-frequency = <29000000>;
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status = "disabled";
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};
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};
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&uart1 { /* console */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
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assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
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assigned-clock-rates = <25000000>;
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status = "okay";
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};
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&uart4 { /* ublox BT */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4>;
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assigned-clocks = <&clk IMX8MQ_CLK_UART4>;
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assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
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assigned-clock-rates = <80000000>;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_fec1: fec1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
|
||||
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
|
||||
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
|
||||
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
|
||||
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
|
||||
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
|
||||
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
|
||||
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
|
||||
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
|
||||
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
|
||||
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
|
||||
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
|
||||
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
|
||||
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie0: pcie0grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x74
|
||||
MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x16
|
||||
MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_qspi: qspigrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
|
||||
MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
|
||||
MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
|
||||
MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
|
||||
MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
|
||||
MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
|
||||
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
|
||||
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
|
||||
MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart4: uart4grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49
|
||||
MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49
|
||||
MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
|
||||
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
|
||||
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
|
||||
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user