Commit Graph

182605 Commits

Author SHA1 Message Date
Manuel Lauss
acc4d245a7 MIPS: Alchemy: Fix Au1100 ethernet build failure
Don't define platform info for second mac on au1100 (which only has a
single mac).

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/1004/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:45 +01:00
Manuel Lauss
570cb456ef MIPS: Alchemy: Repair db1500/bosporus builds
A few hunks somehow ended up outside their #ifdef/endif blocks,
leading to -Werror-induces build failures.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/1003/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:45 +01:00
Yoichi Yuasa
d891a53992 MIPS: ARC: Cleanup unused definitions from sgialib.h
Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org>
Cc: linux-mips <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/979/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:45 +01:00
Bjorn Helgaas
8190471087 MIPS: Cobalt: convert legacy port addresses to GT-64111 bus addresses
The GT-64111 PCI host bridge has no address translation mechanism, so
it can't generate legacy port accesses.  This quirk fixes legacy device
port resources to contain the bus addresses actually generated by the
GT-64111.

I think this is the approach Ben Herrenschmidt suggested long ago:
    http://marc.info/?l=linux-kernel&m=119733290624544&w=2

This allows us to remove the IORESOURCE_PCI_FIXED hack from
pcibios_fixup_device_resources(), which converts bus addresses to CPU
addresses.  IORESOURCE_PCI_FIXED denotes resources that can't be moved;
it has nothing to do with converting bus to CPU addresses.

Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com>
Cc: Yoichi Yuasa <yuasa@linux-mips.org>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: linux-mips@linux-mips.org
Tested-by: Yoichi Yuasa <yuasa@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/998/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:44 +01:00
Manuel Lauss
11b897cf84 MIPS: Alchemy: use 36bit addresses for PCMCIA resources.
On Alchemy the PCMCIA area lies at the end of the chips 36bit system bus
area.  Currently, addresses at the far end of the 32bit area are assumed
to belong to the PCMCIA area and fixed up to the real 36bit address before
being passed to ioremap().

A previous commit enabled 64 bit physical size for the resource datatype on
Alchemy and this allows to use the correct 36bit addresses when registering
the PCMCIA sockets.

This patch removes the 32-to-36bit address fixup and registers the Alchemy
demo board pcmcia socket with the correct 36bit physical addresses.

Tested on DB1200, with a CF card (ide-cs driver) and a 3c589 PCMCIA ethernet
card.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Cc: Manuel Lauss <manuel.lauss@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/994/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:43 +01:00
Ralf Baechle
b9b37787d2 MIPS: Cobalt: Fix theoretical port aliasing issue
Because the VIA SuperIO chip only decodes 24 bits of address space but port
address space currently being configured as 32MB there is the theoretical
possibility of aliases within the I/O port address range.

The complicated solution is to reserve all address range that potencially
could cause such aliases.  But with the PCI spec limiting port allocations
for devices to a maximum of 256 bytes 16MB of port address space already is
way more than one would ever expect to be used so we just reduce the port
space to 16MB.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
To: Yoichi Yuasa <yuasa@linux-mips.org>
Cc: Bjorn Helgaas <bjorn.helgaas@hp.com>
Cc: linux-mips@linux-mips.org
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Patchwork: http://patchwork.linux-mips.org/patch/995/
2010-02-27 12:53:43 +01:00
Matt Turner
2a5d66511a MIPS: Use ALIGN(x, bytes) instead of __ALIGN_MASK(x, bytes - 1)
ALIGN(x, bytes) expands to __ALIGN_MASK(x, bytes - 1), so use the one
that is most clear.

Signed-off-by: Matt Turner <mattst88@gmail.com>
To: linux-mips@linux-mips.org
Cc: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/999/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:43 +01:00
David Daney
bba9076058 MIPS: Crazy spinlock speed test.
This is just a test program for raw_spinlocks.  The main reason I
wrote it is to validate my spinlock changes that I sent in a previous
patch.

To use it enable CONFIG_DEBUG_FS and CONFIG_SPINLOCK_TEST then at run
time do:

# mount -t debugfs none /sys/kernel/debug/
# cat /sys/kernel/debug/mips/spin_single
# cat /sys/kernel/debug/mips/spin_multi

On my 600MHz octeon cn5860 (16 CPUs) I get

		spin_single	spin_multi
base		106885		247941
spinlock_patch	75194		219465

This shows that for uncontended locks the spinlock patch gives 41%
improvement and for contended locks 12% improvement (1/time).

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/969/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:42 +01:00
David Daney
500c2e1fdb MIPS: Optimize spinlocks.
The current locking mechanism uses a ll/sc sequence to release a
spinlock.  This is slower than a wmb() followed by a store to unlock.

The branching forward to .subsection 2 on sc failure slows down the
contended case.  So we get rid of that part too.

Since we are now working on naturally aligned u16 values, we can get
rid of a masking operation as the LHU already does the right thing.
The ANDI are reversed for better scheduling on multi-issue CPUs

On a 12 CPU 750MHz Octeon cn5750 this patch improves ipv4 UDP packet
forwarding rates from 3.58*10^6 PPS to 3.99*10^6 PPS, or about 11%.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/937/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:42 +01:00
Manuel Lauss
e275ed5ee9 MIPS: Alchemy: devboard PM needs to save CPLD registers.
Save/restore CPLD registers when doing suspend-to-ram; this fixes issues
with harddisk and ethernet not working correctly when resuming on DB1200.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/986/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:41 +01:00
David VomLehn
81fc017954 MIPS: PowerTV: Eliminate duplicate opcode definition macros
Change to different macros for assembler macros since the old names in
powertv_setup.c were co-opted for use in asm/asm.h. This broken the
build for the powertv platform. This patch introduces new macros based on
the new macros in asm.h to take the place of the old macro values.

Signed-off-by: David VomLehn <dvomlehn@cisco.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/985/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:41 +01:00
Ralf Baechle
3b439470e3 MIPS: Lemote 2F: Move printks out of port_access_lock.
No point in protecting them and printks are sloow.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:41 +01:00
Ralf Baechle
7fe2d9c41d MIPS: PNX833x: Convert IRQ controller locks to raw spinlocks.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:41 +01:00
David Daney
541247f4d2 MIPS: Octeon: Replace spinlock with raw_spinlocks in dma-octeon.c.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/973/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:40 +01:00
David Daney
399614226c MIPS: Octeon: Replace rwlocks in irq_chip handlers with raw_spinlocks.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/972/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:40 +01:00
Ralf Baechle
4837a661a5 MIPS: Octeon: Convert octeon_irq_msi_lock to raw spinlock.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:40 +01:00
Ralf Baechle
f1d39e6ed7 MIPS: Loongson: Remove pointless sample_lock from oprofile code.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:39 +01:00
Ralf Baechle
36946d7387 MIPS: SNI: Convert sni_rm200_i8259A_lock to raw spinlock.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:39 +01:00
Ralf Baechle
8965087055 MIPS: i8259: Convert IRQ controller lock to raw spinlock.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:38 +01:00
Ralf Baechle
598c5abad7 MIPS: IP27: Convert nmi_lock lock to arch spinlock;
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:38 +01:00
Ralf Baechle
2ba53e3712 MIPS: IP27: Remove code obfuscation by enter_panic_mode().
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:38 +01:00
Ralf Baechle
34ee414847 MIPS: GT641xx: Convert timer lock to raw spinlock.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:37 +01:00
Ralf Baechle
da4afffc1d MIPS: Alchemy: Simplify DMA channel allocation code.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Cc: Manuel Lauss <manuel.lauss@googlemail.com>
2010-02-27 12:53:37 +01:00
Ralf Baechle
2bd0073656 MIPS: Yosemite: Convert SMP startup lock to arch spinlock.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:37 +01:00
Ralf Baechle
1a73f0478a MIPS: Alchemy: Remove time_lock.
The sole user is au1xxx_calc_clock() which is only used in early bootup
where the is no paralellism thus no race condition to protect against.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Cc: Manuel Lauss <manuel.lauss@googlemail.com>
2010-02-27 12:53:36 +01:00
Ralf Baechle
32baba2fb7 MIPS: DEC: Convert KN01 lock to raw spinlock.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:36 +01:00
Ralf Baechle
d8d607d59e MIPS: BCM63xx: Convert timer locks to raw spinlocks.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:35 +01:00
Ralf Baechle
c45ef44f47 MIPS: PowerTV: Convert IRQ controller lock to raw spinlock.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Cc: David VomLehn <dvomlehn@cisco.com>
2010-02-27 12:53:34 +01:00
Ralf Baechle
a963dc70a2 MIPS: Malta: Convert IRQ controller lock to raw spinlock.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:32 +01:00
Ralf Baechle
ed14bbb24e MIPS: SB1480: Convert IRQ controller lock to raw spinlock.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:32 +01:00
Ralf Baechle
5772f6deb6 MIPS: SB1250: Convert IRQ controller lock to raw spinlock.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:32 +01:00
Ralf Baechle
f2c194a005 MIPS: GT641xx: Convert IRQ controller lock to raw spinlock.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:31 +01:00
Ralf Baechle
4a41abe596 MIPS: Jazz: Convert irq controller lock to raw spinlock.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:31 +01:00
Ralf Baechle
4a8a738de6 MIPS: Make various locks static.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:30 +01:00
David Daney
559e25a5e3 Staging: Octeon: Remove /proc/octeon_ethernet_stats
This file shouldn't be in /proc, so we remove it.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
To: netdev@vger.kernel.org
To: gregkh@suse.de
Patchwork: http://patchwork.linux-mips.org/patch/970/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:30 +01:00
David Daney
ec977c5b47 Staging: Octeon: Reformat a bunch of comments.
Many of the comments didn't follow kerneldoc guidlines.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
To: netdev@vger.kernel.org
To: gregkh@suse.de
Patchwork: http://patchwork.linux-mips.org/patch/971/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:30 +01:00
David Daney
4898c56010 Staging: Octeon: Free transmit SKBs in a timely manner
If we wait for the once-per-second cleanup to free transmit SKBs,
sockets with small transmit buffer sizes might spend most of their
time blocked waiting for the cleanup.

Normally we do a cleanup for each transmitted packet.  We add a
watchdog type timer so that we also schedule a timeout for 150uS after
a packet is transmitted.  The watchdog is reset for each transmitted
packet, so for high packet rates, it never expires.  At these high
rates, the cleanups are done for each packet so the extra watchdog
initiated cleanups are neither needed nor triggered.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
To: netdev@vger.kernel.org
To: gregkh@suse.de
Cc: Eric Dumazet <eric.dumazet@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/968/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

This version has spelling and comment changes based on feedback from
Eric Dumazet.
2010-02-27 12:53:30 +01:00
David Daney
86568dc41e MIPS: Octeon: Do proper acknowledgment of CIU timer interrupts.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
To: netdev@vger.kernel.org
To: gregkh@suse.de
Patchwork: http://patchwork.linux-mips.org/patch/967/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:29 +01:00
David Daney
f8c2648666 Staging: Octeon: Run phy bus accesses on a workqueue.
When directly accessing a phy, we must acquire the mdio bus lock.  To
do that we cannot be in interrupt context, so we need to move these
operations to a workqueue.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
To: netdev@vger.kernel.org
To: gregkh@suse.de
Patchwork: http://patchwork.linux-mips.org/patch/965/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:29 +01:00
David Daney
1d08f00d57 Staging: octeon: remove unneeded includes
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
To: netdev@vger.kernel.org
To: gregkh@suse.de
Patchwork: http://patchwork.linux-mips.org/patch/964/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:28 +01:00
Yoichi Yuasa
d007f991a8 MIPS: Use generic ucontext.h
Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org>
Cc: linux-mips <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/959/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:27 +01:00
Yoichi Yuasa
7b012cee61 MIPS: Use generic serial.h
Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org>
Cc: linux-mips <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/960/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:27 +01:00
Yoichi Yuasa
f51e5a0772 MIPS: Use generic parport.h
Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org>
Cc: linux-mips <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/958/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:27 +01:00
Yoichi Yuasa
1a6e8963e0 MIPS: Use generic current.h
Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org>
Cc: linux-mips <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/957/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:27 +01:00
David Daney
27a5bd6457 MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/955/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:26 +01:00
David Daney
6f329468f3 MIPS: Give Octeon+ CPUs their own cputype.
This allows us to treat them differently at runtime.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/951/
Patchwork: http://patchwork.linux-mips.org/patch/987/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:26 +01:00
David Daney
6dd9344cfc MIPS: Implement Read Inhibit/eXecute Inhibit
The SmartMIPS ASE specifies how Read Inhibit (RI) and eXecute Inhibit
(XI) bits in the page tables work.  The upper two bits of EntryLo{0,1}
are RI and XI when the feature is enabled in the PageGrain register.
SmartMIPS only covers 32-bit systems.  Cavium Octeon+ extends this to
64-bit systems by continuing to place the RI and XI bits in the top of
EntryLo even when EntryLo is 64-bits wide.

Because we need to carry the RI and XI bits in the PTE, the layout of
the PTE is changed.  There is a two instruction overhead in the TLB
refill hot path to get the EntryLo bits into the proper position.
Also the TLB load exception has to probe the TLB to check if RI or XI
caused the exception.

Also of note is that the layout of the PTE bits is done at compile and
runtime rather than statically.  In the 32-bit case this allows for
the same number of PFN bits as before the patch as the _PAGE_HUGE is
not supported in 32-bit kernels (we have _PAGE_NO_EXEC and
_PAGE_NO_READ instead of _PAGE_READ and _PAGE_HUGE).

The patch is tested on Cavium Octeon+, but should also work on 32-bit
systems with the Smart-MIPS ASE.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/952/
Patchwork: http://patchwork.linux-mips.org/patch/956/
Patchwork: http://patchwork.linux-mips.org/patch/962/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:26 +01:00
David Daney
32546f38fa MIPS: Add TLBR and ROTR to uasm.
The soon to follow Read Inhibit/eXecute Inhibit patch needs TLBR and
ROTR support in uasm.  We also add a UASM_i_ROTR macro.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/953/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:25 +01:00
David Daney
9fe2e9d6f5 MIPS: Add accessor functions and bit definitions for c0_PageGrain
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/950/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:25 +01:00
David Daney
9b8c38917b MIPS: Use 64-bit stores to c0_entrylo on 64-bit kernels.
64-bit CPUs have 64-bit c0_entrylo{0,1} registers.  We should use the
64-bit dmtc0 instruction to set them.  This becomes important if we
want to set the RI and XI bits present in some processors.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/954/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:25 +01:00