This introduces the first OpenPower Power9 BMC system, Romulus. Romulus is
based on the ast2500 SoC from Aspeed.
These commits also add newly upstreamed drivers to the Palmetto BMC and ast2500
eval board. We now have working network, ipmi bt, gpio and pinmux on all platforms.
ARM: dts: aspeed: Add Romulus BMC platform
ARM: dts: aspeed: Add ftgmac100 to g4 and g5 platforms
ARM: dts: aspeed: Correct palmetto device tree
ARM: dts: aspeed: Reserve framebuffer memory
ARM: dts: aspeed-g5: Add gpio controller to devicetree
ARM: dts: aspeed-g5: Add syscon and pin controller nodes
ARM: dts: aspeed-g5: Add LPC Controller node
ARM: dts: aspeed-g5: Add SoC Display Controller node
ARM: dts: aspeed-g4: Add gpio controller to devicetree
ARM: dts: aspeed-g4: Add syscon and pin controller nodes
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJYfpvhAAoJEGt2WQeBR3CeDxcQAKrPdsPz7guceN9j6I9JU9Ys
NBC0SHY0uavqidvRSOyXSbYp/uWEd+A9jAlaj+w9mfI9y+7gsmYOjtdAdY80L8RB
XLUZdKjwoSxIv80YLVnBfz+jPwQRPkzSihqgy+bFr+BLe5n9S/QRDJfOiUfu37X0
SM36ax1Tc6/LDaUa8tqrSE2IpCPa0h0ewvw9i2581zLznTWaY/JwJMqeJzl98+8P
Q4P8PJYUz/KmjTya4L+NSmJ2ng2TSWcsY7fz3a4hI5UZYsTKsppnEpFlADIWTTLI
65AfGuMahpXiHWr4v/YPVgpHwTlaVaTGrbyFrBznATkx+rud1wmihkMAmqLylgfo
5nui4yLZSaELB/Yc2I0lIoEZJiqLIOMKw2vuJUH7A6r+yDIMzpAYfkTOsfjAk//I
3HPVEsnEP+ZwhhDK2s9ki5B3EV0BOVxdMROSpKvcOhxEuebv6MioNU1mTuLFxWm9
UDqjuUsEK2LfzJqO20pnEtKOAUBlCYFvIJ5i6bSi+O7SZACA6++0WNIoomAWHFjY
ukm4dvjBq93tVr8NC7pbIxmk1WAmpI7BLWWkTNyukw3IuaF3SZar3+V23ODEOm0y
P3JfIFxwmqwsZXZWGMKD6krFB541h/J8ag0kydxZXHrvc1Cm+mFER3hyEEk0HYrS
ik2OWkXI90IeZHXkD6DD
=BeSl
-----END PGP SIGNATURE-----
Merge tag 'aspeed-4.11-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed into next/dt
Aspeed devicetree updates for 4.11
This introduces the first OpenPower Power9 BMC system, Romulus. Romulus is
based on the ast2500 SoC from Aspeed.
These commits also add newly upstreamed drivers to the Palmetto BMC and ast2500
eval board. We now have working network, ipmi bt, gpio and pinmux on all platforms.
* tag 'aspeed-4.11-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed:
ARM: dts: aspeed: Add Romulus BMC platform
ARM: dts: aspeed: Add ftgmac100 to g4 and g5 platforms
ARM: dts: aspeed: Correct palmetto device tree
ARM: dts: aspeed: Reserve framebuffer memory
ARM: dts: aspeed-g5: Add gpio controller to devicetree
ARM: dts: aspeed-g5: Add syscon and pin controller nodes
ARM: dts: aspeed-g5: Add LPC Controller node
ARM: dts: aspeed-g5: Add SoC Display Controller node
ARM: dts: aspeed-g4: Add gpio controller to devicetree
ARM: dts: aspeed-g4: Add syscon and pin controller nodes
Signed-off-by: Olof Johansson <olof@lixom.net>
- Add support for the ethernet switch on the Turris Omnia board
- Clean up and improvement for ClearFog boards
- Correct license text which was mangled when switching to dual license
-----BEGIN PGP SIGNATURE-----
iIEEABECAEEWIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWHkIIiMcZ3JlZ29yeS5j
bGVtZW50QGZyZWUtZWxlY3Ryb25zLmNvbQAKCRALBhiOFHI71WLCAKCGlNI2NPYq
/54Ln14bXataT3uAVgCdF5DLhRKp24ifepK6hDF39drKdWk=
=zoka
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt-4.11-1' of git://git.infradead.org/linux-mvebu into next/dt
mvebu dt for 4.11 (part 1)
- Add support for the ethernet switch on the Turris Omnia board
- Clean up and improvement for ClearFog boards
- Correct license text which was mangled when switching to dual license
* tag 'mvebu-dt-4.11-1' of git://git.infradead.org/linux-mvebu:
ARM: dts: turris-omnia: add support for ethernet switch
ARM: dts: armada388-clearfog: move uart nodes
ARM: dts: armada388-clearfog: move ethernet related nodes
ARM: dts: armada388-clearfog: move I2C nodes
ARM: dts: armada388-clearfog: move device specific pinctrl nodes
ARM: dts: armada388-clearfog: add pro model DTS file
ARM: dts: armada388-clearfog: add base model DTS file
ARM: dts: armada388-clearfog: move rear button
ARM: dts: armada388-clearfog: move SPI CS1
ARM: dts: armada388-clearfog: move second PCIe port
ARM: dts: armada388-clearfog: move DSA switch
ARM: dts: armada388-clearfog: split clearfog DTS file
ARM: dts: armada388-clearfog: move sdhci pinctrl node to microsom
ARM: dts: armada388-clearfog: move SPI flash into microsom
ARM: dts: armada388-clearfog: fix SPI flash #size-cells
ARM: dts: mvebu: Correct license text
Signed-off-by: Olof Johansson <olof@lixom.net>
1. Fixes for initial audio clocks configuration.
2. Enable sound on Odroid-X board.
3. Enable DMA for UART modules on Exynos5 SoCs.
4. Add CPU OPPs for Exynos4412 Prime (newer version of Exynos4412). This pulls
necessary change in the clocks.
5. Remove Exynos4212. We do not have any mainline boards with it. This will
simplify few bits later.
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJYeOsYAAoJEME3ZuaGi4PXuSMP/RFjn4liQ4qG/uE5j6+7HDSF
PC/1yBYyo0xzg8oaEJVz7Ay6ydqNqBAMhPfdJzWk1lzN+zQc2MwLynH1fNNJTWSY
6YtBhNzx5sgs1IRtqG8RvSpj67OlE6i98YJL64j4VjNdhcTrRBPSbm2TDeu82uzh
VY3RDsXkTeWNwiHRuDXRqZ3VLfZ/xGjuT7Ym0cEMjPeuETNHs6jYVfi5e1d1c631
Ln2MJj0dpLbf+eUqkvLjv45LIHr6DmQHhuHlfwNu9iY6EmDtS+m9BKBxMvGrWzSp
5fy/3MpQo6+DD0GocnbsQpqylKmI5sXX9ly0A4F2ZWMRkoULVHv/5UrP7V9puHyO
Rd6i9RrpPDzAm81KRorFbwJnl2uJlomR5yWSISWQ51p6HXP1mFi+78YacUgCgNM0
TDCXhuGp1ZbJmBtq1Eae3C6Ku9GEtq9WLNkphWzeqUc4miZRwQ9NGBtZhbbgoFOl
XvANJAfVcS6PDJyadKlD/bktz8cyNO+H3jMPzlFRqaGW/E0yX8BbG01kjJhmR2dZ
qAMJtWT55PPNBss/ml67qezEYBXw9xwyo9d0vPnTWE0XvCL/p++Q+BEojKB8zYuE
4NJrj01CjZmpa8Ej3zpi6MLbVaKto5TjNTe981jzyAUpGlt2fiAuGmn85lTP2a0c
4LKCFLMZ8HGDMRL1WTkl
=w/rg
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt
Samsung DeviceTree update for v4.11:
1. Fixes for initial audio clocks configuration.
2. Enable sound on Odroid-X board.
3. Enable DMA for UART modules on Exynos5 SoCs.
4. Add CPU OPPs for Exynos4412 Prime (newer version of Exynos4412). This pulls
necessary change in the clocks.
5. Remove Exynos4212. We do not have any mainline boards with it. This will
simplify few bits later.
* tag 'samsung-dt-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: remove Exynos4212 support (dead code)
ARM: dts: exynos: Add CPU OPPs for Exynos4412 Prime
clk: samsung: Add CPU clk configuration data for Exynos4412 Prime
ARM: dts: exynos: Enable DMA support for UART modules on Exynos5 SoCs
ARM: dts: exynos: Cleanup Odroid-X2 and enable sound on Odroid-X
ARM: dts: exynos: Fix initial audio clocks configuration on Exynos4 boards
ARM: dts: exynos: Correct clocks for Exynos4 I2S module
Signed-off-by: Olof Johansson <olof@lixom.net>
- Adds FPGA manager bits
- Enable I2C on Cyclone5 and Arria5 devkits
- Adds LED support on C5/A5 devkits
- Enables CAN on C5 devkit
- Enables watchdog
- Add NAND on Arria10
- Add the LTC2977 Power Monitor on Arria10 devkit
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYdlGPAAoJEBmUBAuBoyj0lw0QAIbaW9pIooV/DLFcI0K4wjsq
CJhbH1f0f9KGhpKqCdr2J5zToHibb06O6xT+h6799oi1MxnbfGPLD/zjcJ3Jr+kw
2CQc8B9j5zSAeg4DpAMpPPzsUk2XJpIz2rNzI55KRuUYllvFlvQ9mAc1sfbVcPub
TBp653uFV3+XKTZz+OZ3zO86bcWGEh8bB0YVqzVArlnoA9PhiWQhV0Ee/cau2VO3
J2GgUmprLVWgOG86OI+WWqEI2Ywc8EAkOXo3DslqoA1zLA4C8ckph3hKiEhjEn+L
Bc4EagXbdalXtbqEIFYcKksW8ZrLX2rY9volGUEHFRBYPUmVH32bl5Q+cr/3gBPe
7TtEh6j9uiSvYtCkNalnVfBBGxLr5lalRDkBXiabFhBv2r3iFdpmfmvGhuNptjls
QNLqEkVVV3bRxSlmRlr7Jb5PdjlOt8lcqyF2jYxU4JlAD6zotEW3dVWLBG+i6awD
n3HUC3FH9DMCxsM5NxhngUYLI8ko7RNpISArApxdEplzxVO1B/+07kzi/JyEMmyI
4DVKUrivpSXUpwsK8GDvmWjXogK1q/ZCzX28zpwRS23a9syJ1f3qm/golyDzQPR4
97RBJWmBqt3Mb2/J8ZO0ybbBkUGFpC2B6HVs+88mHUWJrWU8CV1N7zVrZ7/UVZAf
8zMFRqb/m90Pc7jlNkZB
=hbau
-----END PGP SIGNATURE-----
Merge tag 'socfpga_dts_for_v4.11_part_1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt
SoCFPGA DTS updates for v4.11, part 1
- Adds FPGA manager bits
- Enable I2C on Cyclone5 and Arria5 devkits
- Adds LED support on C5/A5 devkits
- Enables CAN on C5 devkit
- Enables watchdog
- Add NAND on Arria10
- Add the LTC2977 Power Monitor on Arria10 devkit
* tag 'socfpga_dts_for_v4.11_part_1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: dts: socfpga: add missing compatible string for SDRAM controller
ARM: dts: socfpga: add fpga region support on Arria10
ARM: dts: socfpga: add base fpga region and fpga bridges
ARM: dts: socfpga: fpga manager data is 32 bits
ARM: dts: socfpga: Add NAND device tree for Arria10
ARM: dts: socfpga: add fpga-manager node for Arria10
ARM: dts: socfpga: add the LTC2977 power monitor on Arria10 devkit
ARM: dts: socfpga: enable watchdog timer on Arria5 and Arria10
ARM: dts: socfpga: enable CAN on Cyclone5 devkit
ARM: dts: socfpga: Add Rohm DH2228FV DAC
ARM: dts: socfpga: set desired i2c clock on Cyclone5 and Arria5 devkits
ARM: dts: socfpga: enable GPIO and LEDs for Cyclone5 and Arria5 devkits
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch enables RTC on stm32f429-disco with LSI as clock source because
X2 crystal for LSE is not fitted by default.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
This patch set HSE_RTC clock frequency to 1 MHz, as the clock supplied to
the RTC must be 1 MHz.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Rename dmu_reserved to delta_reserved
Rename st231_dmu to st231_delta
Update the delta_reserved memory region start address
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
The clock parent was lower than child clock which is not correct.
In some use case, it leads to division by zero.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
As sti-hda is only available on STiH410-B2120,
disable it in STiH410.dtsi and enable it at board level.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
There are no Exynos4212 based boards in mainline, so there is no need to
keep additional files for SoCs, which are never used. This patch removes
support for Exynos4212 SoCs and moves previously shared Exynos4412
definitions to a single file to simplify future maintenance.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
The Axentia TSE-850 is a SAMA5D3-based device designed to generate
FM subcarrier signals.
Signed-off-by: Peter Rosin <peda@axentia.se>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The sama5d36ek CMP board is the variant of sama5d3xek board.
It is equipped with the low-power DDR2 SDRAM, PMIC ACT8865 and
some power rail. Its main purpose is used to measure the power
consumption.
The difference of the sama5d36ek CMP dts from sama5d36ek dts is
listed as below.
1. The USB host nodes are removed, that is, the USB host is disabled.
2. The gpio_keys node is added to wake up from the sleep.
3. The LCD isn't supported due to the pins for LCD are conflicted
with gpio_keys.
4. The adc0 node support the pinctrl sleep state to fix the over
consumption on VDDANA.
As said in errata, "When the USB host ports are used in high speed
mode (EHCI), it is not possible to suspend the ports if no device is
attached on each port. This leads to increased power consumption even
if the system is in a low power mode." That is why the the USB host
is disabled.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The sama5d2 SoC has Synchronous Serial Controller which provides
synchronous communication link with external devices.
It's generally used in audio and telecom applications such as
I2S, Short Frame Sync, Long Frame Sync.
Signed-off-by: Alex Gershgorin <alex.gershgorin@qcore.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Use DMA for UART3 as we have enough channels and to show how to
specify DMA use with serial nodes.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Now that DMA1 is defined, use it to distribute channel usage among the two
controllers.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The sama5d2 SoC has a second DMA controller and can be used just like DMA0.
By default both DMA controllers are configured as "Secure" in
MATRIX_SPSELR so we can use whichever we want in a "single Secure World"
configuration.
Surprisingly the DMA1 has a lower address than DMA0. To avoid confusion
place it after DMA0 node anyway.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Enable UART1 and use DMA configuration with it.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Some peripherals are "Programmable Secure" but left as "Secure" by default.
If tried to be connected to Non-Secure DMA controller, the possibility to
leak secure data is prevented so using these peripherals with DMA1 is not
possible with this default configuration (MATRIX_SPSELR registers setup by
bootloader).
Move them to DMA0 which is an "Always-Secure" DMA controller.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The new size (0x100) also matches the size given in sama5d3.dtsi
Documentation reference: section 43.6 "Universal Asynchronous
Receiver Transmitter (UART) User Interface", table 43-4 "Register
Mapping" in [1].
[1] Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Palmettos have 512MB of memory as opposed to the previously thought
256MB. Update the device trees accordingly.
We run the uart at 115200.
Signed-off-by: Cyril Bur <cyrilbur@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
When used as a BMC, the host expects to be able to use 16MB of
framebuffer memory at the top of RAM.
Signed-off-by: Cyril Bur <cyrilbur@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
The pin controller's child nodes expose the functions currently
implemented in the g5 pin controller driver.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
The pin controller's child nodes expose the functions currently
implemented in the the g4 pin controller driver.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
This patch include auxiliary clock definition (clocks which are not derived
from system clock.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
This patch adds an external I2S clock in the DT.
The I2S clock could be derived from an external I2S clock or by I2S pll.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Enable analog to digital converter on stm32f429i-eval board.
It has on-board potentimeter wired to ADC3 in8 analog pin and
uses fixed regulator to provide reference voltage.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
This patch adds USART3 pin configuration on PB10/PA11 pins
for STM32F469I-DISCO board.
Signed-off-by: Bruno Herrera <bruherrera@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
This patch fix memory size to support 16MB of external SDRAM.
Signed-off-by: Bruno Herrera <bruherrera@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
