- It contains a series from Schrempf Frieder that cleans up FSL QSPI
device tree nodes. The current device trees are broken because they
use an inconsistent scheme for assigning the reg properties. It
becomes a problem with ongoing QSPI driver under SPI framework. So
the cleanup is a preparation for new driver landing in the next
cycle.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJcFg+pAAoJEFBXWFqHsHzOC3UH/RsA0ysBXsaUF9aNpfmwFpKP
bApnoyo+MhLZSvFqD8eU1K0BhXFOkOmMXMbTle0b3uF7qaknnXEoWTCNz+hJGDsz
fFeOqz7xjyG8Q4U8PT4ImG0OPuFNNGBs1byJKZygxJp/xBlAGMKDp/rRKbM4c8+8
WzoKcWcLqFe+Vau0vuesjcT7J/B3nWvzOWsWX5MHOp10rEWyv9Y4Ct3cAzSMVhAM
1eLQpYegOvUckX0if7BZpj7vSIhDNp/urx6U7D5KGAf9iHK50euMX55LhveiSM8w
CdnnZn2MUXEt2A81Aqb97IOhMsEra47Ffomr1nIV2OGbmDY27HrlUrNSEKNER28=
=I3dR
-----END PGP SIGNATURE-----
Merge tag 'imx-qspi-dt-clean' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt
Freescale QSPI device tree cleanup for 4.21:
- It contains a series from Schrempf Frieder that cleans up FSL QSPI
device tree nodes. The current device trees are broken because they
use an inconsistent scheme for assigning the reg properties. It
becomes a problem with ongoing QSPI driver under SPI framework. So
the cleanup is a preparation for new driver landing in the next
cycle.
* tag 'imx-qspi-dt-clean' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: Add spi-[tx/rx]-bus-width for the FSL QSPI controller
arm64: dts: Remove unused properties from FSL QSPI driver nodes
ARM: dts: Add spi-[tx/rx]-bus-width for the FSL QSPI controller
ARM: dts: imx6sx-sdb: Fix the reg properties for the FSL QSPI nodes
ARM: dts: Remove unused properties from FSL QSPI driver nodes
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
ACPI and PCI are no longer coupled to each other. Specify requirements
for both when pulling in code.
Signed-off-by: Sinan Kaya <okaya@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
- Large PUD support for HugeTLB
- Single-stepping fixes
- Improved tracing
- Various timer and vgic fixups
-----BEGIN PGP SIGNATURE-----
iQJJBAABCgAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAlwahf0VHG1hcmMuenlu
Z2llckBhcm0uY29tAAoJECPQ0LrRPXpDl3MQAKTJ2+vA1vCln2OiKJLZ0TzsSVFB
EXiJfQ6QghD+BHeXw/XU/4X8sD8NjzIP833RvmAgQ/Gm2BpEY/Fj4CmTKaoA5wfJ
UMEvLUFGWb19d0hbf7AllSXg3FvkpAMVof7zfKIyI7tHem6sWHmyXDiXzEfpX2un
bS3x8OBbdVhHcjCvgc1U6Jbii0KUR8Ac5PJBJny1PWkKHFe8NYf/cX+Ii//FMdCm
7zihQAFOpksVOI7y9wYwpmMeI52vDwesergqBBJXkklsAFAda56a2NuoG6oim3BJ
FH/cavGGfrwcdN6Dh5tkvubfxIL5sKF57ZW0Jpy7MPK7u2Zzr7ZvRBHdvYqE+kp3
+jieKr6t1MVnpYfOOZRZgnTqio3Cp++2GzZr283IH0WjDTnN7hhEWbU6/o8DHSge
H/nDyxSycbUZtrGVAOm6oPoy4hNElvW8S71+rLqXVc46aKs3YheNg5MqkLawRA0q
5U9Lw5Um/IvcjfM8DESpmYnugZV8FkzEcMZ3SQjQRYafXdjq2V2NjSMtl2+dyeDh
KthCujhK0F1KBgw7FocNOwh2M7q6mIjw93HrX30CcT6cu2q+0apty+tjXZapP+dc
l7Tad8iFGzAGvW0i3yNWADXhMGk721YrGmptWZh4M9B8CZr2pPzuB4nUPDMeyMYl
XlgIgVGv24MKDjnW
=SiUI
-----END PGP SIGNATURE-----
Merge tag 'kvmarm-for-v4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD
KVM/arm updates for 4.21
- Large PUD support for HugeTLB
- Single-stepping fixes
- Improved tracing
- Various timer and vgic fixups
32 and 64bit use different symbols to identify the traps.
32bit has a fine grained approach (prefetch abort, data abort and HVC),
while 64bit is pretty happy with just "trap".
This has been fine so far, except that we now need to decode some
of that in tracepoints that are common to both architectures.
Introduce ARM_EXCEPTION_IS_TRAP which abstracts the trap symbols
and make the tracepoint use it.
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Although bit 31 of VTCR_EL2 is RES1, we inadvertently end up setting all
of the upper 32 bits to 1 as well because we define VTCR_EL2_RES1 as
signed, which is sign-extended when assigning to kvm->arch.vtcr.
Lucky for us, the architecture currently treats these upper bits as RES0
so, whilst we've been naughty, we haven't set fire to anything yet.
Cc: <stable@vger.kernel.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
We're pretty blind when it comes to system register tracing,
and rely on the ESR value displayed by kvm_handle_sys, which
isn't much.
Instead, let's add an actual name to the sysreg entries, so that
we can finally print it as we're about to perform the access
itself.
The new tracepoint is conveniently called kvm_sys_access.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
vcpu_read_sys_reg should not be modifying the VCPU structure.
Eventually, to handle EL2 sysregs for nested virtualization, we will
call vcpu_read_sys_reg from places that have a const vcpu pointer, which
will complain about the lack of the const modifier on the read path.
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
The kvm_exit tracepoint strangely always reported exits as being IRQs.
This seems to be because either the __print_symbolic or the tracepoint
macros use a variable named idx.
Take this chance to update the fields in the tracepoint to reflect the
concepts in the arm64 architecture that we pass to the tracepoint and
move the exception type table to the same location and header files as
the exits code.
We also clear out the exception code to 0 for IRQ exits (which
translates to UNKNOWN in text) to make it slighyly less confusing to
parse the trace output.
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Otherwise the direct mapping won't work at all given that a NULL
dev->dma_ops causes a fallback. Note that we already explicitly set
dev->dma_ops to dma_dummy_ops for dma-incapable devices, so this
fallback should not be needed anyway.
Fixes: 356da6d0cd ("dma-mapping: bypass indirect calls for dma-direct")
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
The AP6212 is based on the Broadcom BCM43430 or BCM43438. The WiFi side
identifies as BCM43430, while the Bluetooth side identifies as BCM43438.
The Bluetooth side is connected to UART1 in a 4 wire configuration. Same
as the WiFi side, due to being the same chip and package, DLDO2 provides
overall power via VBAT, and DLDO4 provides I/O power via VDDIO. The RTC
clock output provides the LPO low power clock at 32.768 kHz.
This patch enables Bluetooth on this board, and also adds the missing
LPO clock on the WiFi side. There is also a PCM connection for Bluetooth,
but this is not covered here.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
In attempting to re-construct the logic for our stage 2 page table
layout I found the reasoning in the comment explaining how we calculate
the number of levels used for stage 2 page tables a bit backwards.
This commit attempts to clarify the comment, to make it slightly easier
to read without having the Arm ARM open on the right page.
While we're at it, fixup a typo in a comment that was recently changed.
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
KVM only supports PMD hugepages at stage 2. Now that the various page
handling routines are updated, extend the stage 2 fault handling to
map in PUD hugepages.
Addition of PUD hugepage support enables additional page sizes (e.g.,
1G with 4K granule) which can be useful on cores that support mapping
larger block sizes in the TLB entries.
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
[ Replace BUG() => WARN_ON(1) for arm32 PUD helpers ]
Signed-off-by: Suzuki Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
In preparation for creating larger hugepages at Stage 2, add support
to the age handling notifiers for PUD hugepages when encountered.
Provide trivial helpers for arm32 to allow sharing code.
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
[ Replaced BUG() => WARN_ON(1) for arm32 PUD helpers ]
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
In preparation for creating larger hugepages at Stage 2, extend the
access fault handling at Stage 2 to support PUD hugepages when
encountered.
Provide trivial helpers for arm32 to allow sharing of code.
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
[ Replaced BUG() => WARN_ON(1) in PUD helpers ]
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
In preparation for creating PUD hugepages at stage 2, add support for
detecting execute permissions on PUD page table entries. Faults due to
lack of execute permissions on page table entries is used to perform
i-cache invalidation on first execute.
Provide trivial implementations of arm32 helpers to allow sharing of
code.
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
[ Replaced BUG() => WARN_ON(1) in arm32 PUD helpers ]
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
In preparation for creating PUD hugepages at stage 2, add support for
write protecting PUD hugepages when they are encountered. Write
protecting guest tables is used to track dirty pages when migrating
VMs.
Also, provide trivial implementations of required kvm_s2pud_* helpers
to allow sharing of code with arm32.
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
[ Replaced BUG() => WARN_ON() in arm32 pud helpers ]
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Introduce helpers to abstract architectural handling of the conversion
of pfn to page table entries and marking a PMD page table entry as a
block entry.
The helpers are introduced in preparation for supporting PUD hugepages
at stage 2 - which are supported on arm64 but do not exist on arm.
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
When KVM traps an unhandled sysreg/coproc access from a guest, it logs
the guest PC. To aid debugging, it would be helpful to know which
exception level the trap came from, along with other PSTATE/CPSR bits,
so let's log the PSTATE/CPSR too.
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
When we emulate a guest instruction, we don't advance the hardware
singlestep state machine, and thus the guest will receive a software
step exception after a next instruction which is not emulated by the
host.
We bodge around this in an ad-hoc fashion. Sometimes we explicitly check
whether userspace requested a single step, and fake a debug exception
from within the kernel. Other times, we advance the HW singlestep state
rely on the HW to generate the exception for us. Thus, the observed step
behaviour differs for host and guest.
Let's make this simpler and consistent by always advancing the HW
singlestep state machine when we skip an instruction. Thus we can rely
on the hardware to generate the singlestep exception for us, and never
need to explicitly check for an active-pending step, nor do we need to
fake a debug exception from the guest.
Cc: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
The "num-lanes" property for PCIe is not used, remove it.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
TM2(e) boards have a Broadcom Bluetooth chip connected to 3rd UART port.
Add a device tree node describing it and its resources (control GPIO lines
and clock).
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
The external nWDOG signal connects to the EVK board reset circuit.
Tested on the i.MX8MQ EVK rev B3.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This is the evaluation kit board for the i.MX8M. The current level of
support yields a working console and is able to boot userspace from
SD card or Network.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> (v1)
Reviewed-by: Rob Herring <robh@kernel.org> (v3)
Tested-by: Tested-by: Baruch Siach <baruch@tkos.co.il> (v1)
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This adds the basic DTS for the i.MX8MQ.
For now only the following peripherals are supported:
- IOMUXC (pin controller)
- CCM (clock controller)
- GPIO
- UART
- uSDHC (SD/eMMC controller)
- FEC (ethernet controller)
- i2c
This is enough to get a very basic board support up and running.
One known limitation is that the driver for the GPC interrupt
controller is still missing, rendering the CPU sleep states unusable
as there is nothing waking them up anymore.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Dong Aisheng <Aisheng.dong@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add basic Kconfig symbols to make the MXC architecture available
in the ARM64 world.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
We will move the FSL QSPI driver to the SPI framework soon. To
prepare and to make sure the full buswidth is used (as it is with
the current driver), let's add the right properties.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The properties 'num-cs' and 'bus-num' were never read by the driver
and can be removed.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This define is used by arm64 to calculate the size of the vmemmap
region. It is defined as the log2 of the upper bound on the size of a
struct page.
We move it into mm_types.h so it can be defined properly instead of set
and checked with a build bug. This also allows us to use the same
define for riscv.
Link: http://lkml.kernel.org/r/20181107205433.3875-2-logang@deltatee.com
Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Andrew Morton <akpm@linux-foundation.org>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Christoph Hellwig <hch@lst.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
non-cacheable alias in the FORCE_CONTIGUOUS case
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEE5RElWfyWxS+3PLO2a9axLQDIXvEFAlwT5e4ACgkQa9axLQDI
XvGYhg//bU9qdZ0xDxVIiuA6/H/ptiFYDFd15vAKBXF+PJkREQSqFqZc5gsZrEa1
y3e1cJ8zcP9wSsuYbUFuN3LWaIPRqrUdNrD6d+IfGgx8o+WbdexCLhus0NyAwQUQ
CqR/CVOBGfpdOXqKKoryXGP4yPnBcrxjhXB6tqlOahoQj3ZF1RxO4uqOw+w6bUn8
gXd00DBOqomsqRimKFksXrslO5aAhw6opkF0tsHSSh0v1V3M+GRAKMQ7O7s/Khf/
yvJ75r0IVwP5/dE2FqxXJAjyPv8sXZudIR+jSxAS40v2azultyRJEjaOduB+qLHw
PqqcmXMaQhZ54hq1YnVC67h9WpvfVsUfE/TrwgRopcNikbhGQsJ7AlYUmQuxiIej
5bKcy3YC4i+/xLOCoGjmxps3Q3tUsfr+aGj76n+yL1xLwhZK3VjKqbjnXl/OV7kf
N2SAtPJUeVTBkCbLCwqG5k4cVNoS7Ncu/Nk3r1fuArRBc4OH4B4kQHVauHnZ51hA
nzbnBjyLfee37E9b7IwKZGXxedRYtEjRM1NpdFg4yYuc2k3oc9J+6LPVnliA8dc7
CnhxdlxxBSAzP5BFSPN5kytSNXZXGjBWfrMbDFw3GmMihQXOT8Oskq80sxYjFOqO
0u/kA4E9nySAUVA7QxKY76Ez1u2lf1BxzvmYdgZegplwvTxewPg=
=FMny
-----END PGP SIGNATURE-----
Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 fix from Catalin Marinas:
"Invalidate the caches before clearing the DMA buffer via the
non-cacheable alias in the FORCE_CONTIGUOUS case"
* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: dma-mapping: Fix FORCE_CONTIGUOUS buffer clearing
When debug with kaslr, it is sometimes necessary to have PHYS_OFFSET to
perform linear virtual address to physical address translation.
Sometimes we're debugging with only few information such as a kernel log
and a symbol file, print PHYS_OFFSET in dump_kernel_offset() for that case.
Tested by:
echo c > /proc/sysrq-trigger
[ 11.996161] SMP: stopping secondary CPUs
[ 11.996732] Kernel Offset: 0x2522200000 from 0xffffff8008000000
[ 11.996881] PHYS_OFFSET: 0xffffffeb40000000
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Miles Chen <miles.chen@mediatek.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Enable McSPI0 of main domain and add DT node for the SPI NOR flash
connected to CS0.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
There are 3 instances of McSPI in MCU domain and 4 instances in Main domain.
Add DT nodes for all McSPI instances present on AM654 SoC.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Populate power-domain property for UART nodes, this is required for
Linux to enable UART clocks via PM calls. Without this UART instances
not initialized by bootloader (like main_uart1) fails to work in Linux.
Also, drop current-speed property from main_uart1 and main_uart2 nodes
as these UARTs are not initialized before Linux boots up and current
speed is unknown.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add pinmux for main uart0 that is serves as console on AM654 EVM
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add pinctrl regions for the main and wkup mmr.
The range for main pinctrl region contains a gap
at offset 0x2e4, and because of this, the pinctrl
range is split into two sections.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Avoid expensive indirect calls in the fast path DMA mapping
operations by directly calling the dma_direct_* ops if we are using
the directly mapped DMA operations.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Jesper Dangaard Brouer <brouer@redhat.com>
Tested-by: Jesper Dangaard Brouer <brouer@redhat.com>
Tested-by: Tony Luck <tony.luck@intel.com>
While the dma-direct code is (relatively) clean and simple we actually
have to use the swiotlb ops for the mapping on many architectures due
to devices with addressing limits. Instead of keeping two
implementations around this commit allows the dma-direct
implementation to call the swiotlb bounce buffering functions and
thus share the guts of the mapping implementation. This also
simplified the dma-mapping setup on a few architectures where we
don't have to differenciate which implementation to use.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Jesper Dangaard Brouer <brouer@redhat.com>
Tested-by: Jesper Dangaard Brouer <brouer@redhat.com>
Tested-by: Tony Luck <tony.luck@intel.com>
The dummy DMA ops are currently used by arm64 for any device which has
an invalid ACPI description and is thus barred from using DMA due to not
knowing whether is is cache-coherent or not. Factor these out into
general dma-mapping code so that they can be referenced from other
common code paths. In the process, we can prune all the optional
callbacks which just do the same thing as the default behaviour, and
fill in .map_resource for completeness.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
[hch: moved to a separate source file]
Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: Jesper Dangaard Brouer <brouer@redhat.com>
Tested-by: Jesper Dangaard Brouer <brouer@redhat.com>
Tested-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
All architectures except for sparc64 use the dma-direct code in some
form, and even for sparc64 we had the discussion of a direct mapping
mode a while ago. In preparation for directly calling the direct
mapping code don't bother having it optionally but always build the
code in. This is a minor hardship for some powerpc and arm configs
that don't pull it in yet (although they should in a relase ot two),
and sparc64 which currently doesn't need it at all, but it will
reduce the ifdef mess we'd otherwise need significantly.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Jesper Dangaard Brouer <brouer@redhat.com>
Tested-by: Jesper Dangaard Brouer <brouer@redhat.com>
Tested-by: Tony Luck <tony.luck@intel.com>
Using shifts directly is error-prone and can cause inadvertent sign
extensions or build problems with older versions of binutils.
Consistent use of the _BITUL() macro makes these problems disappear.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Open-coding the pointer-auth HWCAPs is a mess and can be avoided by
reusing the multi-cap logic from the CPU errata framework.
Move the multi_entry_cap_matches code to cpufeature.h and reuse it for
the pointer auth HWCAPs.
Reviewed-by: Suzuki Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
We can easily avoid defining the two meta-capabilities for the address
and generic keys, so remove them and instead just check both of the
architected and impdef capabilities when determining the level of system
support.
Reviewed-by: Suzuki Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
We don't need to get at the per-thread keys from assembly at all, so
they can live alongside the rest of the per-thread register state in
thread_struct instead of thread_info.
This will also allow straighforward whitelisting of the keys for
hardened usercopy should we expose them via a ptrace request later on.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Now that all the necessary bits are in place for userspace, add the
necessary Kconfig logic to allow this to be enabled.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Add an arm64-specific prctl to allow a thread to reinitialize its
pointer authentication keys to random values. This can be useful when
exec() is not used for starting new processes, to ensure that different
processes still have different keys.
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
When the kernel is unwinding userspace callchains, we can't expect that
the userspace consumer of these callchains has the data necessary to
strip the PAC from the stored LR.
This patch has the kernel strip the PAC from user stackframes when the
in-kernel unwinder is used. This only affects the LR value, and not the
FP.
This only affects the in-kernel unwinder. When userspace performs
unwinding, it is up to userspace to strip PACs as necessary (which can
be determined from DWARF information).
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
When pointer authentication is in use, data/instruction pointers have a
number of PAC bits inserted into them. The number and position of these
bits depends on the configured TCR_ELx.TxSZ and whether tagging is
enabled. ARMv8.3 allows tagging to differ for instruction and data
pointers.
For userspace debuggers to unwind the stack and/or to follow pointer
chains, they need to be able to remove the PAC bits before attempting to
use a pointer.
This patch adds a new structure with masks describing the location of
the PAC bits in userspace instruction and data pointers (i.e. those
addressable via TTBR0), which userspace can query via PTRACE_GETREGSET.
By clearing these bits from pointers (and replacing them with the value
of bit 55), userspace can acquire the PAC-less versions.
This new regset is exposed when the kernel is built with (user) pointer
authentication support, and the address authentication feature is
enabled. Otherwise, the regset is hidden.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
[will: Fix to use vabits_user instead of VA_BITS and rename macro]
Signed-off-by: Will Deacon <will.deacon@arm.com>
This patch adds basic support for pointer authentication, allowing
userspace to make use of APIAKey, APIBKey, APDAKey, APDBKey, and
APGAKey. The kernel maintains key values for each process (shared by all
threads within), which are initialised to random values at exec() time.
The ID_AA64ISAR1_EL1.{APA,API,GPA,GPI} fields are exposed to userspace,
to describe that pointer authentication instructions are available and
that the kernel is managing the keys. Two new hwcaps are added for the
same reason: PACA (for address authentication) and PACG (for generic
authentication).
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Tested-by: Adam Wallis <awallis@codeaurora.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
[will: Fix sizeof() usage and unroll address key initialisation]
Signed-off-by: Will Deacon <will.deacon@arm.com>
So that we can dynamically handle the presence of pointer authentication
functionality, wire up probing code in cpufeature.c.
From ARMv8.3 onwards, ID_AA64ISAR1 is no longer entirely RES0, and now
has four fields describing the presence of pointer authentication
functionality:
* APA - address authentication present, using an architected algorithm
* API - address authentication present, using an IMP DEF algorithm
* GPA - generic authentication present, using an architected algorithm
* GPI - generic authentication present, using an IMP DEF algorithm
This patch checks for both address and generic authentication,
separately. It is assumed that if all CPUs support an IMP DEF algorithm,
the same algorithm is used across all CPUs.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
To allow EL0 (and/or EL1) to use pointer authentication functionality,
we must ensure that pointer authentication instructions and accesses to
pointer authentication keys are not trapped to EL2.
This patch ensures that HCR_EL2 is configured appropriately when the
kernel is booted at EL2. For non-VHE kernels we set HCR_EL2.{API,APK},
ensuring that EL1 can access keys and permit EL0 use of instructions.
For VHE kernels host EL0 (TGE && E2H) is unaffected by these settings,
and it doesn't matter how we configure HCR_EL2.{API,APK}, so we don't
bother setting them.
This does not enable support for KVM guests, since KVM manages HCR_EL2
itself when running VMs.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: kvmarm@lists.cs.columbia.edu
Signed-off-by: Will Deacon <will.deacon@arm.com>
In subsequent patches we're going to expose ptrauth to the host kernel
and userspace, but things are a bit trickier for guest kernels. For the
time being, let's hide ptrauth from KVM guests.
Regardless of how well-behaved the guest kernel is, guest userspace
could attempt to use ptrauth instructions, triggering a trap to EL2,
resulting in noise from kvm_handle_unknown_ec(). So let's write up a
handler for the PAC trap, which silently injects an UNDEF into the
guest, as if the feature were really missing.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: kvmarm@lists.cs.columbia.edu
Signed-off-by: Will Deacon <will.deacon@arm.com>
In KVM we define the configuration of HCR_EL2 for a VHE HOST in
HCR_HOST_VHE_FLAGS, but we don't have a similar definition for the
non-VHE host flags, and open-code HCR_RW. Further, in head.S we
open-code the flags for VHE and non-VHE configurations.
In future, we're going to want to configure more flags for the host, so
lets add a HCR_HOST_NVHE_FLAGS defintion, and consistently use both
HCR_HOST_VHE_FLAGS and HCR_HOST_NVHE_FLAGS in the kvm code and head.S.
We now use mov_q to generate the HCR_EL2 value, as we use when
configuring other registers in head.S.
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: kvmarm@lists.cs.columbia.edu
Signed-off-by: Will Deacon <will.deacon@arm.com>
The ARMv8.3 pointer authentication extension adds:
* New fields in ID_AA64ISAR1 to report the presence of pointer
authentication functionality.
* New control bits in SCTLR_ELx to enable this functionality.
* New system registers to hold the keys necessary for this
functionality.
* A new ESR_ELx.EC code used when the new instructions are affected by
configurable traps
This patch adds the relevant definitions to <asm/sysreg.h> and
<asm/esr.h> for these, to be used by subsequent patches.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
To make it clear which exceptions can't be taken to EL1 or EL2, add
comments next to the ESR_ELx_EC_* macro definitions.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Although the upper 32 bits of the PMEVTYPER<n>_EL0 registers are RES0,
we should treat the EXCLUDE_EL* bit definitions as unsigned so that we
avoid accidentally sign-extending the privilege filtering bit (bit 31)
into the upper half of the register.
Signed-off-by: Will Deacon <will.deacon@arm.com>
While the CSV3 field of the ID_AA64_PFR0 CPU ID register can be checked
to see if a CPU is susceptible to Meltdown and therefore requires kpti
to be enabled, existing CPUs do not implement this field.
We therefore whitelist all unaffected Cortex-A CPUs that do not implement
the CSV3 field.
Signed-off-by: Will Deacon <will.deacon@arm.com>
To some degree, most known AArch64 micro-architectures appear to be
able to issue ALU instructions in parellel to SIMD instructions
without affecting the SIMD throughput. This means we can use the ALU
to process a fifth ChaCha block while the SIMD is processing four
blocks in parallel.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Update the 4-way NEON ChaCha routine so it can handle input of any
length >64 bytes in its entirety, rather than having to call into
the 1-way routine and/or memcpy()s via temp buffers to handle the
tail of a ChaCha invocation that is not a multiple of 256 bytes.
On inputs that are a multiple of 256 bytes (and thus in tcrypt
benchmarks), performance drops by around 1% on Cortex-A57, while
performance for inputs drawn randomly from the range [64, 1024)
increases by around 30%.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Now that the ARM64 NEON implementation of ChaCha20 and XChaCha20 has
been refactored to support varying the number of rounds, add support for
XChaCha12. This is identical to XChaCha20 except for the number of
rounds, which is 12 instead of 20. This can be used by Adiantum.
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
In preparation for adding XChaCha12 support, rename/refactor the ARM64
NEON implementation of ChaCha20 to support different numbers of rounds.
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add an XChaCha20 implementation that is hooked up to the ARM64 NEON
implementation of ChaCha20. This can be used by Adiantum.
A NEON implementation of single-block HChaCha20 is also added so that
XChaCha20 can use it rather than the generic implementation. This
required refactoring the ChaCha20 permutation into its own function.
Signed-off-by: Eric Biggers <ebiggers@google.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add an ARM64 NEON implementation of NHPoly1305, an ε-almost-∆-universal
hash function used in the Adiantum encryption mode. For now, only the
NH portion is actually NEON-accelerated; the Poly1305 part is less
performance-critical so is just implemented in C.
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> # big-endian
Signed-off-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Commit e8342cc795 ("enable CAAM crypto engine on QorIQ DPAA2 SoCs")
enabled CRYPTO_DEV_FSL_DPAA2_CAAM, which depends on FSL_MC_DPIO,
which is not set. Enable FSL_MC_BUS, and build FSL_MC_DPIO and
CRYPTO_DEV_FSL_DPAA2_CAAM as modules.
Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
[olof: refreshed due to churn]
Signed-off-by: Olof Johansson <olof@lixom.net>
Commit e78d57b2f8 ("pinctrl: mediatek: add pinctrl-moore that
implements the generic pinctrl dt-bindings") made PINCTRL_MT7622
depend on PINCTRL_MTK_MOORE, so it fell off in the refresh.
Add MTK_MOORE, which automatically enables MT7622.
Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
[olof: refresh and minor commit message reword]
Signed-off-by: Olof Johansson <olof@lixom.net>
Run the platform defconfig through kbuild, and handle the trivial case
where options merely move around.
Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
[olof: refreshed due to some recent churn]
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Olof Johansson <olof@lixom.net>
Our usual pull request with the changes shared between the H3 and H5 SoCs.
The major changes for this release are:
- Addition of the video engine for the H5
- H3 Camera support
- New board: Emlid Neutis N5, Mapleboard MP130
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXAqJJwAKCRDj7w1vZxhR
xTq4AP9SxrPeKDTBD4mKV+PVuJ2qq919M6o+mcxDkCecEMfbagD+JLkt2uGzdpb8
eC6CuieHvJq1y/akfDpRBf0ZZD0/bw0=
=yRd0
-----END PGP SIGNATURE-----
Merge tag 'sunxi-h3-h5-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt
Allwinner H3/H5 changes for 4.21
Our usual pull request with the changes shared between the H3 and H5 SoCs.
The major changes for this release are:
- Addition of the video engine for the H5
- H3 Camera support
- New board: Emlid Neutis N5, Mapleboard MP130
* tag 'sunxi-h3-h5-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: dts: allwinner: h5: Add Video Engine node
ARM/arm64: dts: allwinner: Move H3/H5 syscon label over to soc-specific nodes
arm64: dts: allwinner: h5: Add system-control node with SRAM C1
ARM: dts: sun8i: h3: Fix the system-control register range
ARM: dts: sun8i: Add the H3/H5 CSI controller
ARM: dts: sun8i-h3: Add dts for the Mapleboard MP130
arm64: dts: allwinner: new board - Emlid Neutis N5
dt-bindings: vendor-prefix: new vendor - Emlid
ARM: dts: sun8i-h3: add sy8106a to orange pi plus
Signed-off-by: Olof Johansson <olof@lixom.net>
* pm-rmobile driver
- Move to drivers/soc/renesas/
- Clean up struct rmobile_pm_domain
* Renesas SoC Kconfig Symbols
- Move symbols for ARM and SoCs to drivers/soc/renesas/
- Hide ARCH_RZN1 to improve consistency
* SH-Mobile AG5 (sh73a0) SoC: Remove obsolete inclusion of <asm/smp_twd.h>
* Restrict TWD and SCU to Renesas ARM based SoCs where they are present
* Enable GPIOLIB on Renesas arm64 based SoCs to allow GPIO driver selection
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAlwJl3UACgkQ189kaWo3
T77nHg/9HvFT/gkyNnqUmzPQB8l1WUu5J1b5uK6tuxQH4/6QADXvksw38o++Qamn
vqLiIO5bRoJN9tyLcARnt6/dukjHCyXN1DiPTpl3nW40psding6CPxGDRT/XGcsO
Q/Yn9u523Se7IddSX75O+Tfxq0XUOCHOqlMBPYBECBC5Kuo5iTUPx5Mh/Aiii7fL
u6kt8/H7hsVw+XK6ceBElwmqqXq7Jh0SuSG5e20DNFyFUGECYod9YZOc9yz3sT8L
bs6U9yM4Xfpe4e0lMwVNJAt2AOUPj/U0fKwqMJ2Fs9fjZVhN9jU5/+qDs8105Znh
P0fSCqmzc4qj+Jpvz3JunzIiobQHdZUUzav9VupuTjN3CyayisoM7lLfpdw9LSc3
AwBhMwhiqO4tbbKVxNiK9696pSOqRMXXmpU6pei8paEP0ORxrekZCr3KgprvMpv1
MGfXewhScjuIqfrOcpfAISTZRrm0N8ZpkuBfVhrC2pNAdjZyHRz4qQgciBk2Y1Cm
4FQdMA7k+sVj7b6fur97vTCvizDJpTsOrN+OL8/fFXzG2y6iZT9T2wPfytQ55FwA
b12HAEGKHEBiQWRmxy/gNm+VQRm1EBzEjv7nRMXCdf253ojcYjqCI4m9kpPRHUhG
mybv5TmmUiNdBSGtRtZwfZCtvdNXdCp39NwYeIwzYdTzzY4OrBs=
=i17r
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc-for-v4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Renesas ARM Based SoC Updates for v4.21
* pm-rmobile driver
- Move to drivers/soc/renesas/
- Clean up struct rmobile_pm_domain
* Renesas SoC Kconfig Symbols
- Move symbols for ARM and SoCs to drivers/soc/renesas/
- Hide ARCH_RZN1 to improve consistency
* SH-Mobile AG5 (sh73a0) SoC: Remove obsolete inclusion of <asm/smp_twd.h>
* Restrict TWD and SCU to Renesas ARM based SoCs where they are present
* Enable GPIOLIB on Renesas arm64 based SoCs to allow GPIO driver selection
* tag 'renesas-soc-for-v4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: R-Mobile: Move pm-rmobile to drivers/soc/renesas/
ARM: shmobile: R-Mobile: Clean up struct rmobile_pm_domain
ARM: shmobile: Move SoC Kconfig symbols to drivers/soc/renesas/
arm64: renesas: Move SoC Kconfig symbols to drivers/soc/renesas/
ARM: shmobile: Hide ARCH_RZN1 to improve consistency
ARM: shmobile: sh73a0: Remove obsolete inclusion of <asm/smp_twd.h>
ARM: shmobile: Restrict TWD support to SoCs that have it
ARM: shmobile: Restrict SCU support to SoCs that have it
arm64: renesas: Enable GPIOLIB to allow GPIO driver selection
Signed-off-by: Olof Johansson <olof@lixom.net>
A bunch of patches to improve the coverage of Allwinner drivers in the
arm64 defconfig, mostly targeted at adding display drivers support.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXAqBowAKCRDj7w1vZxhR
xVZMAQCfcR+ZJf0vqHJ2fR0nOroltxrs36wU/SutdePaHInQuAD/dfdXlVonEaGN
1VBKIGzl1Z9PNTsCGADLN0dQRLlX/Q4=
=Q2ck
-----END PGP SIGNATURE-----
Merge tag 'sunxi-config64-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/defconfig
Allwinner arm64 defconfig for 4.21
A bunch of patches to improve the coverage of Allwinner drivers in the
arm64 defconfig, mostly targeted at adding display drivers support.
* tag 'sunxi-config64-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: defconfig: Enable PWM_SUN4I
arm64: defconfig: Enable DRM_SUN8I_DW_HDMI
arm64: defconfig: Enable DRM_SUN8I_MIXER
arm64: defconfig: Enable MFD_AXP20X_I2C
Signed-off-by: Olof Johansson <olof@lixom.net>
hdmi output for rockpro64, vpu node on rk3399 and adding the
always on 32kHz clock on rk3399-Gru to get a more complete clock
tree.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlwQxHMQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgTbOCACON4DSK2x1MpKOOcUMniqPW6Q7KP3o5MJ6
vTgBHdnjTK4LQLrq/B0LBwe4czJSj0uKxdf4bPddZgZSvM1bSdjQ7YHoZNRB5UTx
pO4qiiGdLw4CAAMEhaOivN51KBxri+qyUNq/Pyh5lhhyrqjPswDzyA4ou22SaXzY
2BqT8tzHDUmCzXM+0mD+81VMCQax5rezjDFeod6MRT5oSqa4xht7fd4M2Wc5Vqkr
B0YfdWvH9ey06vF8bLm2828yA6Gr3uCEHbkVD15PNBGixN0aRSSH6BEThFih+PHq
nMkN51wZepnkW3q8wIU6O46UERWE7ySmyZD8ph45IuPtEBXy+aOG
=s5pB
-----END PGP SIGNATURE-----
Merge tag 'v4.21-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Support for the onboard LEDs of the 2 96boards (ficus, rock960),
hdmi output for rockpro64, vpu node on rk3399 and adding the
always on 32kHz clock on rk3399-Gru to get a more complete clock
tree.
* tag 'v4.21-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: Add on-board LED support on rk3399-rock960
arm64: dts: rockchip: Add on-board LED support on rk3399-ficus
arm64: dts: rockchip: enable hdmi output on rk3399-rockpro64
arm64: dts: rockchip: add VPU device node for RK3399
arm64: dts: rockchip: Add 32k clk on rk3399-gru
Signed-off-by: Olof Johansson <olof@lixom.net>
- Add device tree for LS1028A SoC and NXP FRWY & QDS boards support
based on this SoC.
- Add device tree for LX2160A SoC and NXP QDS & RDB boards support
based on this SoC.
- Add qdma devices for LS1043A and LS1046A SoC.
- Disable PCIe device by default in SoC device tree and let board level
device tree to enable as needed.
- Drop compatible string "snps,dw-pcie" from LayerScape PCIe devices to
avoid incorrect matching.
- Move fsl-mc device as a child node of soc node, and add missing
dma-ranges property for LS1088A SoC.
- Update LayerScape SoCs' cooling maps to include all devices affected
by individual trip points.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJcDgwJAAoJEFBXWFqHsHzObhIH/0knVFbw3ubCvjxdYh3wKkKp
B7D39BTQZUwJXNc9To79TKsnFbCW9QucofRKeZN6Ln/qIkvPrlmyQ7bafaz6Lah4
i++bNIyDtHUQ0ZBB/37vl5n+KRbX7CnRsGwEiZnOCBXdKJcsaMYBXKh7q3o4vFRy
PgacoiipkfYVSosQmxoC/b4PUeYCWa8Mkh0p6X+1aadI1PT58SZo374/NDAiu4aG
ao2FJgWCyYOCXRVPaDS2XDOUU3cogMJSk3M9c3xtEDI2yfzlKQ1TkoyYYG3WwcH7
5aEqGd5Iky27G2S8p16zoqyhHiC4Vq8fsWRRAnF/mVorNtpJC7BdI86VIzvKQlQ=
=sarB
-----END PGP SIGNATURE-----
Merge tag 'imx-dt64-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt
Freescale arm64 device tree update for 4.21:
- Add device tree for LS1028A SoC and NXP FRWY & QDS boards support
based on this SoC.
- Add device tree for LX2160A SoC and NXP QDS & RDB boards support
based on this SoC.
- Add qdma devices for LS1043A and LS1046A SoC.
- Disable PCIe device by default in SoC device tree and let board level
device tree to enable as needed.
- Drop compatible string "snps,dw-pcie" from LayerScape PCIe devices to
avoid incorrect matching.
- Move fsl-mc device as a child node of soc node, and add missing
dma-ranges property for LS1088A SoC.
- Update LayerScape SoCs' cooling maps to include all devices affected
by individual trip points.
* tag 'imx-dt64-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: ls1046a: add qdma device tree nodes
arm64: dts: ls1043a: add qdma device tree nodes
arm64: dts: ls1088a: Add missing dma-ranges property
arm64: dts: ls1088a: Move fsl-mc node
arm64: dts: fsl: Add all CPUs in cooling maps
arm64: dts: Add support for NXP LS1028A SoC
arm64: dts: layerscape: removed compatible string "snps,dw-pcie"
arm64: dts: fsl: Add the status property disable PCIe
arm64: dts: ls1012a: Add FRWY-LS1012A board support
arm64: dts: add LX2160AQDS board support
arm64: dts: add LX2160ARDB board support
arm64: dts: add QorIQ LX2160A SoC support
Signed-off-by: Olof Johansson <olof@lixom.net>
1. Update DWC3 hardware modules to Exynos5433 specific variant.
2. Update cooling maps to include all CPU devices in multiple DTS files.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAlwM920QHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD14IfD/4iMXDbb3VKcQyKFjepxhxtXsQ/cgOuDepG
enamjIVBkXFocbldVtEiKb2KM0j278It+8Q/vT5gvHESc/UL4nOJsmLUcaaIG6Jf
yqk3QDM3IzvKimT/UQFK871D6yMOYkLilaX9QL8RwdEtaBIEQNpT7OJORVjcxwbK
MXDyfO+B6qjcT4puulPv37/RWQEajN8qtTEwAlshvRoD8VPqIwU0sLKuMbKrU0wL
J4SZU6jPejwsB1xHJRE+Qq8aJVFCSdSd1vKYRObYfb1q0pBKg6npcEzEURl/G1OB
wcRfbT1Sg9u38a+qTSVMaEAgqfISB/mfeZbjJ/wJ/QaokAXoAxHhTX6M9BtWBAv2
iSRa9RR9I2dN7ZLeuq7SFxLsrglpnxundGUCg9ahmGLcnc+mUfM+ghNYYAIjsgLb
hUE8purXZMUJssvkOp6KjN9D5HW7nLvghNZ5ivQ99qIrPAwFZsZLIbcyrFKN8zCK
oa9gtSbDSOxOB43Uqh/93c7/1sCgJSuQgQnvDbV00ttQrApgHBFRBssaU9ByZz12
lBr7cAfEHAUrN+qvioOCWGp8jGBDbIoLeHm0KAV298TkLzVj1fnewrbcZjjew/+K
c398nGabl8AToLi6AHepCw6KPz8QWVX/mphw8hiUIWHMQfclSWMPLqEbdjdGHKqU
8LXDEUQZaQ==
=vgas
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt64-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt
Samsung DTS ARM64 changes for v4.21
1. Update DWC3 hardware modules to Exynos5433 specific variant.
2. Update cooling maps to include all CPU devices in multiple DTS files.
* tag 'samsung-dt64-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Add all CPUs in cooling maps
arm64: dts: exynos: Update DWC3 modules on Exynos5433 SoCs
Signed-off-by: Olof Johansson <olof@lixom.net>
- complete the description of the clearfog-gt-8k board (Armada 8040
based board)
- declare eMMC on espressobin (Armada 3720 based board) which still
need to be enable by the bootloader as it is not present on all the
board.
- add a new version of the Macchiatobin (Armada 8040 based board): the
Single Shot (without the 10G 3310 PHYs).
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCXAuF0wAKCRALBhiOFHI7
1Z0ZAJ41K0DWU/kNuQ8ZKTWhUFIVNNVxagCgnumdAUE7jxpgXu+WaVMNMXSJi+A=
=9Qkr
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt64-4.21-1' of git://git.infradead.org/linux-mvebu into next/dt
mvebu dt64 for 4.21 (part 1)
- complete the description of the clearfog-gt-8k board (Armada 8040
based board)
- declare eMMC on espressobin (Armada 3720 based board) which still
need to be enable by the bootloader as it is not present on all the
board.
- add a new version of the Macchiatobin (Armada 8040 based board): the
Single Shot (without the 10G 3310 PHYs).
* tag 'mvebu-dt64-4.21-1' of git://git.infradead.org/linux-mvebu:
arm64: dts: clearfog-gt-8k: describe mini-PCIe CON2 USB
arm64: dts: add support for Macchiatobin Single Shot board
arm64: dts: marvell: armada-37xx: Enable emmc on espressobin
arm64: dts: marvell: armada37xx: Add emmc/sdio pinctrl definition
arm64: dts: clearfog-gt-8k: enable mini-PCIe CON2 USB
arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal
arm64: dts: clearfog-gt-8k: fix USB regulator gpio polarity
Signed-off-by: Olof Johansson <olof@lixom.net>
* Switch to use dwc3-qcom glue driver on MSM8996
* Fix issue with xo clk name on MSM8998
* Add cooling maps on MSM8916
* Add UART nodes on SDM845
* Add camera subsystem support on MSM8996 and MSM8916
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJcCv8oAAoJEFKiBbHx2RXVPU8P/RdMSnKQp4hWtXyi/n0x8A7W
221Q/VQNzv4HjujdBP/+QsDBErrkb2JKUvqS5VPYqh1MPHnmbXuv185Ccr9m6L+D
YMNpZoMe1bWhUmdQnSS95DSeLzIpCS8sSyczWUdQlm1faVoFZ7A6XyGdFUKVCBqf
6x3egZb8gBDKfUS1KnzEo8bhWxltdzK7TOmjZQJzZIqFmQ5eb42YV+mBhRAwj6nt
1wi93eof+f7DOSVOtBebyiDiWAKVcuDAZgMDe0cDVJzxgNx9ODAxheF1DPM9P2XK
izak3TRdlEgZLMUuH65mlqxR3FGqMoKpPrl+WYrQIFO6NdgUiB308TJDPW85B9eE
1ZSZOFr059K4btP8kG27PBKxISKuLsiFW348zP2Cx1QOquQUX/R2t7yfsShAABQX
S3MpUvHzGwfCuHih+SNSmk3cd10C65efNR9UN4MwbKtFqVRfiWRSKWGgWMQNkOQ0
ga6NKK2OfTqGeJ5MYnqM0Ke25+ACkdW1UMhGaFg3IPqTwdZZ2ClKDq2I8AvqnZ1G
k656Z4KGud8RifPBeRARqzRe8ZCxomns7f66IAyCP6xO/pxC+JcjBL0GY3bBDNsE
QA4kfrLQ27LTDvICEOdUsshUoiDBg+keEttbLI0QCh6GTyZKL8yqDp8xICp1AEvq
InAboFK/dxsqdmRNkgAh
=EMri
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-for-4.21-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt
Qualcomm ARM64 Updates for v4.21 Part 2
* Switch to use dwc3-qcom glue driver on MSM8996
* Fix issue with xo clk name on MSM8998
* Add cooling maps on MSM8916
* Add UART nodes on SDM845
* Add camera subsystem support on MSM8996 and MSM8916
* tag 'qcom-arm64-for-4.21-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
arm64: dts: msm8996: Use dwc3-qcom glue driver for USB
arm64: dts: qcom: msm8998: Fixup clock to use xo_board
arm64: dts: qcom: sdm845: Add UART nodes
arm64: dts: qcom: msm8996: Add CAMSS support
arm64: dts: qcom: msm8996: Add VFE SMMU node
arm64: dts: qcom: Add pinctrls for camera sensors
arm64: dts: qcom: Add Camera Control Interface pinctrls
arm64: dts: qcom: msm8916: Add CAMSS support
arm64: dts: qcom: msm8916: Add IOMMU sub-node for VFE context bank
arm64: dts: msm8916: Add all CPUs in cooling maps
Signed-off-by: Olof Johansson <olof@lixom.net>
Our usual set of arm64 DT changes, with the biggest additions being:
- Support for the video decoding engine in the A64
- Support for the audio codec in the A64
- USB Support in the H6
- HDMI Support in the H6
- EMAC Support in the H6
- New board: Orange Pi Lite2
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXAqGvQAKCRDj7w1vZxhR
xeObAQDZGMVjFjiWlC0jYjBQoCHMf1dlu6iPd4qe8h3GS1XUVQD/c8SJaMj5oLX1
HKjtqQD+sJRUQdcWlwAsqEEKyKUhfQs=
=aAr3
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt64-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt
Allwinner arm64 DT changes for 4.21
Our usual set of arm64 DT changes, with the biggest additions being:
- Support for the video decoding engine in the A64
- Support for the audio codec in the A64
- USB Support in the H6
- HDMI Support in the H6
- EMAC Support in the H6
- New board: Orange Pi Lite2
* tag 'sunxi-dt64-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (27 commits)
arm64: dts: allwinner: a64: Fix up RTC device node and clock references
arm64: dts: allwinner: a64: Add Video Engine node
arm64: dts: allwinner: a64: Add support for the SRAM C1 section
arm64: dts: allwinner: a64: pinebook: enable power supplies
arm64: dts: allwinner: a64: sopine-baseboard: enable power supplies
arm64: dts: allwinner: axp803: add AC and battery power supplies
arm64: dts: allwinner: a64: bananapi-m64: Enable audio codec
arm64: dts: allwinner: a64: enable sound on Pinebook
arm64: dts: allwinner: a64: enable sound on Pine64 and SoPine
arm64: dts: allwinner: a64: add nodes necessary for analog sound support
arm64: dts: allwinner: h6: orangepi: Add device nodes for LEDs
arm64: dts: allwinner: h6: orangepi: Enable USB 2.0 host and OTG ports
arm64: dts: allwinner: h6: orangepi: Add board-wide 5V regulator
arm64: dts: allwinner: h6: fix EMAC compatible string sequence
arm64: dts: allwinner: a64: Add device node for Mali-400 GPU
dt-bindings: gpu: mali-utgard: Add compatible for A64 Mali
arm64: dts: allwinner: h6: enable USB2 on Pine H64
arm64: dts: allwinner: h6: add USB Vbus regulator for Pine H64
arm64: dts: allwinner: h6: add USB2-related device nodes
arm64: dts: allwinner: h6: Enable HDMI output on Pine H64 board
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This is a quite big pull request this time, with a huge number of changes
(and patches) due to us fixing the vast majority of the DTC warnings our DT
had.
We also have a bunch of other good, more meaningful, changes:
- Support for the new Allwinner T3 (rebranded R40) and f1c100s (armv5)
SoCs
- AXP803 PMIC AC Power supply support
- Rework of the oscillators tree
- Two new boards: the t3-cqa3t-bv3 and Lichee Pi Nano
Plus a few enhancements here and there.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXAqFhwAKCRDj7w1vZxhR
xcQzAQDJu0dPrs3SQlWdDhOa0iFVp/7gmN4iRMxMScIIjrRUgAEAzmhUjQNNTNLc
OPF9XzMdT12rs2SAbk2XXtWH1hN8KQA=
=vSCG
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt
Allwinner DT changes for 4.21
This is a quite big pull request this time, with a huge number of changes
(and patches) due to us fixing the vast majority of the DTC warnings our DT
had.
We also have a bunch of other good, more meaningful, changes:
- Support for the new Allwinner T3 (rebranded R40) and f1c100s (armv5)
SoCs
- AXP803 PMIC AC Power supply support
- Rework of the oscillators tree
- Two new boards: the t3-cqa3t-bv3 and Lichee Pi Nano
Plus a few enhancements here and there.
* tag 'sunxi-dt-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (84 commits)
ARM: dts: sunxi: Fix PMU compatible strings
ARM: dts: sun8i: r40: Add RTC device node
ARM: dts: sunxi: h3/h5: Fix up RTC device node and clock references
ARM: dts: sun8i: a23/a33: Fix up RTC device node
ARM: dts: sun8i: r40: Add clock accuracy for external oscillators
ARM: dts: sunxi: h3/h5: Add clock accuracy for external oscillators
ARM: dts: sun8i: a33: Drop audio codec oversampling rate to 128 fs
ARM: dts: sun8i: h3: Remove unnecessary reserved memory node
ARM: dts: sun8i: a33: Remove unnecessary reserved memory node
ARM: dts: suniv: Add device tree for Lichee Pi Nano
ARM: dts: suniv: add initial DTSI file for F1C100s
ARM: dts: axp81x: add AC power supply subnode
ARM: dts: sun8i: v3s: Remove skeleton and memory to avoid warnings
ARM: dts: sun8i: v3s: Provide default muxing for relevant controllers
ARM: dts: sun8i: v3s: Change pinctrl nodes to avoid warning
ARM: dts: sun8i: v3s: Change LRADC node names to avoid warnings
ARM: dts: sun8i: h3: Remove leading zeros from unit-addresses
ARM: dts: sun8i: BPI-M2M: Remove i2c nodes
ARM: dts: sun8i: a23/a33: Provide default muxing for relevant controllers
ARM: dts: sunxi: reference: Move the muxing back to the common DTSI
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This enables the use of per-task stack canary values if GCC has
support for emitting the stack canary reference relative to the
value of sp_el0, which holds the task struct pointer in the arm64
kernel.
The $(eval) extends KBUILD_CFLAGS at the moment the make rule is
applied, which means asm-offsets.o (which we rely on for the offset
value) is built without the arguments, and everything built afterwards
has the options set.
Reviewed-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Wire up the basic support for hot-adding memory. Since memory hotplug
is fairly tightly coupled to sparsemem, we tweak pfn_valid() to also
cross-check the presence of a section in the manner of the generic
implementation, before falling back to memblock to check for no-map
regions within a present section as before. By having arch_add_memory(()
create the linear mapping first, this then makes everything work in the
way that __add_section() expects.
We expect hotplug to be ACPI-driven, so the swapper_pg_dir updates
should be safe from races by virtue of the global device hotplug lock.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Commit 959bf2fd03 ("arm64: percpu: Rewrite per-cpu ops to allow use of
LSE atomics") introduced alternative code sequences for the arm64 percpu
atomics, so that the LSE instructions can be patched in at runtime if
they are supported by the CPU.
Unfortunately, when patching in the LSE sequence for a value-returning
pcpu atomic, the argument registers are the wrong way round. The
implementation of this_cpu_add_return() therefore ends up adding
uninitialised stack to the percpu variable and returning garbage.
As it turns out, there aren't very many users of the value-returning
percpu atomics in mainline and we only spotted this due to a failure in
the kprobes selftests. In this case, when attempting to single-step over
the out-of-line instruction slot, the debug monitors would not be
enabled because calling this_cpu_inc_return() on the kernel debug
monitor refcount would fail to detect the transition from 0. We would
consequently execute past the slot and take an undefined instruction
exception from the kernel, resulting in a BUG:
| kernel BUG at arch/arm64/kernel/traps.c:421!
| PREEMPT SMP
| pc : do_undefinstr+0x268/0x278
| lr : do_undefinstr+0x124/0x278
| Process swapper/0 (pid: 1, stack limit = 0x(____ptrval____))
| Call trace:
| do_undefinstr+0x268/0x278
| el1_undef+0x10/0x78
| 0xffff00000803c004
| init_kprobes+0x150/0x180
| do_one_initcall+0x74/0x178
| kernel_init_freeable+0x188/0x224
| kernel_init+0x10/0x100
| ret_from_fork+0x10/0x1c
Fix the argument order to get the value-returning pcpu atomics working
correctly when implemented using the LSE instructions.
Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
While we can export symbols from assembly files, CONFIG_MODVERIONS requires C
declarations of anyhting that's exported.
Let's account for this as other architectures do by placing these declarations
in <asm/asm-prototypes.h>, which kbuild will automatically use to generate
modversion information for assembly files.
Since we already define most prototypes in existing headers, we simply need to
include those headers in <asm/asm-prototypes.h>, and don't need to duplicate
these.
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
With the introduction of 52-bit virtual addressing for userspace, we are
now in a position where the virtual addressing capability of userspace
may exceed that of the kernel. Consequently, the VA_BITS definition
cannot be used blindly, since it reflects only the size of kernel
virtual addresses.
This patch introduces MAX_USER_VA_BITS which is either VA_BITS or 52
depending on whether 52-bit virtual addressing has been configured at
build time, removing a few places where the 52 is open-coded based on
explicit CONFIG_ guards.
Signed-off-by: Will Deacon <will.deacon@arm.com>
This patch enables arm64's bpf_int_jit_compile() to provide
bpf_line_info by calling bpf_prog_fill_jited_linfo().
Signed-off-by: Martin KaFai Lau <kafai@fb.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
In some randconfig builds, the new CONFIG_ARM64_USER_VA_BITS_52
triggered a build failure:
arch/arm64/mm/proc.S:287: Error: immediate out of range
As it turns out, we were incorrectly setting PGTABLE_LEVELS here,
lacking any other default value.
This fixes the calculation of CONFIG_PGTABLE_LEVELS to consider
all combinations again.
Fixes: 68d23da437 ("arm64: Kconfig: Re-jig CONFIG options for 52-bit VA")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Commit 3962446922 ("arm64: preempt: Provide our own implementation of
asm/preempt.h") extended the preempt count field in struct thread_info
to 64 bits, so that it consists of a 32-bit count plus a 32-bit flag
indicating whether or not the current task needs rescheduling.
Whilst the asm-offsets definition of TSK_TI_PREEMPT was updated to point
to this new field, the assembly usage was left untouched meaning that a
32-bit load from TSK_TI_PREEMPT on a big-endian machine actually returns
the reschedule flag instead of the count.
Whilst we could fix this by pointing TSK_TI_PREEMPT at the count field,
we're actually better off reworking the two assembly users so that they
operate on the whole 64-bit value in favour of inspecting the thread
flags separately in order to determine whether a reschedule is needed.
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reported-by: "kernelci.org bot" <bot@kernelci.org>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Add on-board LED support for Rock960 board based on the following
standard used by rest of the 96Boards:
green:user1 default-trigger: heartbeat
green:user2 default-trigger: mmc0/disk-activity(onboard-storage)
green:user3 default-trigger: mmc1 (SD-card)
green:user4 default-trigger: none, panic-indicator
yellow:wlan default-trigger: phy0tx
blue:bt default-trigger: hci0-power
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add on-board LED support for Ficus board based on the following
standard used by other 96Boards:
red:user1 default-trigger: heartbeat
red:user2 default-trigger: mmc0/disk-activity (onboard-storage)
red:user3 default-trigger: mmc1 (SD-card)
red:user4 default-trigger: none, panic-indicator
red:wlan default-trigger: phy0tx
red:bt default-trigger: hci0-power
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
These changes add a bunch of features for Tegra194 and Tegra186, such as
wake events, on-die RTC, temperature sensors, HDA for audio over HDMI
and fan support on Jetson Xavier to allow cooling of the device.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlwKf7oTHHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zofceD/43trVxXm9WMt/mTWfVZuhJNmgnt8x2
38m8cM09nw/E4sBMUfNwyUPo18swxZ1AEmluSkw1Rc6kzEU2S3xMv2lqJX70fyZE
nl3Rt9NUu6YwWaackGZuqq4LWa6BhnMxuNPuEvapMIoFIpFT+wT+12M7CxK99Z2I
0Du3Q0F/7v4Q9jvjMrdyerd/Jd43HkeysFR4hLJjaBkExVRfsntR7wb2P7kMWlRL
A3rXhB5L9ZAze54z3jJyEayx8Eiq7qCh3iuKYZ3VeuOKcFbSUy4MjAg1ZoKrir2G
6YbCmSURnnsj4A4OJD+P9g/0sWjE+9QWnnxeN5bFEcA4SnSLJT3F65z9G19p65/k
Y2CDl7LAMFJN+1iYxWhQOfVw+LUGycs0eTrpNxoSSzZ/MSntexCTgFox1SCqfF/x
fP9zmZGoZIQ/G9H+trhT1eRiE0l25gJjJGIcxRQTYtgVicK1YpsF8oBzl6k8sikI
XpK0dO6kCsyLjfqw3VKoR3ZTLl4YJq6qQObaxtoFz94QaCudRcJ42AaHjdCOGhSP
IXlp4/YFih9z2Uw58e09YcM0TawcAXS0h2twKMif7ktMBcO2Eo79c3cEapCgbo3e
MN7yyoscNrIbl3PKhdj1J5VTU0li2EKZXfXPQZAf0NSPXJ9IZN0KWP5E23FgrpJB
1+rrxD/8IhxoLg==
=CDXO
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-4.21-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt
arm64: tegra: Device tree change for v4.21-rc1
These changes add a bunch of features for Tegra194 and Tegra186, such as
wake events, on-die RTC, temperature sensors, HDA for audio over HDMI
and fan support on Jetson Xavier to allow cooling of the device.
* tag 'tegra-for-4.21-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (29 commits)
arm64: tegra: Set reg property for display-hub on Tegra194
arm64: tegra: Set reg property for display-hub on Tegra186
arm64: dts: tegra186: Enable IOMMU for SDHCI
arm64: tegra: Enable HDA controller on Jetson TX1
arm64: tegra: Add CEC controller on Tegra194
arm64: tegra: Enable HDA on Jetson Xavier
arm64: tegra: Add HDA controller on Tegra194
arm64: tegra: Add CEC controller on Tegra186
arm64: tegra: Enable HDA on Jetson TX2
arm64: tegra: Add HDA controller on Tegra186
arm64: tegra: Add temperature sensor on P2888
arm64: tegra: Add gpio-keys on Jetson Xavier
arm64: tegra: Add AON GPIO controller on Tegra194
arm64: tegra: p2888: Enable on-die RTC
arm64: tegra: Add RTC support on Tegra194
arm64: tegra: Enable PMC wake events on Tegra194
arm64: tegra: p3310: Enable on-die RTC
arm64: tegra: Add RTC support on Tegra186
arm64: tegra: Enable PMC wake events on Tegra186
arm64: tegra: Fix power key interrupt type on Jetson TX2
...
Signed-off-by: Olof Johansson <olof@lixom.net>
We need to invalidate the caches *before* clearing the buffer via the
non-cacheable alias, else in the worst case __dma_flush_area() may
write back dirty lines over the top of our nice new zeros.
Fixes: dd65a941f6 ("arm64: dma-mapping: clear buffers allocated with FORCE_CONTIGUOUS flag")
Cc: <stable@vger.kernel.org> # 4.18.x-
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This is needed for compilation in some configurations that don't
include it implicitly:
arch/arm64/kernel/machine_kexec_file.c: In function 'arch_kimage_file_post_load_cleanup':
arch/arm64/kernel/machine_kexec_file.c:37:2: error: implicit declaration of function 'vfree'; did you mean 'kvfree'? [-Werror=implicit-function-declaration]
Fixes: 52b2a8af74 ("arm64: kexec_file: load initrd and device-tree")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Daniel Borkmann says:
====================
pull-request: bpf-next 2018-12-11
The following pull-request contains BPF updates for your *net-next* tree.
It has three minor merge conflicts, resolutions:
1) tools/testing/selftests/bpf/test_verifier.c
Take first chunk with alignment_prevented_execution.
2) net/core/filter.c
[...]
case bpf_ctx_range_ptr(struct __sk_buff, flow_keys):
case bpf_ctx_range(struct __sk_buff, wire_len):
return false;
[...]
3) include/uapi/linux/bpf.h
Take the second chunk for the two cases each.
The main changes are:
1) Add support for BPF line info via BTF and extend libbpf as well
as bpftool's program dump to annotate output with BPF C code to
facilitate debugging and introspection, from Martin.
2) Add support for BPF_ALU | BPF_ARSH | BPF_{K,X} in interpreter
and all JIT backends, from Jiong.
3) Improve BPF test coverage on archs with no efficient unaligned
access by adding an "any alignment" flag to the BPF program load
to forcefully disable verifier alignment checks, from David.
4) Add a new bpf_prog_test_run_xattr() API to libbpf which allows for
proper use of BPF_PROG_TEST_RUN with data_out, from Lorenz.
5) Extend tc BPF programs to use a new __sk_buff field called wire_len
for more accurate accounting of packets going to wire, from Petar.
6) Improve bpftool to allow dumping the trace pipe from it and add
several improvements in bash completion and map/prog dump,
from Quentin.
7) Optimize arm64 BPF JIT to always emit movn/movk/movk sequence for
kernel addresses and add a dedicated BPF JIT backend allocator,
from Ard.
8) Add a BPF helper function for IR remotes to report mouse movements,
from Sean.
9) Various cleanups in BPF prog dump e.g. to make UAPI bpf_prog_info
member naming consistent with existing conventions, from Yonghong
and Song.
10) Misc cleanups and improvements in allowing to pass interface name
via cmdline for xdp1 BPF example, from Matteo.
11) Fix a potential segfault in BPF sample loader's kprobes handling,
from Daniel T.
12) Fix SPDX license in libbpf's README.rst, from Andrey.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
TASK_SIZE is defined using the vabits_user variable for 64-bit tasks,
so ensure that this variable is exported to modules to avoid the
following build breakage with allmodconfig:
| ERROR: "vabits_user" [lib/test_user_copy.ko] undefined!
| ERROR: "vabits_user" [drivers/misc/lkdtm/lkdtm.ko] undefined!
| ERROR: "vabits_user" [drivers/infiniband/hw/mlx5/mlx5_ib.ko] undefined!
Signed-off-by: Will Deacon <will.deacon@arm.com>
The __cpu_up() routine ignores the errors reported by the firmware
for a CPU bringup operation and looks for the error status set by the
booting CPU. If the CPU never entered the kernel, we could end up
in assuming stale error status, which otherwise would have been
set/cleared appropriately by the booting CPU.
Reported-by: Steve Capper <steve.capper@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Rather than add additional variables to detect specific early feature
mismatches with secondary CPUs, we can instead dedicate the upper bits
of the CPU boot status word to flag specific mismatches.
This allows us to communicate both granule and VA-size mismatches back
to the primary CPU without the need for additional book-keeping.
Tested-by: Steve Capper <steve.capper@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Enabling 52-bit VAs for userspace is pretty confusing, since it requires
you to select "48-bit" virtual addressing in the Kconfig.
Rework the logic so that 52-bit user virtual addressing is advertised in
the "Virtual address space size" choice, along with some help text to
describe its interaction with Pointer Authentication. The EXPERT-only
option to force all user mappings to the 52-bit range is then made
available immediately below the VA size selection.
Signed-off-by: Will Deacon <will.deacon@arm.com>
On arm64 52-bit VAs are provided to userspace when a hint is supplied to
mmap. This helps maintain compatibility with software that expects at
most 48-bit VAs to be returned.
In order to help identify software that has 48-bit VA assumptions, this
patch allows one to compile a kernel where 52-bit VAs are returned by
default on HW that supports it.
This feature is intended to be for development systems only.
Signed-off-by: Steve Capper <steve.capper@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
On arm64 there is optional support for a 52-bit virtual address space.
To exploit this one has to be running with a 64KB page size and be
running on hardware that supports this.
For an arm64 kernel supporting a 48 bit VA with a 64KB page size,
some changes are needed to support a 52-bit userspace:
* TCR_EL1.T0SZ needs to be 12 instead of 16,
* TASK_SIZE needs to reflect the new size.
This patch implements the above when the support for 52-bit VAs is
detected at early boot time.
On arm64 userspace addresses translation is controlled by TTBR0_EL1. As
well as userspace, TTBR0_EL1 controls:
* The identity mapping,
* EFI runtime code.
It is possible to run a kernel with an identity mapping that has a
larger VA size than userspace (and for this case __cpu_set_tcr_t0sz()
would set TCR_EL1.T0SZ as appropriate). However, when the conditions for
52-bit userspace are met; it is possible to keep TCR_EL1.T0SZ fixed at
12. Thus in this patch, the TCR_EL1.T0SZ size changing logic is
disabled.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steve Capper <steve.capper@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
For cases where there is a mismatch in ARMv8.2-LVA support between CPUs
we have to be careful in allowing secondary CPUs to boot if 52-bit
virtual addresses have already been enabled on the boot CPU.
This patch adds code to the secondary startup path. If the boot CPU has
enabled 52-bit VAs then ID_AA64MMFR2_EL1 is checked to see if the
secondary can also enable 52-bit support. If not, the secondary is
prevented from booting and an error message is displayed indicating why.
Technically this patch could be implemented using the cpufeature code
when considering 52-bit userspace support. However, we employ low level
checks here as the cpufeature code won't be able to run if we have
mismatched 52-bit kernel va support.
Signed-off-by: Steve Capper <steve.capper@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Enabling 52-bit VAs on arm64 requires that the PGD table expands from 64
entries (for the 48-bit case) to 1024 entries. This quantity,
PTRS_PER_PGD is used as follows to compute which PGD entry corresponds
to a given virtual address, addr:
pgd_index(addr) -> (addr >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)
Userspace addresses are prefixed by 0's, so for a 48-bit userspace
address, uva, the following is true:
(uva >> PGDIR_SHIFT) & (1024 - 1) == (uva >> PGDIR_SHIFT) & (64 - 1)
In other words, a 48-bit userspace address will have the same pgd_index
when using PTRS_PER_PGD = 64 and 1024.
Kernel addresses are prefixed by 1's so, given a 48-bit kernel address,
kva, we have the following inequality:
(kva >> PGDIR_SHIFT) & (1024 - 1) != (kva >> PGDIR_SHIFT) & (64 - 1)
In other words a 48-bit kernel virtual address will have a different
pgd_index when using PTRS_PER_PGD = 64 and 1024.
If, however, we note that:
kva = 0xFFFF << 48 + lower (where lower[63:48] == 0b)
and, PGDIR_SHIFT = 42 (as we are dealing with 64KB PAGE_SIZE)
We can consider:
(kva >> PGDIR_SHIFT) & (1024 - 1) - (kva >> PGDIR_SHIFT) & (64 - 1)
= (0xFFFF << 6) & 0x3FF - (0xFFFF << 6) & 0x3F // "lower" cancels out
= 0x3C0
In other words, one can switch PTRS_PER_PGD to the 52-bit value globally
provided that they increment ttbr1_el1 by 0x3C0 * 8 = 0x1E00 bytes when
running with 48-bit kernel VAs (TCR_EL1.T1SZ = 16).
For kernel configuration where 52-bit userspace VAs are possible, this
patch offsets ttbr1_el1 and sets PTRS_PER_PGD corresponding to the
52-bit value.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steve Capper <steve.capper@arm.com>
[will: added comment to TTBR1_BADDR_4852_OFFSET calculation]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Now that we have DEFAULT_MAP_WINDOW defined, we can arch_get_mmap_end
and arch_get_mmap_base helpers to allow for high addresses in mmap.
Signed-off-by: Steve Capper <steve.capper@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
We wish to introduce a 52-bit virtual address space for userspace but
maintain compatibility with software that assumes the maximum VA space
size is 48 bit.
In order to achieve this, on 52-bit VA systems, we make mmap behave as
if it were running on a 48-bit VA system (unless userspace explicitly
requests a VA where addr[51:48] != 0).
On a system running a 52-bit userspace we need TASK_SIZE to represent
the 52-bit limit as it is used in various places to distinguish between
kernelspace and userspace addresses.
Thus we need a new limit for mmap, stack, ELF loader and EFI (which uses
TTBR0) to represent the non-extended VA space.
This patch introduces DEFAULT_MAP_WINDOW and DEFAULT_MAP_WINDOW_64 and
switches the appropriate logic to use that instead of TASK_SIZE.
Signed-off-by: Steve Capper <steve.capper@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
If the kernel is configured with KASAN_EXTRA, the stack size is
increased significantly due to setting the GCC -fstack-reuse option to
"none" [1]. As a result, it can trigger a stack overrun quite often with
32k stack size compiled using GCC 8. For example, this reproducer
https://github.com/linux-test-project/ltp/blob/master/testcases/kernel/syscalls/madvise/madvise06.c
can trigger a "corrupted stack end detected inside scheduler" very
reliably with CONFIG_SCHED_STACK_END_CHECK enabled. There are other
reports at:
https://lore.kernel.org/lkml/1542144497.12945.29.camel@gmx.us/https://lore.kernel.org/lkml/721E7B42-2D55-4866-9C1A-3E8D64F33F9C@gmx.us/
There are just too many functions that could have a large stack with
KASAN_EXTRA due to large local variables that have been called over and
over again without being able to reuse the stacks. Some noticiable ones
are,
size
7536 shrink_inactive_list
7440 shrink_page_list
6560 fscache_stats_show
3920 jbd2_journal_commit_transaction
3216 try_to_unmap_one
3072 migrate_page_move_mapping
3584 migrate_misplaced_transhuge_page
3920 ip_vs_lblcr_schedule
4304 lpfc_nvme_info_show
3888 lpfc_debugfs_nvmestat_data.constprop
There are other 49 functions over 2k in size while compiling kernel with
"-Wframe-larger-than=" on this machine. Hence, it is too much work to
change Makefiles for each object to compile without
-fsanitize-address-use-after-scope individually.
[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715#c23
Signed-off-by: Qian Cai <cai@lca.pw>
Signed-off-by: Will Deacon <will.deacon@arm.com>
It has been reported that ftrace_replace_code() which is called by
ftrace_modify_all_code() can cause a soft lockup warning for an
allmodconfig kernel. This is because all the debug options enabled
causes the loop in ftrace_replace_code() (which loops over all the
functions being enabled where there can be 10s of thousands), is too
slow, and never schedules out.
To solve this, setting FTRACE_MAY_SLEEP to the command passed into
ftrace_replace_code() will make it call cond_resched() in the loop,
which prevents the soft lockup warning from triggering.
Link: http://lkml.kernel.org/r/20181204192903.8193-1-anders.roxell@linaro.org
Link: http://lkml.kernel.org/r/20181205183304.000714627@goodmis.org
Acked-by: Will Deacon <will.deacon@arm.com>
Reported-by: Anders Roxell <anders.roxell@linaro.org>
Tested-by: Anders Roxell <anders.roxell@linaro.org>
Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
The usual batch; most of them are DT tweaks to fix misdescribed
hardware. Beyond that:
- A bugfix for MMP2 CPU detection, it's been there quite a while but
makes sense to fix now anyway.
- Some power management tweaks;
+ disabling of CPU idle power state on Marvell Armada 7K/8K (Macchiatobin et al)
+ Increase of minimum voltage on BananaPi M3
+ Tweak of power ramp time for DVFS on NXP/Freescale i.MX7SX
- A couple of MAINTAINER updates; MMP has a new volunteer to look after
it, and Mediatek adds a few keywords, IRC channel and wiki URL.
-----BEGIN PGP SIGNATURE-----
iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAlwNtPAPHG9sb2ZAbGl4
b20ubmV0AAoJEIwa5zzehBx3o7oQAKbaWFicYzMaH1MK7wmNf2k0VKqwA0EQcQKA
DSfT+16bcnetP84e559k5YwpjUKAW7c/LfG5zQ/Zz1ZXdDRPKNDpT+C0mqg0DPeM
IcraDbRooqeT9VNNCFRr22nB5kp57OjmFDnDjYVoZbjTjyI2uAgaZGA4AMCauOS5
LzUXqxkMSe+LVqHeTnnHZDol4ICOlIg5eBkhmmRd3fCPq2NLI/l0HfCbLHBQsJYe
dlMxkhNzfxepiojY1uGzQledUg0/1JOkJF2tXMWb176JhcZ7Hoxx002/GAm1m0G2
Rkb5/cs3tfl8Jr29LR6h9BCnZZ+q3D4C2e/sWtWYRNB0z0zBqrOIopmtgh5iyERI
T+CeJwf9fso6HTXQnWelYT5+2eQBQfakDx9PbQpYaNoA1g3LwZUxOc6d/t89vYKV
7tWeXJ0/PI2Vo8AUoT6mu4GH62QAZSM7mAg7p8uPFar2IiVd1ktVD4PoXVYsEhvT
h7hljPsYkBC/EcHG9tacTqCMfO0dJfH0AKfzs6PuY22S6+dPDg+ReoAvoF35P0HK
5oHB6WqKEC15ZG72rVurkk1C6YEirBF9wTPmxxBQnwrdqBddjvgl0Lv21ryrcAjW
O3dX24mB9Ayq+ecu797SNPMDPmgnrqJSG/O8JPxjZFIT+0sb2DVFVfW8jHgw1nj9
vqfwi+m3
=gJxg
-----END PGP SIGNATURE-----
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"The usual batch; most of them are DT tweaks to fix misdescribed
hardware. Beyond that:
- A bugfix for MMP2 CPU detection, it's been there quite a while but
makes sense to fix now anyway.
- Some power management tweaks:
+ disabling of CPU idle power state on Marvell Armada 7K/8K
(Macchiatobin et al)
+ Increase of minimum voltage on BananaPi M3
+ Tweak of power ramp time for DVFS on NXP/Freescale i.MX7SX
- A couple of MAINTAINER updates:
+ MMP has a new volunteer to look after it
+ Mediatek adds a few keywords, IRC channel and wiki URL"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: dts: imx7d-nitrogen7: Fix the description of the Wifi clock
ARM: imx: update the cpu power up timing setting on i.mx6sx
Revert "arm64: dts: marvell: add CPU Idle power state support on Armada 7K/8K"
ARM: dts: imx7d-pico: Describe the Wifi clock
ARM: dts: realview: Fix some more duplicate regulator nodes
MAINTAINERS: update entry for MMP platform
ARM: mmp/mmp2: fix cpu_is_mmp2() on mmp2-dt
MAINTAINERS: mediatek: Update SoC entry
ARM: dts: bcm2837: Fix polarity of wifi reset GPIOs
arm64: dts: mt7622: Drop the general purpose timer node
arm64: dts: mt7622: fix no more console output on BPI-R64 board
arm64: dts: mt7622: fix no more console output on rfb1
ARM: dts: sun8i: a83t: bananapi-m3: increase vcc-pd voltage to 3.3V
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The dcache_by_line_op macro suffers from a couple of small problems:
First, the GAS directives that are currently being used rely on
assembler behavior that is not documented, and probably not guaranteed
to produce the correct behavior going forward. As a result, we end up
with some undefined symbols in cache.o:
$ nm arch/arm64/mm/cache.o
...
U civac
...
U cvac
U cvap
U cvau
This is due to the fact that the comparisons used to select the
operation type in the dcache_by_line_op macro are comparing symbols
not strings, and even though it seems that GAS is doing the right
thing here (undefined symbols by the same name are equal to each
other), it seems unwise to rely on this.
Second, when patching in a DC CVAP instruction on CPUs that support it,
the fallback path consists of a DC CVAU instruction which may be
affected by CPU errata that require ARM64_WORKAROUND_CLEAN_CACHE.
Solve these issues by unrolling the various maintenance routines and
using the conditional directives that are documented as operating on
strings. To avoid the complexity of nested alternatives, we move the
DC CVAP patching to __clean_dcache_area_pop, falling back to a branch
to __clean_dcache_area_poc if DCPOP is not supported by the CPU.
Reported-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Suggested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Now that the infrastructure to handle erratum 1165522 is in place,
let's make it a selectable option and add the required documentation.
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
In order to avoid TLB corruption whilst invalidating TLBs on CPUs
affected by erratum 1165522, we need to prevent S1 page tables
from being usable.
For this, we set the EL1 S1 MMU on, and also disable the page table
walker (by setting the TCR_EL1.EPD* bits to 1).
This ensures that once we switch to the EL1/EL0 translation regime,
speculated AT instructions won't be able to parse the page tables.
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
In order to ensure that slipping HCR_EL2.TGE is done at the right
time when switching translation regime, let insert the required ISBs
that will be patched in when erratum 1165522 is detected.
Take this opportunity to add the missing include of asm/alternative.h
which was getting there by pure luck.
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
In order to easily mitigate ARM erratum 1165522, we need to force
affected CPUs to run in VHE mode if using KVM.
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
We are soon going to play with TCR_EL1.EPD{0,1}, so let's add the
relevant definitions.
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
It is a bit odd that we only install stage-2 translation after having
cleared HCR_EL2.TGE, which means that there is a window during which
AT requests could fail as stage-2 is not configured yet.
Let's move stage-2 configuration before we clear TGE, making the
guest entry sequence clearer: we first configure all the guest stuff,
then only switch to the guest translation regime.
While we're at it, do the same thing for !VHE. It doesn't hurt,
and keeps things symmetric.
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
An SVE system is so far the only case where we mandate VHE. As we're
starting to grow this requirements, let's slightly rework the way we
deal with that situation, allowing for easy extension of this check.
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Contrary to the non-VHE version of the TLB invalidation helpers, the VHE
code has interrupts enabled, meaning that we can take an interrupt in
the middle of such a sequence, and start running something else with
HCR_EL2.TGE cleared.
That's really not a good idea.
Take the heavy-handed option and disable interrupts in
__tlb_switch_to_guest_vhe, restoring them in __tlb_switch_to_host_vhe.
The latter also gain an ISB in order to make sure that TGE really has
taken effect.
Cc: stable@vger.kernel.org
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Now that arm64ksyms.c has been reduced to a stub, let's remove it
entirely. New exports should be associated with their function
definition.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
For a while now it's been possible to use EXPORT_SYMBOL() in assembly
files, which allows us to place exports immediately after assembly
functions, as we do for C functions.
As a step towards removing arm64ksyms.c, let's move the ftrace exports
to the assembly files the functions are defined in.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
For a while now it's been possible to use EXPORT_SYMBOL() in assembly
files, which allows us to place exports immediately after assembly
functions, as we do for C functions.
As a step towards removing arm64ksyms.c, let's move the string routine
exports to the assembly files the functions are defined in. Routines
which should only be exported for !KASAN builds are exported using the
EXPORT_SYMBOL_NOKASAN() helper.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
For a while now it's been possible to use EXPORT_SYMBOL() in assembly
files, which allows us to place exports immediately after assembly
functions, as we do for C functions.
As a step towards removing arm64ksyms.c, let's move the uaccess exports
to the assembly files the functions are defined in. As we have to
include <asm/assembler.h>, the existing includes are fixed to follow the
usual ordering conventions.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
For a while now it's been possible to use EXPORT_SYMBOL() in assembly
files, which allows us to place exports immediately after assembly
functions, as we do for C functions.
As a step towards removing arm64ksyms.c, let's move the copy_page and
clear_page exports to the assembly files the functions are defined in.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
For a while now it's been possible to use EXPORT_SYMBOL() in assembly
files, which allows us to place exports immediately after assembly
functions, as we do for C functions.
As a step towards removing arm64ksyms.c, let's move the SMCCC exports to
the assembly file the functions are defined in.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
For a while now it's been possible to use EXPORT_SYMBOL() in assembly
files, which allows us to place exports immediately after assembly
functions, as we do for C functions.
As a step towards removing arm64ksyms.c, let's move the tishift exports
to the assembly file the functions are defined in.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
So that we can export symbols directly from assembly files, let's make
use of the generic <asm/export.h>. We have a few symbols that we'll want
to conditionally export for !KASAN kernel builds, so we add a helper for
that in <asm/assembler.h>.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Since we define memstart_addr in a C file, we can have the export
immediately after the definition of the symbol, as we do elsewhere.
As a step towards removing arm64ksyms.c, move the export of
memstart_addr to init.c, where the symbol is defined.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Now that the arm64 bitops are inlines built atop of the regular atomics,
we don't need to export anything.
Remove the redundant exports.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Adding CPU Idle state in the device tree for Armada 8040 seems to
breaks boot on some board, so let's revert it waiting for a better
solution.
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCXAuDHQAKCRALBhiOFHI7
1c27AJ0ddbDv84YeIAMDGt7ne2W0sjfaTACeIMt0Gk3yNonkTHSnfISzZ9p1Cu4=
=vrYg
-----END PGP SIGNATURE-----
Merge tag 'mvebu-fixes-4.20-1' of git://git.infradead.org/linux-mvebu into fixes
mvebu fixes for 4.20
Adding CPU Idle state in the device tree for Armada 8040 seems to
breaks boot on some board, so let's revert it waiting for a better
solution.
* tag 'mvebu-fixes-4.20-1' of git://git.infradead.org/linux-mvebu:
Revert "arm64: dts: marvell: add CPU Idle power state support on Armada 7K/8K"
Signed-off-by: Olof Johansson <olof@lixom.net>
Functions in the set_graph_notrace no longer subtract FTRACE_NOTRACE_DEPTH
from curr_ret_stack, as that is now implemented via the trace_recursion
flags. Access to curr_ret_stack no longer needs to worry about checking for
this. curr_ret_stack is still initialized to -1, when there's not a shadow
stack allocated.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Acked-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Joel Fernandes (Google) <joel@joelfernandes.org>
Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
- Introduce protected-clock DT binding to fix breakage on qcom sdm845-mtp
boards where the qspi clks introduced this merge window cause the
firmware on those boards to take down the system if we try to read
the clk registers
- Fix a couple off-by-one errors found by Dan Carpenter
- Handle failure in zynq fixed factor clk driver to avoid using
uninitialized data
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAlwLBpERHHNib3lkQGtl
cm5lbC5vcmcACgkQrQKIl8bklSUmVRAAuswyoavqTsj09/lhEeM1w8f+2QlnCFb2
6kUuVYmQP35u2MhuXv0sHwe1Gnnf5dL4r1d2TwCdZDTJxGIT6lbkLmeKxJzeAJzO
TgVCSNxTfwNyAAY16tFSdY3sigjQCFL+0LrKTh8ID6Ub05xz2NUZ17d0eC8WTsn1
6O66QBzCOAWvJ6LO8ktnpLpRUQAoECjKs9Vn2bnpBV+jxnuqthaD6LbK/snzNgI1
NE+CKeFjs1bFP4WiXUn7HATw+GQxmMN3MOB9KSd36OILQYA5eMYS0voJW6V/LmJv
5HImYCPc+vBhptLWflzQrbGmGV57zTH3V6OVXd0BD/tBxbIF/l56Xpv8YDC0ahe3
RklehCka/o+cF7O9/sRLwLKKNYVNJs+JOX+MxJ3Pv/ANMaeZepMtTII38IcJFKQS
aVXKbAwHvxWDI88PmdykO2gS5Nu6sdjkriQ63FdvRFL9UmnCTl3ruk/9Ww8aV04v
cwwHJlw6sHVcRnzHJidh3UAyvEY8cSD9nbS2zV+xbiw1nR3S94hTx05N4UCc2Q/6
7dRlZ9B+STni4YOnQlU0u6ApICrZEkcZk30dW7bX154x9WKbX7yusOCrpHa2Bx5b
xvdNmuiSjNjLjmi2ZR0nFF/DAhBW9dAva/keeV7IC0Gilakgp33/MvUiLPFZ0piz
5/vCWZx88FY=
=t1kp
-----END PGP SIGNATURE-----
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A few clk driver fixes this time:
- Introduce protected-clock DT binding to fix breakage on qcom
sdm845-mtp boards where the qspi clks introduced this merge window
cause the firmware on those boards to take down the system if we
try to read the clk registers
- Fix a couple off-by-one errors found by Dan Carpenter
- Handle failure in zynq fixed factor clk driver to avoid using
uninitialized data"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: zynqmp: Off by one in zynqmp_is_valid_clock()
clk: mmp: Off by one in mmp_clk_add()
clk: mvebu: Off by one bugs in cp110_of_clk_get()
arm64: dts: qcom: sdm845-mtp: Mark protected gcc clocks
clk: qcom: Support 'protected-clocks' property
dt-bindings: clk: Introduce 'protected-clocks' property
clk: zynqmp: handle fixed factor param query error
Enable the USB3 peripheral that is wired to CON2 on the Clearfog GT-8K
board.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Add DT support for the Macchiatobin Single Shot board from SolidRun,
which is similar to the Double Shot board, but does not have the
10G 3310 PHYs - the two ethernet ports are instead connected directly
to the SFP+ cages.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The ESPRESSObin board has a emmc interface available on U11: declare it
and let the bootloader enable it if the emmc is present.
[gregory.clement@bootlin.com: disable the emmc by default]
Signed-off-by: Ding Tao <miyatsu@qq.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
add the qDMA device tree nodes for LS1046A devices.
Signed-off-by: Wen He <wen.he_1@nxp.com>
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
add the qDMA device tree nodes for LS1043A devices.
Signed-off-by: Wen He <wen.he_1@nxp.com>
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
LS1088A has a 48-bit address size so make sure that the
dma-ranges property reflects this.
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The fsl-mc node should sit under the soc node, so move it to
its proper location.
Fixes: ac7c9ff741 ("arm64: dts: ls1088a: add fsl-mc hardware resource manager node")
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
LS1028A contains two ARM v8 CortexA72 processor cores
with 32 KB L1-D cache and 48 KB L1-I cache
Features summary
Two 32-bit / 64-bit ARM v8 Cortex-A72 CPUs
- Arranged as single clusters of two cores sharing a 1 MB L2 cache
- Speed Up to 1.3 GHz
- Support for cluster power-gating.
Cache coherent interconnect (CCI-400)
- Hardware-managed data coherency
- Up to 400 MHz
32-bit DDR4 SDRAM memory controller with ECC
Two PCIe 3.0 controllers
One serial ATA (SATA 3.0) controller
Two high-speed USB 3.0 controllers with integrated PHY
Following levels of DTSI/DTS files have been created for the LS1028A
SoC family:
- fsl-ls1028a.dtsi:
DTS-Include file for NXP LS1028A SoC.
- fsl-ls1028a-qds.dts:
DTS file for NXP LS1028A QDS board.
- fsl-ls1028a-rdb.dts:
DTS file for NXP LS1028A RDB board
Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Removed the wrong compatible string "snps,dw-pcie", in case
match incorrect driver.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the status property disable the PCIe, the property will be enable
by bootloader.
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
LS1012A-FRWY is an ls1012a based SoC board.
Key features of this board are Micro SD, USB 3.0,
upto 1GB DDR, UART
Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
A long running stress test on a custom board shipping an AXG SoCs and a
Realtek RTL8211F PHY revealed that after a few hours the connection
speed would drop drastically, from ~1000Mbps to ~3Mbps. At the same time
the 'macirq' (eth0) IRQ would stop being triggered at all and as
consequence the GMAC IRQs never ACKed.
After a painful investigation the problem seemed to be due to a wrong
defined IRQ type for the GMAC IRQ that should be LEVEL_HIGH instead of
EDGE_RISING.
The change in the macirq IRQ type also solved another long standing
issue affecting this SoC/PHY where EEE was causing the network
connection to die after stressing it with iperf3 (even though much
sooner). It's now possible to remove the 'eee-broken-1000t' quirk as
well.
Fixes: feb3cbea09 ("ARM64: dts: meson-gxbb-odroidc2: fix GbE tx link breakage")
Fixes: 6d28d57751 ("ARM64: dts: meson-axg: fix ethernet stability issue")
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Enable the GPIO interrupt controller for the AXG SoCs.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Now that the GPIO controller has been enabled also on AXG we can hook up
the GPIO interrupt for the PHY.
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Move from dwc3-of-simple to dwc3-qcom glue driver to
support peripheral mode which requires qscratch wrapper
programming on VBUS event.
Fixes: a4333c3a6b ("usb: dwc3: Add Qualcomm DWC3 glue driver")
Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
Tested-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch sets the msm8998 xo clock name back to xo_board. Recent
clock tree changes fixed the clock tree and the change to the xo name
is causing issues where msm8998 boards do not boot properly. Let's
change it back and leave the xo label on it.
Fixes: 634da3307b (arm64: dts: qcom: msm8998: correct xo clock name)
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Jeffrey Hugo <jhugo@codeaurora.org>
The "L" AArch64 machine constraint, which we use for the "old" value in
an LL/SC cmpxchg(), generates an immediate that is suitable for a 64-bit
logical instruction. However, for cmpxchg() operations on types smaller
than 64 bits, this constraint can result in an invalid instruction which
is correctly rejected by GAS, such as EOR W1, W1, #0xffffffff.
Whilst we could special-case the constraint based on the cmpxchg size,
it's far easier to change the constraint to "K" and put up with using
a register for large 64-bit immediates. For out-of-line LL/SC atomics,
this is all moot anyway.
Reported-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Our percpu code is a bit of an inconsistent mess:
* It rolls its own xchg(), but reuses cmpxchg_local()
* It uses various different flavours of preempt_{enable,disable}()
* It returns values even for the non-returning RmW operations
* It makes no use of LSE atomics outside of the cmpxchg() ops
* There are individual macros for different sizes of access, but these
are all funneled through a switch statement rather than dispatched
directly to the relevant case
This patch rewrites the per-cpu operations to address these shortcomings.
Whilst the new code is a lot cleaner, the big advantage is that we can
use the non-returning ST- atomic instructions when we have LSE.
Signed-off-by: Will Deacon <will.deacon@arm.com>
The CAS instructions implicitly access only the relevant bits of the "old"
argument, so there is no need for explicit masking via type-casting as
there is in the LL/SC implementation.
Move the casting into the LL/SC code and remove it altogether for the LSE
implementation.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Our atomic instructions (either LSE atomics of LDXR/STXR sequences)
natively support byte, half-word, word and double-word memory accesses
so there is no need to mask the data register prior to being stored.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Since commit 3b8c9f1cdf ("arm64: IPI each CPU after invalidating the
I-cache for kernel mappings"), a call to flush_icache_range() will use
an IPI to cross-call other online CPUs so that any stale instructions
are flushed from their pipelines. This triggers a WARN during the
hibernation resume path, where flush_icache_range() is called with
interrupts disabled and is therefore prone to deadlock:
| Disabling non-boot CPUs ...
| CPU1: shutdown
| psci: CPU1 killed.
| CPU2: shutdown
| psci: CPU2 killed.
| CPU3: shutdown
| psci: CPU3 killed.
| WARNING: CPU: 0 PID: 1 at ../kernel/smp.c:416 smp_call_function_many+0xd4/0x350
| Modules linked in:
| CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.20.0-rc4 #1
Since all secondary CPUs have been taken offline prior to invalidating
the I-cache, there's actually no need for an IPI and we can simply call
__flush_icache_range() instead.
Cc: <stable@vger.kernel.org>
Fixes: 3b8c9f1cdf ("arm64: IPI each CPU after invalidating the I-cache for kernel mappings")
Reported-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Tested-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Tested-by: James Morse <james.morse@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Now that kexec_walk_memblock() can do the crash-kernel placement itself
architectures that don't support kdump via kexe_file_load() need to
explicitly forbid it.
We don't support this on arm64 until the kernel can add the elfcorehdr
and usable-memory-range fields to the DT. Without these the crash-kernel
overwrites the previous kernel's memory during startup.
Add a check to refuse crash image loading.
Reviewed-by: Bhupesh Sharma <bhsharma@redhat.com>
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
The asm-generic/preempt.h implementation doesn't make use of the
PREEMPT_NEED_RESCHED flag, since this can interact badly with load/store
architectures which rely on the preempt_count word being unchanged across
an interrupt.
However, since we're a 64-bit architecture and the preempt count is
only 32 bits wide, we can simply pack it next to the resched flag and
load the whole thing in one go, so that a dec-and-test operation doesn't
need to load twice.
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Technically the display-hub driver could access registers via the
specified region, though it practice it will do so via the display
controllers' register regions.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Technically the display-hub driver could access registers via the
specified region, though it practice it will do so via the display
controllers' register regions.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The RTC module on the A64 was claimed to be the same as on the A31, when
in fact it is not. It is actually compatible to the H3's RTC. The A64's
RTC has some extra crypto-related registers which the H3's does not, but
the exact function of these is not clear.
This patch fixes the compatible string and clock properties to conform
to the updated bindings. The device node for the internal oscillator is
removed, as it is internalized into the RTC device. Clock references to
the IOSC and LOSC are also fixed.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The RTC module on the H3 was claimed to be the same as on the A31, when
in fact it is not. The A31 does not have an RTC external clock output,
and its internal RC oscillator's average clock rate is not in the same
range. The H5's RTC has some extra crypto-related registers compared to
the H3. Their exact functions are not clear. Also the RTC-VIO regulator
has different settings.
This patch fixes the compatible string and clock properties to conform
to the updated bindings. The device node for the internal oscillator is
removed, as it is internalized into the RTC device. Clock references to
the IOSC and LOSC are also fixed.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The CEC controller found on Tegra194 can be used to control consumer
devices using the HDMI CEC pin.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The HDA controller found on Tegra194 can be used for audio playback over
HDMI.
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The CEC controller found on Tegra186 can be used to control consumer
devices using the HDMI CEC pin.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add hstate for each supported hugepage size using arch initcall.
* no hugepage parameters
Without hugepage parameters, only a default hugepage size is
available for dynamic allocation. It's different, for example, from
x86_64 and sparc64 where all supported hugepage sizes are available.
* only default_hugepagesz= is specified and set not to HPAGE_SIZE
In spite of the fact that default_hugepagesz= is set to a valid
hugepage size, it's treated as unsupported and reverted to
HPAGE_SIZE. Such behaviour is also different from x86_64 and
sparc64.
Acked-by: Steve Capper <steve.capper@arm.com>
Reviewed-by: Tom Saeger <tom.saeger@oracle.com>
Signed-off-by: Dmitry Klochkov <dmitry.klochkov@oracle.com>
Signed-off-by: Allen Pais <allen.pais@oracle.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This is a NEON acceleration method that can improve
performance by approximately 20%. I got the following
data from the centos 7.5 on Huawei's HISI1616 chip:
[ 93.837726] xor: measuring software checksum speed
[ 93.874039] 8regs : 7123.200 MB/sec
[ 93.914038] 32regs : 7180.300 MB/sec
[ 93.954043] arm64_neon: 9856.000 MB/sec
[ 93.954047] xor: using function: arm64_neon (9856.000 MB/sec)
I believe this code can bring some optimization for
all arm64 platform. thanks for Ard Biesheuvel's suggestions.
Signed-off-by: Jackie Liu <liuyun01@kylinos.cn>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
In a way similar to ARM commit 09096f6a0e ("ARM: 7822/1: add workaround
for ambiguous C99 stdint.h types"), this patch redefines the macros that
are used in stdint.h so its definitions of uint64_t and int64_t are
compatible with those of the kernel.
This patch comes from: https://patchwork.kernel.org/patch/3540001/
Wrote by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
We mark this file as a private file and don't have to override asm/types.h
Signed-off-by: Jackie Liu <liuyun01@kylinos.cn>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
The comment about SYS_MEMBARRIER_SYNC_CORE relying on ERET being
context-synchronizing is confusing and misplaced with kpti. Given that
this is already documented under Documentation/ (see arch-support.txt
for membarrier), remove the comment altogether.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Some CPUs can speculate past an ERET instruction and potentially perform
speculative accesses to memory before processing the exception return.
Since the register state is often controlled by a lower privilege level
at the point of an ERET, this could potentially be used as part of a
side-channel attack.
This patch emits an SB sequence after each ERET so that speculation is
held up on exception return.
Signed-off-by: Will Deacon <will.deacon@arm.com>
We currently use a DSB; ISB sequence to inhibit speculation in set_fs().
Whilst this works for current CPUs, future CPUs may implement a new SB
barrier instruction which acts as an architected speculation barrier.
On CPUs that support it, patch in an SB; NOP sequence over the DSB; ISB
sequence and advertise the presence of the new instruction to userspace.
Signed-off-by: Will Deacon <will.deacon@arm.com>
setup_dtb() is a little difficult to read. This is largely because it
duplicates the FDT -> Linux errno conversion for every intermediate
return value, but also because of silly cosmetic things like naming
and formatting.
Given that this is all brand new, refactor the function to get us off on
the right foot.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Adding "kaslr-seed" to dtb enables triggering kaslr, or kernel virtual
address randomization, at secondary kernel boot. We always do this as
it will have no harm on kaslr-incapable kernel.
We don't have any "switch" to turn off this feature directly, but still
can suppress it by passing "nokaslr" as a kernel boot argument.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
[will: Use rng_is_initialized()]
Signed-off-by: Will Deacon <will.deacon@arm.com>
With this patch, kernel verification can be done without IMA security
subsystem enabled. Turn on CONFIG_KEXEC_VERIFY_SIG instead.
On x86, a signature is embedded into a PE file (Microsoft's format) header
of binary. Since arm64's "Image" can also be seen as a PE file as far as
CONFIG_EFI is enabled, we adopt this format for kernel signing.
You can create a signed kernel image with:
$ sbsign --key ${KEY} --cert ${CERT} Image
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
[will: removed useless pr_debug()]
Signed-off-by: Will Deacon <will.deacon@arm.com>
We use a stop_machine call for each available capability to
enable it on all the CPUs available at boot time. Instead
we could batch the cpu_enable callbacks to a single stop_machine()
call to save us some time.
Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com>
Tested-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Use the sorted list of capability entries for the detection and
verification.
Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com>
Tested-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Make use of the sorted capability list to access the capability
entry in this_cpu_has_cap() to avoid iterating over the two
tables.
Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com>
Tested-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
We maintain two separate tables of capabilities, errata and features,
which decide the system capabilities. We iterate over each of these
tables for various operations (e.g, detection, verification etc.).
We do not have a way to map a system "capability" to its entry,
(i.e, cap -> struct arm64_cpu_capabilities) which is needed for
this_cpu_has_cap(). So we iterate over the table one by one to
find the entry and then do the operation. Also, this prevents
us from optimizing the way we "enable" the capabilities on the
CPUs, where we now issue a stop_machine() for each available
capability.
One solution is to merge the two tables into a single table,
sorted by the capability. But this is has the following
disadvantages:
- We loose the "classification" of an errata vs. feature
- It is quite easy to make a mistake when adding an entry,
unless we sort the table at runtime.
So we maintain a list of pointers to the capability entry, sorted
by the "cap number" in a separate array, initialized at boot time.
The only restriction is that we can have one "entry" per capability.
While at it, remove the duplicate declaration of arm64_errata table.
Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com>
Tested-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
These days architectures are mostly out of the business of dealing with
struct scatterlist at all, unless they have architecture specific iommu
drivers. Replace the ARCH_HAS_SG_CHAIN symbol with a ARCH_NO_SG_CHAIN
one only enabled for architectures with horrible legacy iommu drivers
like alpha and parisc, and conditionally for arm which wants to keep it
disable for legacy platforms.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Return DMA_MAPPING_ERROR instead of 0 on a dma mapping failure and let
the core dma-mapping code handle the rest.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Linus Torvalds <torvalds@linux-foundation.org>
Just return DMA_MAPPING_ERROR from __dummy_map_page and let the core
dma-mapping code handle the rest.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Linus Torvalds <torvalds@linux-foundation.org>
On arm64, purgatory would do almost nothing. So just invoke secondary
kernel directly by jumping into its entry code.
While, in this case, cpu_soft_restart() must be called with dtb address
in the fifth argument, the behavior still stays compatible with kexec_load
case as long as the argument is null.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: James Morse <james.morse@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This patch provides kexec_file_ops for "Image"-format kernel. In this
implementation, a binary is always loaded with a fixed offset identified
in text_offset field of its header.
Regarding signature verification for trusted boot, this patch doesn't
contains CONFIG_KEXEC_VERIFY_SIG support, which is to be added later
in this series, but file-attribute-based verification is still a viable
option by enabling IMA security subsystem.
You can sign(label) a to-be-kexec'ed kernel image on target file system
with:
$ evmctl ima_sign --key /path/to/private_key.pem Image
On live system, you must have IMA enforced with, at least, the following
security policy:
"appraise func=KEXEC_KERNEL_CHECK appraise_type=imasig"
See more details about IMA here:
https://sourceforge.net/p/linux-ima/wiki/Home/
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
load_other_segments() is expected to allocate and place all the necessary
memory segments other than kernel, including initrd and device-tree
blob (and elf core header for crash).
While most of the code was borrowed from kexec-tools' counterpart,
users may not be allowed to specify dtb explicitly, instead, the dtb
presented by the original boot loader is reused.
arch_kimage_kernel_post_load_cleanup() is responsible for freeing arm64-
specific data allocated in load_other_segments().
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Those helper functions for MMFR0 register will be used later by kexec_file
loader.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
