Commit Graph

843336 Commits

Author SHA1 Message Date
Hawking Zhang
03c9963f47 drm/amdgpu: add umc v6_1_1 IP headers
the change introduces IP headers for unified memory controller (umc)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-31 14:49:10 -05:00
Hawking Zhang
245219a660 drm/amdgpu: add rsmu v_0_0_2 ip headers
remote smu (rsmu) is a sub-block used as ip register interface,
error handling, reset generation.etc

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-31 14:49:03 -05:00
Hawking Zhang
9e585a523b drm/amdgpu: add amdgpu_umc_functions structure
This is common structure as UMC callback function

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-31 14:48:57 -05:00
Hawking Zhang
6501a77170 drm/amdgpu: init RSMU and UMC ip base address for vega20
the driver needs to program RSMU and UMC registers to
support vega20 RAS feature

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-31 14:48:51 -05:00
Hawking Zhang
7af25d5b7e drm/amdgpu: move some ras data structure to amdgpu_ras.h
These are common structures that can be included by IP specific
source files

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-31 14:48:32 -05:00
Alex Deucher
fa1884f9d8 drm/amdgpu: drop drmP.h from vcn_v2_5.c
Unused.

Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-31 14:33:41 -05:00
Alex Deucher
9a2ffeb525 drm/amdgpu: drop drmP.h from vcn_v2_0.c
And fix the fallout.

Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-31 14:33:36 -05:00
Alex Deucher
75589f496d drm/amdgpu: drop drmP.h from sdma_v5_0.c
And fix the fallout.

Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-31 14:33:31 -05:00
Alex Deucher
e9eea90247 drm/amdgpu: drop drmP.h from nv.c
And fix up the fallout.

Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-31 14:33:26 -05:00
Alex Deucher
b23b2e9e49 drm/amdgpu: drop drmP.h from navi10_ih.c
And fix the fallout.

Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-31 14:33:21 -05:00
Alex Deucher
0a069bbe13 drm/amdgpu: drop drmP.h in gfx_v10_0.c
And fix the fallout.

Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-31 14:33:16 -05:00
Alex Deucher
3b90f6ecdf drm/amdgpu: drop drmP.h from amdgpu_amdkfd_gfx_v10.c
Unused.

Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-31 14:33:10 -05:00
Alex Deucher
32978d8cfd drm/amdgpu: drop drmP.h in amdgpu_amdkfd_arcturus.c
Unused.

Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-31 14:32:56 -05:00
Evan Quan
59de58f84f drm/amd/powerplay: determine the features to enable by pptable only
Per current logics, the features to enable are determined together
by driver and pptable. This is not efficient in co-debug with
firmware team.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:35 -05:00
Hawking Zhang
861324983d drm/amdgpu: correct irq type used for sdma ecc
we should pass irq type, instead of irq client id,
to irq_get/put interface

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:35 -05:00
Evan Quan
b4af964e75 drm/amd/powerplay: make power limit retrieval as asic specific
The power limit retrieval should be done per asic. Since we may
need to lookup in the pptable and that's really asic specific.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:35 -05:00
Evan Quan
1f23cadbe0 drm/amd/powerplay: correct arcturus current clock level calculation
There may be 1Mhz delta between target and actual frequency. That
should be taken into consideration for current level check.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:35 -05:00
Evan Quan
60d435b73d drm/amd/powerplay: support UMD PSTATE settings on arcturus
Enable arcturus UMD PSTATE support.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:35 -05:00
Evan Quan
4bf76e60b9 drm/amd/powerplay: fix arcturus real-time clock frequency retrieval
Make sure we can still get the accurate gfxclk/uclk/socclk frequency
even on dpm disabled.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:34 -05:00
Kevin Wang
790ef68afc drm/amd/powerplay: remove redundancy debug log in smu
remove redundacy debug log in smu.
eg:
[ 6897.969447] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6897.969448] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6897.969448] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6899.024114] amdgpu: [powerplay] Unsupported SMU message: 38
[ 6899.024151] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6899.024151] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6899.024152] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6900.078296] amdgpu: [powerplay] Unsupported SMU message: 38
[ 6900.078332] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6900.078332] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6900.078333] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6901.133230] amdgpu: [powerplay] Unsupported SMU message: 38

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:34 -05:00
Evan Quan
8a856ced35 drm/amd/powerplay: correct the bitmask used in arcturus
Those bitmask prefixed by "SMU_" should be used.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:34 -05:00
Evan Quan
55bf7e6243 drm/amd/powerplay: add missing arcturus feature maps
Add missing feature maps for arcturus.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:34 -05:00
Evan Quan
d427cf8f7f drm/amd/powerplay: support fan speed retrieval on arcturus
Support arcturus fan speed retrieval.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:34 -05:00
Evan Quan
631807f091 drm/amd/powerplay: support real-time clock retrieval on arcturus
Enable arcturus real-time clock retrieval.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:34 -05:00
Evan Quan
ba74c8bf88 drm/amd/powerplay: support sensor reading on arcturus
Support sensor reading for gpu loading, power and
temperatures.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:34 -05:00
Evan Quan
832a7062a0 drm/amd/powerplay: init arcturus SMU metrics table on bootup
Initialize arcturus SMU metrics table.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:34 -05:00
Evan Quan
1f96ecef6f drm/amd/powerplay: correct UVD/VCE/VCN power status retrieval
VCN should be used for Vega20 later ASICs while UVD and VCE
are for previous ASICs.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:34 -05:00
Evan Quan
5fa790f6c9 drm/amd/powerplay: correct Navi10 VCN powergate control (v2)
No VCN DPM bit check as that's different from VCN PG. Also
no extra check for possible double enablement/disablement
as that's already done by VCN.

v2: check return value of smu_feature_set_enabled

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:34 -05:00
Evan Quan
bf2bf52383 drm/amd/powerplay: support VCN powergate status retrieval for SW SMU
Commonly used for VCN powergate status retrieval for SW SMU.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:34 -05:00
Evan Quan
ab9e314886 drm/amd/powerplay: support VCN powergate status retrieval on Raven
Enable VCN powergate status report on Raven.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:34 -05:00
Evan Quan
9829e3d89b drm/amd/powerplay: add new sensor type for VCN powergate status
VCN is widely used in new ASICs and different from tranditional
UVD and VCE.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:34 -05:00
Le Ma
7d0e6329df drm/amdgpu: update more sdma instances irq support
Update for sdma ras ecc_irq and other minors.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:34 -05:00
Le Ma
9d4d7236ef drm/amd/include: adjust base offset of SMUIO and THM for Arcturus
Arcturus has different _BASE_IDX value in some HWIP_offset.h. To make source
files like smu_v11_0.c and soc15.c that include HWIP_offset.h of Vega20
reusable for Arcturus, align this base offset with Vega20.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:34 -05:00
Evan Quan
3ff101b8ab drm/amd/powerplay: hold on the arcturus gfx dpm support in driver
As for now, only "Prefetcher" is guarded to be working from
SMU firmware.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:34 -05:00
Evan Quan
7c16d24abe drm/amdgpu: correct VCN powergate routine for acturus
Arcturus VCN should powergate in the way as Navi.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:34 -05:00
Evan Quan
fe089e1dd7 drm/amd/powerplay: enable arcturus powerplay
Arcturus powerplay is ready to use.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:33 -05:00
Evan Quan
cca4fafc09 drm/amd/powerplay: initialize arcturus MP1 and THM base address
Initialize base address for those IPs which are used in powerplay.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:33 -05:00
Evan Quan
22e1831734 drm/amd/powerplay: enable SW SMU routine support for arcturus
Enable arcturus SW SMU routines.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:33 -05:00
Evan Quan
a94235af11 drm/amd/powerplay: update arcturus_ppt.c/h V3
Arcturus ASIC specific powerplay interfaces.

V2: correct SMU msg naming
    drop unnecessary debugs

V3: rebase (Alex)

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:33 -05:00
Evan Quan
c8893d5ce7 drm/amd/powerplay: update arcturus_ppsmc.h
Correct header and fix typo.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:33 -05:00
Evan Quan
22808306f2 drm/amd/powerplay: update smu11_driver_if_arcturus.h
It guides how driver should interface with SMU in arcturus.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:33 -05:00
Evan Quan
7c8bcaf408 drm/amd/powerplay: add SW SMU interface for dumping pptable out (v2)
This is especially useful in early bring up phase.

v2: disabled by default (Alex)

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:33 -05:00
Evan Quan
4c35e77865 drm/amd/powerplay: add smcdpminfo table v4_6 support
New smcdpminfo table used in arcturus.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:33 -05:00
Jay Cornwall
1faa3b8054 drm/amdkfd: Save/restore vcc on gfx10
VCC moved out of user SGPR allocation in gfx10. It's now stored
in SGPRs 106-107.

Also fixes incorrect SGPR read offsets.

Cc: Shaoyun Liu <shaoyun.liu@amd.com>
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: shaoyunl <shaoyun.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:33 -05:00
Jay Cornwall
f9e346aba1 drm/amdkfd: Save/restore flat_scratch_lo/hi on gfx10
These moved from SGPRs in gfx9 to HWREG in gfx10.

Cc: Shaoyun Liu <shaoyun.liu@amd.com>
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: shaoyunl <shaoyun.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:33 -05:00
Jay Cornwall
7ce55e0b6f drm/amdkfd: Fix gfx10 wave64 VGPR context restore
Copy/paste error, first 4 VGPRs are separated by 64 dwords (256 bytes).

Cc: Shaoyun Liu <shaoyun.liu@amd.com>
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: shaoyunl <shaoyun.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:33 -05:00
Nicholas Kazlauskas
f16d523f9d drm/amd/display: Support uclk switching for DCN2
[Why]
We were previously forcing the uclk for every state to max and reducing
the switch time to prevent uclk switching from occuring. This workaround
was previously needed in order to avoid hangs + underflow under certain
display configurations.

Now that DC has the proper fix complete we can drop the hacks and
improve power for most display configurations.

[How]
We still need the function pointers hooked up to grab the real uclk
states from pplib. The rest of the prior hack can be reverted.

The key requirements here are really just DC support, updated firmware,
and support for disabling p-state support when needed in pplib/smu.

When these requirements are met uclk switching works without underflow
or hangs.

Fixes: 02316e963a ("drm/amd/display: Force uclk to max for every state")

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:33 -05:00
Nicholas Kazlauskas
fb6959ae50 drm/amd/display: Embed DCN2 SOC bounding box
[Why]
In order to support uclk switching on NV10 the SOC bounding box
needs to be updated.

[How]
We currently read the constants from the gpu info FW, but supporting
workarounds in DC for different versions of the FW adds additional
complexity to the codebase.

NV10 has been released so it's cleanest to keep the bounding box and
source code in sync by embedding the bounding box like we do for
other ASICs.

Fixes: 02316e963a ("drm/amd/display: Force uclk to max for every state")

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:33 -05:00
Wang Xiayang
1a2c29bce0 drm/amdgpu: fix a potential information leaking bug
Coccinelle reports a path that the array "data" is never initialized.
The path skips the checks in the conditional branches when either
of callback functions, read_wave_vgprs and read_wave_sgprs, is not
registered. Later, the uninitialized "data" array is read
in the while-loop below and passed to put_user().

Fix the path by allocating the array with kcalloc().

The patch is simplier than adding a fall-back branch that explicitly
calls memset(data, 0, ...). Also it does not need the multiplication
1024*sizeof(*data) as the size parameter for memset() though there is
no risk of integer overflow.

Signed-off-by: Wang Xiayang <xywang.sjtu@sjtu.edu.cn>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:33 -05:00
Christian König
6494120695 drm/amdgpu: fix error handling in amdgpu_cs_process_fence_dep
We always need to drop the ctx reference and should check
for errors first and then dereference the fence pointer.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30 23:48:33 -05:00