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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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mmc: sh_mmcif: process requests asynchronously
This patch converts the sh_mmcif MMC host driver to process requests asynchronously instead of waiting in its .request() method for completion. This is achieved by using threaded IRQs. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Chris Ball <cjb@laptop.org>
This commit is contained in:
Guennadi Liakhovetski
Chris Ball
parent
ee4b88879f
commit
f985da17f4
@ -16,6 +16,32 @@
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*
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*/
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/*
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* The MMCIF driver is now processing MMC requests asynchronously, according
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* to the Linux MMC API requirement.
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*
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* The MMCIF driver processes MMC requests in up to 3 stages: command, optional
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* data, and optional stop. To achieve asynchronous processing each of these
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* stages is split into two halves: a top and a bottom half. The top half
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* initialises the hardware, installs a timeout handler to handle completion
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* timeouts, and returns. In case of the command stage this immediately returns
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* control to the caller, leaving all further processing to run asynchronously.
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* All further request processing is performed by the bottom halves.
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*
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* The bottom half further consists of a "hard" IRQ handler, an IRQ handler
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* thread, a DMA completion callback, if DMA is used, a timeout work, and
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* request- and stage-specific handler methods.
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*
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* Each bottom half run begins with either a hardware interrupt, a DMA callback
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* invocation, or a timeout work run. In case of an error or a successful
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* processing completion, the MMC core is informed and the request processing is
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* finished. In case processing has to continue, i.e., if data has to be read
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* from or written to the card, or if a stop command has to be sent, the next
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* top half is called, which performs the necessary hardware handling and
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* reschedules the timeout work. This returns the driver state machine into the
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* bottom half waiting state.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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@ -168,9 +194,22 @@ enum mmcif_state {
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STATE_IOS,
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};
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enum mmcif_wait_for {
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MMCIF_WAIT_FOR_REQUEST,
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MMCIF_WAIT_FOR_CMD,
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MMCIF_WAIT_FOR_MREAD,
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MMCIF_WAIT_FOR_MWRITE,
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MMCIF_WAIT_FOR_READ,
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MMCIF_WAIT_FOR_WRITE,
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MMCIF_WAIT_FOR_READ_END,
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MMCIF_WAIT_FOR_WRITE_END,
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MMCIF_WAIT_FOR_STOP,
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};
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struct sh_mmcif_host {
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struct mmc_host *mmc;
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struct mmc_data *data;
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struct mmc_request *mrq;
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struct platform_device *pd;
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struct sh_dmae_slave dma_slave_tx;
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struct sh_dmae_slave dma_slave_rx;
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@ -178,11 +217,17 @@ struct sh_mmcif_host {
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unsigned int clk;
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int bus_width;
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bool sd_error;
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bool dying;
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long timeout;
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void __iomem *addr;
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struct completion intr_wait;
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u32 *pio_ptr;
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spinlock_t lock; /* protect sh_mmcif_host::state */
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enum mmcif_state state;
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enum mmcif_wait_for wait_for;
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struct delayed_work timeout_work;
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size_t blocksize;
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int sg_idx;
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int sg_blkidx;
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bool power;
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bool card_present;
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@ -468,125 +513,183 @@ static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
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return ret;
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}
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static int sh_mmcif_single_read(struct sh_mmcif_host *host,
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struct mmc_request *mrq)
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static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p)
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{
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struct mmc_data *data = mrq->data;
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long time;
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u32 blocksize, i, *p = sg_virt(data->sg);
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struct mmc_data *data = host->mrq->data;
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host->sg_blkidx += host->blocksize;
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/* data->sg->length must be a multiple of host->blocksize? */
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BUG_ON(host->sg_blkidx > data->sg->length);
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if (host->sg_blkidx == data->sg->length) {
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host->sg_blkidx = 0;
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if (++host->sg_idx < data->sg_len)
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host->pio_ptr = sg_virt(++data->sg);
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} else {
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host->pio_ptr = p;
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}
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if (host->sg_idx == data->sg_len)
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return false;
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return true;
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}
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static void sh_mmcif_single_read(struct sh_mmcif_host *host,
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struct mmc_request *mrq)
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{
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host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
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BLOCK_SIZE_MASK) + 3;
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host->wait_for = MMCIF_WAIT_FOR_READ;
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schedule_delayed_work(&host->timeout_work, host->timeout);
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/* buf read enable */
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sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
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time = wait_for_completion_interruptible_timeout(&host->intr_wait,
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host->timeout);
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if (time <= 0 || host->sd_error)
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return sh_mmcif_error_manage(host);
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}
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blocksize = (BLOCK_SIZE_MASK &
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sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
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for (i = 0; i < blocksize / 4; i++)
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static bool sh_mmcif_read_block(struct sh_mmcif_host *host)
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{
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struct mmc_data *data = host->mrq->data;
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u32 *p = sg_virt(data->sg);
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int i;
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if (host->sd_error) {
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data->error = sh_mmcif_error_manage(host);
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return false;
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}
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for (i = 0; i < host->blocksize / 4; i++)
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*p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
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/* buffer read end */
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sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
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time = wait_for_completion_interruptible_timeout(&host->intr_wait,
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host->timeout);
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if (time <= 0 || host->sd_error)
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return sh_mmcif_error_manage(host);
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host->wait_for = MMCIF_WAIT_FOR_READ_END;
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return 0;
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return true;
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}
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static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
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struct mmc_request *mrq)
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static void sh_mmcif_multi_read(struct sh_mmcif_host *host,
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struct mmc_request *mrq)
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{
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struct mmc_data *data = mrq->data;
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long time;
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u32 blocksize, i, j, sec, *p;
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blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
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MMCIF_CE_BLOCK_SET);
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for (j = 0; j < data->sg_len; j++) {
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p = sg_virt(data->sg);
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for (sec = 0; sec < data->sg->length / blocksize; sec++) {
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sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
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/* buf read enable */
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time = wait_for_completion_interruptible_timeout(&host->intr_wait,
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host->timeout);
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if (!data->sg_len || !data->sg->length)
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return;
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if (time <= 0 || host->sd_error)
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return sh_mmcif_error_manage(host);
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host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
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BLOCK_SIZE_MASK;
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for (i = 0; i < blocksize / 4; i++)
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*p++ = sh_mmcif_readl(host->addr,
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MMCIF_CE_DATA);
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}
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if (j < data->sg_len - 1)
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data->sg++;
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host->wait_for = MMCIF_WAIT_FOR_MREAD;
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host->sg_idx = 0;
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host->sg_blkidx = 0;
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host->pio_ptr = sg_virt(data->sg);
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schedule_delayed_work(&host->timeout_work, host->timeout);
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sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
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}
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static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)
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{
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struct mmc_data *data = host->mrq->data;
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u32 *p = host->pio_ptr;
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int i;
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if (host->sd_error) {
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data->error = sh_mmcif_error_manage(host);
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return false;
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}
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return 0;
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BUG_ON(!data->sg->length);
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for (i = 0; i < host->blocksize / 4; i++)
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*p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
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if (!sh_mmcif_next_block(host, p))
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return false;
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schedule_delayed_work(&host->timeout_work, host->timeout);
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sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
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return true;
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}
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static int sh_mmcif_single_write(struct sh_mmcif_host *host,
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static void sh_mmcif_single_write(struct sh_mmcif_host *host,
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struct mmc_request *mrq)
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{
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struct mmc_data *data = mrq->data;
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long time;
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u32 blocksize, i, *p = sg_virt(data->sg);
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host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
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BLOCK_SIZE_MASK) + 3;
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sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
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host->wait_for = MMCIF_WAIT_FOR_WRITE;
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schedule_delayed_work(&host->timeout_work, host->timeout);
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/* buf write enable */
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time = wait_for_completion_interruptible_timeout(&host->intr_wait,
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host->timeout);
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if (time <= 0 || host->sd_error)
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return sh_mmcif_error_manage(host);
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sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
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}
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blocksize = (BLOCK_SIZE_MASK &
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sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
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for (i = 0; i < blocksize / 4; i++)
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static bool sh_mmcif_write_block(struct sh_mmcif_host *host)
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{
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struct mmc_data *data = host->mrq->data;
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u32 *p = sg_virt(data->sg);
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int i;
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if (host->sd_error) {
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data->error = sh_mmcif_error_manage(host);
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return false;
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}
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for (i = 0; i < host->blocksize / 4; i++)
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sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
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/* buffer write end */
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sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
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host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
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time = wait_for_completion_interruptible_timeout(&host->intr_wait,
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host->timeout);
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if (time <= 0 || host->sd_error)
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return sh_mmcif_error_manage(host);
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return 0;
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return true;
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}
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static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
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struct mmc_request *mrq)
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static void sh_mmcif_multi_write(struct sh_mmcif_host *host,
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struct mmc_request *mrq)
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{
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struct mmc_data *data = mrq->data;
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long time;
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u32 i, sec, j, blocksize, *p;
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blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
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MMCIF_CE_BLOCK_SET);
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if (!data->sg_len || !data->sg->length)
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return;
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for (j = 0; j < data->sg_len; j++) {
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p = sg_virt(data->sg);
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for (sec = 0; sec < data->sg->length / blocksize; sec++) {
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sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
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/* buf write enable*/
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time = wait_for_completion_interruptible_timeout(&host->intr_wait,
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host->timeout);
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host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
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BLOCK_SIZE_MASK;
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if (time <= 0 || host->sd_error)
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return sh_mmcif_error_manage(host);
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host->wait_for = MMCIF_WAIT_FOR_MWRITE;
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host->sg_idx = 0;
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host->sg_blkidx = 0;
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host->pio_ptr = sg_virt(data->sg);
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schedule_delayed_work(&host->timeout_work, host->timeout);
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sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
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}
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for (i = 0; i < blocksize / 4; i++)
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sh_mmcif_writel(host->addr,
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MMCIF_CE_DATA, *p++);
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}
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if (j < data->sg_len - 1)
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data->sg++;
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static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)
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{
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struct mmc_data *data = host->mrq->data;
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u32 *p = host->pio_ptr;
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int i;
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if (host->sd_error) {
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data->error = sh_mmcif_error_manage(host);
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return false;
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}
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return 0;
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BUG_ON(!data->sg->length);
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for (i = 0; i < host->blocksize / 4; i++)
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sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
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if (!sh_mmcif_next_block(host, p))
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return false;
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schedule_delayed_work(&host->timeout_work, host->timeout);
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sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
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return true;
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}
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static void sh_mmcif_get_response(struct sh_mmcif_host *host,
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@ -683,18 +786,22 @@ static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
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}
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static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
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struct mmc_request *mrq, u32 opc)
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struct mmc_request *mrq, u32 opc)
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{
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switch (opc) {
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case MMC_READ_MULTIPLE_BLOCK:
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return sh_mmcif_multi_read(host, mrq);
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sh_mmcif_multi_read(host, mrq);
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return 0;
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case MMC_WRITE_MULTIPLE_BLOCK:
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return sh_mmcif_multi_write(host, mrq);
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sh_mmcif_multi_write(host, mrq);
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return 0;
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case MMC_WRITE_BLOCK:
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return sh_mmcif_single_write(host, mrq);
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sh_mmcif_single_write(host, mrq);
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return 0;
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case MMC_READ_SINGLE_BLOCK:
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case MMC_SEND_EXT_CSD:
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return sh_mmcif_single_read(host, mrq);
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sh_mmcif_single_read(host, mrq);
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return 0;
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default:
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dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
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return -EINVAL;
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@ -705,9 +812,8 @@ static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
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struct mmc_request *mrq)
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{
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struct mmc_command *cmd = mrq->cmd;
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long time;
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int ret = 0;
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u32 mask, opc = cmd->opcode;
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u32 opc = cmd->opcode;
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u32 mask;
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switch (opc) {
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/* response busy check */
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@ -738,62 +844,14 @@ static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
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/* set cmd */
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sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
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time = wait_for_completion_interruptible_timeout(&host->intr_wait,
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host->timeout);
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if (time <= 0) {
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cmd->error = sh_mmcif_error_manage(host);
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return;
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}
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if (host->sd_error) {
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switch (cmd->opcode) {
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case MMC_ALL_SEND_CID:
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case MMC_SELECT_CARD:
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case MMC_APP_CMD:
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cmd->error = -ETIMEDOUT;
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break;
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default:
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dev_dbg(&host->pd->dev, "Cmd(d'%d) err\n",
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cmd->opcode);
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cmd->error = sh_mmcif_error_manage(host);
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break;
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}
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host->sd_error = false;
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return;
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}
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if (!(cmd->flags & MMC_RSP_PRESENT)) {
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cmd->error = 0;
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return;
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}
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sh_mmcif_get_response(host, cmd);
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if (host->data) {
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if (!host->dma_active) {
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ret = sh_mmcif_data_trans(host, mrq, cmd->opcode);
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} else {
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long time =
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wait_for_completion_interruptible_timeout(&host->dma_complete,
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host->timeout);
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if (!time)
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ret = -ETIMEDOUT;
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else if (time < 0)
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ret = time;
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sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
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BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
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host->dma_active = false;
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}
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if (ret < 0)
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mrq->data->bytes_xfered = 0;
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else
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mrq->data->bytes_xfered =
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mrq->data->blocks * mrq->data->blksz;
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}
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cmd->error = ret;
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host->wait_for = MMCIF_WAIT_FOR_CMD;
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schedule_delayed_work(&host->timeout_work, host->timeout);
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}
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static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
|
||||
struct mmc_request *mrq)
|
||||
{
|
||||
struct mmc_command *cmd = mrq->stop;
|
||||
long time;
|
||||
|
||||
if (mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK)
|
||||
sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
|
||||
@ -805,14 +863,8 @@ static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
|
||||
return;
|
||||
}
|
||||
|
||||
time = wait_for_completion_interruptible_timeout(&host->intr_wait,
|
||||
host->timeout);
|
||||
if (time <= 0 || host->sd_error) {
|
||||
cmd->error = sh_mmcif_error_manage(host);
|
||||
return;
|
||||
}
|
||||
sh_mmcif_get_cmd12response(host, cmd);
|
||||
cmd->error = 0;
|
||||
host->wait_for = MMCIF_WAIT_FOR_STOP;
|
||||
schedule_delayed_work(&host->timeout_work, host->timeout);
|
||||
}
|
||||
|
||||
static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
||||
@ -851,23 +903,11 @@ static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
||||
default:
|
||||
break;
|
||||
}
|
||||
host->data = mrq->data;
|
||||
if (mrq->data) {
|
||||
if (mrq->data->flags & MMC_DATA_READ) {
|
||||
if (host->chan_rx)
|
||||
sh_mmcif_start_dma_rx(host);
|
||||
} else {
|
||||
if (host->chan_tx)
|
||||
sh_mmcif_start_dma_tx(host);
|
||||
}
|
||||
}
|
||||
sh_mmcif_start_cmd(host, mrq);
|
||||
host->data = NULL;
|
||||
|
||||
if (!mrq->cmd->error && mrq->stop)
|
||||
sh_mmcif_stop_cmd(host, mrq);
|
||||
host->state = STATE_IDLE;
|
||||
mmc_request_done(mmc, mrq);
|
||||
host->mrq = mrq;
|
||||
host->data = mrq->data;
|
||||
|
||||
sh_mmcif_start_cmd(host, mrq);
|
||||
}
|
||||
|
||||
static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
||||
@ -942,6 +982,157 @@ static struct mmc_host_ops sh_mmcif_ops = {
|
||||
.get_cd = sh_mmcif_get_cd,
|
||||
};
|
||||
|
||||
static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)
|
||||
{
|
||||
struct mmc_command *cmd = host->mrq->cmd;
|
||||
long time;
|
||||
|
||||
if (host->sd_error) {
|
||||
switch (cmd->opcode) {
|
||||
case MMC_ALL_SEND_CID:
|
||||
case MMC_SELECT_CARD:
|
||||
case MMC_APP_CMD:
|
||||
cmd->error = -ETIMEDOUT;
|
||||
host->sd_error = false;
|
||||
break;
|
||||
default:
|
||||
cmd->error = sh_mmcif_error_manage(host);
|
||||
dev_dbg(&host->pd->dev, "Cmd(d'%d) error %d\n",
|
||||
cmd->opcode, cmd->error);
|
||||
break;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
if (!(cmd->flags & MMC_RSP_PRESENT)) {
|
||||
cmd->error = 0;
|
||||
return false;
|
||||
}
|
||||
|
||||
sh_mmcif_get_response(host, cmd);
|
||||
|
||||
if (!host->data)
|
||||
return false;
|
||||
|
||||
if (host->mrq->data->flags & MMC_DATA_READ) {
|
||||
if (host->chan_rx)
|
||||
sh_mmcif_start_dma_rx(host);
|
||||
} else {
|
||||
if (host->chan_tx)
|
||||
sh_mmcif_start_dma_tx(host);
|
||||
}
|
||||
|
||||
if (!host->dma_active) {
|
||||
host->data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);
|
||||
if (!host->data->error)
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Running in the IRQ thread, can sleep */
|
||||
time = wait_for_completion_interruptible_timeout(&host->dma_complete,
|
||||
host->timeout);
|
||||
if (host->sd_error) {
|
||||
dev_err(host->mmc->parent,
|
||||
"Error IRQ while waiting for DMA completion!\n");
|
||||
/* Woken up by an error IRQ: abort DMA */
|
||||
if (host->data->flags & MMC_DATA_READ)
|
||||
dmaengine_terminate_all(host->chan_rx);
|
||||
else
|
||||
dmaengine_terminate_all(host->chan_tx);
|
||||
host->data->error = sh_mmcif_error_manage(host);
|
||||
} else if (!time) {
|
||||
host->data->error = -ETIMEDOUT;
|
||||
} else if (time < 0) {
|
||||
host->data->error = time;
|
||||
}
|
||||
sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
|
||||
BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
|
||||
host->dma_active = false;
|
||||
|
||||
if (host->data->error)
|
||||
host->data->bytes_xfered = 0;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
|
||||
{
|
||||
struct sh_mmcif_host *host = dev_id;
|
||||
struct mmc_request *mrq = host->mrq;
|
||||
|
||||
cancel_delayed_work_sync(&host->timeout_work);
|
||||
|
||||
/*
|
||||
* All handlers return true, if processing continues, and false, if the
|
||||
* request has to be completed - successfully or not
|
||||
*/
|
||||
switch (host->wait_for) {
|
||||
case MMCIF_WAIT_FOR_REQUEST:
|
||||
/* We're too late, the timeout has already kicked in */
|
||||
return IRQ_HANDLED;
|
||||
case MMCIF_WAIT_FOR_CMD:
|
||||
if (sh_mmcif_end_cmd(host))
|
||||
/* Wait for data */
|
||||
return IRQ_HANDLED;
|
||||
break;
|
||||
case MMCIF_WAIT_FOR_MREAD:
|
||||
if (sh_mmcif_mread_block(host))
|
||||
/* Wait for more data */
|
||||
return IRQ_HANDLED;
|
||||
break;
|
||||
case MMCIF_WAIT_FOR_READ:
|
||||
if (sh_mmcif_read_block(host))
|
||||
/* Wait for data end */
|
||||
return IRQ_HANDLED;
|
||||
break;
|
||||
case MMCIF_WAIT_FOR_MWRITE:
|
||||
if (sh_mmcif_mwrite_block(host))
|
||||
/* Wait data to write */
|
||||
return IRQ_HANDLED;
|
||||
break;
|
||||
case MMCIF_WAIT_FOR_WRITE:
|
||||
if (sh_mmcif_write_block(host))
|
||||
/* Wait for data end */
|
||||
return IRQ_HANDLED;
|
||||
break;
|
||||
case MMCIF_WAIT_FOR_STOP:
|
||||
if (host->sd_error) {
|
||||
mrq->stop->error = sh_mmcif_error_manage(host);
|
||||
break;
|
||||
}
|
||||
sh_mmcif_get_cmd12response(host, mrq->stop);
|
||||
mrq->stop->error = 0;
|
||||
break;
|
||||
case MMCIF_WAIT_FOR_READ_END:
|
||||
case MMCIF_WAIT_FOR_WRITE_END:
|
||||
if (host->sd_error)
|
||||
mrq->data->error = sh_mmcif_error_manage(host);
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
|
||||
if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
|
||||
host->data = NULL;
|
||||
|
||||
if (!mrq->cmd->error && mrq->data && !mrq->data->error)
|
||||
mrq->data->bytes_xfered =
|
||||
mrq->data->blocks * mrq->data->blksz;
|
||||
|
||||
if (mrq->stop && !mrq->cmd->error && (!mrq->data || !mrq->data->error)) {
|
||||
sh_mmcif_stop_cmd(host, mrq);
|
||||
if (!mrq->stop->error)
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
}
|
||||
|
||||
host->wait_for = MMCIF_WAIT_FOR_REQUEST;
|
||||
host->state = STATE_IDLE;
|
||||
mmc_request_done(host->mmc, mrq);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
|
||||
{
|
||||
struct sh_mmcif_host *host = dev_id;
|
||||
@ -993,14 +1184,58 @@ static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
|
||||
host->sd_error = true;
|
||||
dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
|
||||
}
|
||||
if (state & ~(INT_CMD12RBE | INT_CMD12CRE))
|
||||
complete(&host->intr_wait);
|
||||
else
|
||||
if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {
|
||||
if (!host->dma_active)
|
||||
return IRQ_WAKE_THREAD;
|
||||
else if (host->sd_error)
|
||||
mmcif_dma_complete(host);
|
||||
} else {
|
||||
dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void mmcif_timeout_work(struct work_struct *work)
|
||||
{
|
||||
struct delayed_work *d = container_of(work, struct delayed_work, work);
|
||||
struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);
|
||||
struct mmc_request *mrq = host->mrq;
|
||||
|
||||
if (host->dying)
|
||||
/* Don't run after mmc_remove_host() */
|
||||
return;
|
||||
|
||||
/*
|
||||
* Handle races with cancel_delayed_work(), unless
|
||||
* cancel_delayed_work_sync() is used
|
||||
*/
|
||||
switch (host->wait_for) {
|
||||
case MMCIF_WAIT_FOR_CMD:
|
||||
mrq->cmd->error = sh_mmcif_error_manage(host);
|
||||
break;
|
||||
case MMCIF_WAIT_FOR_STOP:
|
||||
mrq->stop->error = sh_mmcif_error_manage(host);
|
||||
break;
|
||||
case MMCIF_WAIT_FOR_MREAD:
|
||||
case MMCIF_WAIT_FOR_MWRITE:
|
||||
case MMCIF_WAIT_FOR_READ:
|
||||
case MMCIF_WAIT_FOR_WRITE:
|
||||
case MMCIF_WAIT_FOR_READ_END:
|
||||
case MMCIF_WAIT_FOR_WRITE_END:
|
||||
host->data->error = sh_mmcif_error_manage(host);
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
|
||||
host->state = STATE_IDLE;
|
||||
host->wait_for = MMCIF_WAIT_FOR_REQUEST;
|
||||
host->data = NULL;
|
||||
host->mrq = NULL;
|
||||
mmc_request_done(host->mmc, mrq);
|
||||
}
|
||||
|
||||
static int __devinit sh_mmcif_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret = 0, irq[2];
|
||||
@ -1054,7 +1289,6 @@ static int __devinit sh_mmcif_probe(struct platform_device *pdev)
|
||||
host->clk = clk_get_rate(host->hclk);
|
||||
host->pd = pdev;
|
||||
|
||||
init_completion(&host->intr_wait);
|
||||
spin_lock_init(&host->lock);
|
||||
|
||||
mmc->ops = &sh_mmcif_ops;
|
||||
@ -1091,18 +1325,20 @@ static int __devinit sh_mmcif_probe(struct platform_device *pdev)
|
||||
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
|
||||
|
||||
ret = request_irq(irq[0], sh_mmcif_intr, 0, "sh_mmc:error", host);
|
||||
ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:error", host);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n");
|
||||
goto clean_up3;
|
||||
}
|
||||
ret = request_irq(irq[1], sh_mmcif_intr, 0, "sh_mmc:int", host);
|
||||
ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:int", host);
|
||||
if (ret) {
|
||||
free_irq(irq[0], host);
|
||||
dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
|
||||
goto clean_up3;
|
||||
}
|
||||
|
||||
INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work);
|
||||
|
||||
mmc_detect_change(host->mmc, 0);
|
||||
|
||||
dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
|
||||
@ -1129,11 +1365,19 @@ static int __devexit sh_mmcif_remove(struct platform_device *pdev)
|
||||
struct sh_mmcif_host *host = platform_get_drvdata(pdev);
|
||||
int irq[2];
|
||||
|
||||
host->dying = true;
|
||||
pm_runtime_get_sync(&pdev->dev);
|
||||
|
||||
mmc_remove_host(host->mmc);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
|
||||
|
||||
/*
|
||||
* FIXME: cancel_delayed_work(_sync)() and free_irq() race with the
|
||||
* mmc_remove_host() call above. But swapping order doesn't help either
|
||||
* (a query on the linux-mmc mailing list didn't bring any replies).
|
||||
*/
|
||||
cancel_delayed_work_sync(&host->timeout_work);
|
||||
|
||||
if (host->addr)
|
||||
iounmap(host->addr);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user