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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 09:30:53 +07:00
mmc: sh_mmcif: cosmetic clean up
This patch doesn't introduce any functional changes, it only simplifies some code fragments, removes superfluous parameters, fixes typos. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Chris Ball <cjb@laptop.org>
This commit is contained in:
Guennadi Liakhovetski
Chris Ball
parent
8a8284a98c
commit
ee4b88879f
@ -124,6 +124,11 @@
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#define MASK_MRBSYTO (1 << 1)
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#define MASK_MRSPTO (1 << 0)
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#define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
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MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
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MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \
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MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
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/* CE_HOST_STS1 */
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#define STS1_CMDSEQ (1 << 31)
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@ -176,8 +181,8 @@ struct sh_mmcif_host {
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long timeout;
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void __iomem *addr;
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struct completion intr_wait;
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spinlock_t lock; /* protect sh_mmcif_host::state */
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enum mmcif_state state;
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spinlock_t lock;
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bool power;
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bool card_present;
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@ -422,7 +427,7 @@ static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
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static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
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{
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u32 state1, state2;
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int ret, timeout = 10000000;
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int ret, timeout;
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host->sd_error = false;
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@ -434,31 +439,30 @@ static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
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if (state1 & STS1_CMDSEQ) {
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sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
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sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
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while (1) {
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timeout--;
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if (timeout < 0) {
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dev_err(&host->pd->dev,
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"Forceed end of command sequence timeout err\n");
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return -EIO;
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}
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for (timeout = 10000000; timeout; timeout--) {
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if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
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& STS1_CMDSEQ))
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& STS1_CMDSEQ))
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break;
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mdelay(1);
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}
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if (!timeout) {
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dev_err(&host->pd->dev,
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"Forced end of command sequence timeout err\n");
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return -EIO;
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}
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sh_mmcif_sync_reset(host);
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dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
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return -EIO;
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}
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if (state2 & STS2_CRC_ERR) {
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dev_dbg(&host->pd->dev, ": Happened CRC error\n");
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dev_dbg(&host->pd->dev, ": CRC error\n");
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ret = -EIO;
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} else if (state2 & STS2_TIMEOUT_ERR) {
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dev_dbg(&host->pd->dev, ": Happened Timeout error\n");
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dev_dbg(&host->pd->dev, ": Timeout\n");
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ret = -ETIMEDOUT;
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} else {
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dev_dbg(&host->pd->dev, ": Happened End/Index error\n");
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dev_dbg(&host->pd->dev, ": End/Index error\n");
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ret = -EIO;
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}
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return ret;
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@ -681,55 +685,44 @@ static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
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static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
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struct mmc_request *mrq, u32 opc)
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{
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int ret;
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switch (opc) {
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case MMC_READ_MULTIPLE_BLOCK:
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ret = sh_mmcif_multi_read(host, mrq);
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break;
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return sh_mmcif_multi_read(host, mrq);
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case MMC_WRITE_MULTIPLE_BLOCK:
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ret = sh_mmcif_multi_write(host, mrq);
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break;
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return sh_mmcif_multi_write(host, mrq);
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case MMC_WRITE_BLOCK:
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ret = sh_mmcif_single_write(host, mrq);
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break;
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return sh_mmcif_single_write(host, mrq);
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case MMC_READ_SINGLE_BLOCK:
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case MMC_SEND_EXT_CSD:
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ret = sh_mmcif_single_read(host, mrq);
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break;
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return sh_mmcif_single_read(host, mrq);
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default:
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dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
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ret = -EINVAL;
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break;
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return -EINVAL;
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}
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return ret;
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}
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static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
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struct mmc_request *mrq, struct mmc_command *cmd)
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struct mmc_request *mrq)
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{
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struct mmc_command *cmd = mrq->cmd;
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long time;
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int ret = 0, mask = 0;
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u32 opc = cmd->opcode;
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int ret = 0;
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u32 mask, opc = cmd->opcode;
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switch (opc) {
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/* respons busy check */
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/* response busy check */
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case MMC_SWITCH:
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case MMC_STOP_TRANSMISSION:
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case MMC_SET_WRITE_PROT:
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case MMC_CLR_WRITE_PROT:
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case MMC_ERASE:
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case MMC_GEN_CMD:
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mask = MASK_MRBSYE;
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mask = MASK_START_CMD | MASK_MRBSYE;
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break;
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default:
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mask = MASK_MCRSPE;
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mask = MASK_START_CMD | MASK_MCRSPE;
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break;
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}
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mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR |
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MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR |
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MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO |
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MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
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if (host->data) {
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sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
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@ -797,8 +790,9 @@ static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
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}
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static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
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struct mmc_request *mrq, struct mmc_command *cmd)
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struct mmc_request *mrq)
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{
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struct mmc_command *cmd = mrq->stop;
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long time;
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if (mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK)
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@ -867,11 +861,11 @@ static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
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sh_mmcif_start_dma_tx(host);
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}
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}
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sh_mmcif_start_cmd(host, mrq, mrq->cmd);
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sh_mmcif_start_cmd(host, mrq);
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host->data = NULL;
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if (!mrq->cmd->error && mrq->stop)
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sh_mmcif_stop_cmd(host, mrq, mrq->stop);
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sh_mmcif_stop_cmd(host, mrq);
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host->state = STATE_IDLE;
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mmc_request_done(mmc, mrq);
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}
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@ -948,11 +942,6 @@ static struct mmc_host_ops sh_mmcif_ops = {
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.get_cd = sh_mmcif_get_cd,
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};
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static void sh_mmcif_detect(struct mmc_host *mmc)
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{
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mmc_detect_change(mmc, 0);
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}
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static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
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{
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struct sh_mmcif_host *host = dev_id;
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@ -1114,7 +1103,7 @@ static int __devinit sh_mmcif_probe(struct platform_device *pdev)
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goto clean_up3;
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}
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sh_mmcif_detect(host->mmc);
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mmc_detect_change(host->mmc, 0);
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dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
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dev_dbg(&pdev->dev, "chip ver H'%04x\n",
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