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drm/amd/powerplay: custom peak clock freq for navi10
v2: add function smu_default_set_performance_level as default dpm level handler. change function name smu_set_performance_level to smu_asic_set_performance_level v1: 1.NAVI10_PEAK_SCLK_XTX 1830 Mhz 2.NAVI10_PEAK_SCLK_XT 1755 Mhz 3.NAVI10_PEAK_SCLK_XL 1625 Mhz Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Jack Gui <Jack.Gui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1394,13 +1394,49 @@ static int smu_enable_umd_pstate(void *handle,
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return 0;
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}
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static int smu_default_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
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{
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int ret = 0;
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uint32_t sclk_mask, mclk_mask, soc_mask;
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switch (level) {
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case AMD_DPM_FORCED_LEVEL_HIGH:
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ret = smu_force_dpm_limit_value(smu, true);
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break;
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case AMD_DPM_FORCED_LEVEL_LOW:
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ret = smu_force_dpm_limit_value(smu, false);
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break;
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case AMD_DPM_FORCED_LEVEL_AUTO:
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case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
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ret = smu_unforce_dpm_levels(smu);
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break;
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case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
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case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
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case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
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ret = smu_get_profiling_clk_mask(smu, level,
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&sclk_mask,
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&mclk_mask,
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&soc_mask);
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if (ret)
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return ret;
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smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
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smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
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smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
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break;
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case AMD_DPM_FORCED_LEVEL_MANUAL:
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case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
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default:
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break;
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}
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return ret;
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}
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int smu_adjust_power_state_dynamic(struct smu_context *smu,
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enum amd_dpm_forced_level level,
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bool skip_display_settings)
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{
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int ret = 0;
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int index = 0;
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uint32_t sclk_mask, mclk_mask, soc_mask;
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long workload;
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struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
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@ -1431,39 +1467,10 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
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}
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if (smu_dpm_ctx->dpm_level != level) {
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switch (level) {
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case AMD_DPM_FORCED_LEVEL_HIGH:
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ret = smu_force_dpm_limit_value(smu, true);
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break;
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case AMD_DPM_FORCED_LEVEL_LOW:
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ret = smu_force_dpm_limit_value(smu, false);
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break;
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case AMD_DPM_FORCED_LEVEL_AUTO:
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case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
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ret = smu_unforce_dpm_levels(smu);
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break;
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case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
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case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
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case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
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ret = smu_get_profiling_clk_mask(smu, level,
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&sclk_mask,
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&mclk_mask,
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&soc_mask);
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if (ret)
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return ret;
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smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
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smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
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smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
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break;
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case AMD_DPM_FORCED_LEVEL_MANUAL:
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case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
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default:
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break;
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ret = smu_asic_set_performance_level(smu, level);
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if (ret) {
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ret = smu_default_set_performance_level(smu, level);
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}
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if (!ret)
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smu_dpm_ctx->dpm_level = level;
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}
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@ -631,6 +631,7 @@ struct pptable_funcs {
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int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
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int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
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int (*set_default_od_settings)(struct smu_context *smu, bool initialize);
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int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
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};
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struct smu_funcs
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@ -928,6 +929,9 @@ struct smu_funcs
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((smu)->funcs->baco_get_state? (smu)->funcs->baco_get_state((smu), (state)) : 0)
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#define smu_baco_reset(smu) \
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((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
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#define smu_asic_set_performance_level(smu, level) \
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((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
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extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
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uint16_t *size, uint8_t *frev, uint8_t *crev,
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@ -1590,6 +1590,60 @@ static int navi10_set_ppfeature_status(struct smu_context *smu,
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return 0;
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}
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static int navi10_set_peak_clock_by_device(struct smu_context *smu)
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{
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struct amdgpu_device *adev = smu->adev;
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int ret = 0;
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uint32_t sclk_freq = 0, uclk_freq = 0;
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uint32_t uclk_level = 0;
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switch (adev->rev_id) {
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case 0xf0: /* XTX */
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case 0xc0:
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sclk_freq = NAVI10_PEAK_SCLK_XTX;
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break;
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case 0xf1: /* XT */
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case 0xc1:
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sclk_freq = NAVI10_PEAK_SCLK_XT;
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break;
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default: /* XL */
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sclk_freq = NAVI10_PEAK_SCLK_XL;
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break;
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}
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ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_level);
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if (ret)
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return ret;
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ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, uclk_level - 1, &uclk_freq);
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if (ret)
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return ret;
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ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
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if (ret)
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return ret;
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ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
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if (ret)
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return ret;
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return ret;
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}
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static int navi10_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
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{
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int ret = 0;
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switch (level) {
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case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
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ret = navi10_set_peak_clock_by_device(smu);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static const struct pptable_funcs navi10_ppt_funcs = {
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.tables_init = navi10_tables_init,
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.alloc_dpm_context = navi10_allocate_dpm_context,
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@ -1625,6 +1679,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
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.get_uclk_dpm_states = navi10_get_uclk_dpm_states,
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.get_ppfeature_status = navi10_get_ppfeature_status,
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.set_ppfeature_status = navi10_set_ppfeature_status,
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.set_performance_level = navi10_set_performance_level,
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};
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void navi10_set_ppt_funcs(struct smu_context *smu)
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@ -23,6 +23,10 @@
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#ifndef __NAVI10_PPT_H__
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#define __NAVI10_PPT_H__
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#define NAVI10_PEAK_SCLK_XTX (1830)
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#define NAVI10_PEAK_SCLK_XT (1755)
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#define NAVI10_PEAK_SCLK_XL (1625)
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extern void navi10_set_ppt_funcs(struct smu_context *smu);
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#endif
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