First batch of DT changes for 4.1:

- at91sam9x5 & EK board: ISI and camera sensors
 - at91sam9n12 & EK board: USB gadget nodes
 - sama5d3: typos, gpio-keys on Xplained board
 - sama5d4: i2c, leds, audio, ISI, crypto, pwm missing nodes
 - new sama5d4 xplained board
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Merge tag 'at91-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/dt

Pull "First batch of DT changes for 4.1" into next/dt:

- at91sam9x5 & EK board: ISI and camera sensors
- at91sam9n12 & EK board: USB gadget nodes
- sama5d3: typos, gpio-keys on Xplained board
- sama5d4: i2c, leds, audio, ISI, crypto, pwm missing nodes
- new sama5d4 xplained board

* tag 'at91-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91: (31 commits)
  ARM: at91/dt: sama5d4: add ISI dt support
  ARM: at91/dt: sama5d4: add pwm0 device node
  ARM: at91/dt: sama5d4: add aes, sha and tdes nodes
  ARM: at91: dt: sama5d4ek: enable audio
  ARM: at91: dt: sama5d4ek: add and enable wm8904
  ARM: at91: dt: sama5d4ek: enable ssc0
  ARM: at91: dt: sama5d4: add ssc nodes
  ARM: at91/dt: sama5d4 xplained: add i2c0
  ARM: at91/dt: sama5d4: add dts for sama5d4 xplained board
  ARM: at91/dt: sama5d4: add #{address, size}_cells properties for macb0
  ARM: at91/dt: sama5d4ek: add leds in DT node
  ARM: at91/dt: add i2c1 declaration to sama5d4
  ARM: at91/dt: gpio-keys: address-cells and size-cells properties are not needed
  ARM: at91/dt: at91-sama5d3_xplained: add gpio-key pinctrl property
  ARM: at91/dt/trivial: correct file headers for SAMA5D3 SoC peripherals
  ARM: at91/dt: at91sam9n12ek: enable udp
  ARM: at91/dt: at91sam9n12: add udp device node
  ARM: at91: at91sam9g25ek/dts: enable ISI and ov2640
  ARM: at91: at91sam9x5ek/dts: add ov2640 support
  ARM: at91: at91sam9x5/dts: add ISI dt support, include isi node, pinctrls
  ...
This commit is contained in:
Arnd Bergmann 2015-03-11 22:48:55 +01:00
commit e3d00145e3
31 changed files with 702 additions and 70 deletions

View File

@ -26,6 +26,11 @@ Optional properties:
- atmel,disable : Should be present if you want to disable the watchdog.
- atmel,idle-halt : Should be present if you want to stop the watchdog when
entering idle state.
CAUTION: This property should be used with care, it actually makes the
watchdog not counting when the CPU is in idle state, therefore the
watchdog reset time depends on mean CPU usage and will not reset at all
if the CPU stop working while it is in idle state, which is probably
not what you want.
- atmel,dbg-halt : Should be present if you want to stop the watchdog when
entering debug state.

View File

@ -42,6 +42,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \
sama5d34ek.dtb \
sama5d35ek.dtb \
sama5d36ek.dtb \
at91-sama5d4_xplained.dtb \
at91-sama5d4ek.dtb
dtb-$(CONFIG_ARCH_ATLAS6) += \
atlas6-evb.dtb

View File

@ -188,6 +188,11 @@ pinctrl_i2c2_pu: i2c2_pu {
<AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
};
pinctrl_key_gpio: key_gpio_0 {
atmel,pins =
<AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_mmc0_cd: mmc0_cd {
atmel,pins =
<AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
@ -276,6 +281,9 @@ usb2: ehci@00700000 {
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio>;
bp3 {
label = "PB_USER";
gpios = <&pioE 29 GPIO_ACTIVE_LOW>;

View File

@ -0,0 +1,241 @@
/*
* at91-sama5d4_xplained.dts - Device Tree file for SAMA5D4 Xplained board
*
* Copyright (C) 2015 Atmel,
* 2015 Josh Wu <josh.wu@atmel.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sama5d4.dtsi"
/ {
model = "Atmel SAMA5D4 Xplained";
compatible = "atmel,sama5d4-xplained", "atmel,sama5d4", "atmel,sama5";
chosen {
bootargs = "console=ttyS0,115200 ignore_loglevel earlyprintk";
};
memory {
reg = <0x20000000 0x20000000>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
main_clock: clock@0 {
compatible = "atmel,osc", "fixed-clock";
clock-frequency = <12000000>;
};
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <12000000>;
};
};
ahb {
apb {
spi0: spi@f8010000 {
cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
status = "okay";
m25p80@0 {
compatible = "atmel,at25df321a";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
i2c0: i2c@f8014000 {
status = "okay";
};
macb0: ethernet@f8020000 {
phy-mode = "rmii";
status = "okay";
phy0: ethernet-phy@1 {
interrupt-parent = <&pioE>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
reg = <1>;
};
};
mmc1: mmc@fc000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioE 3 0>;
};
};
usart3: serial@fc00c000 {
status = "okay";
};
usart4: serial@fc010000 {
status = "okay";
};
adc0: adc@fc034000 {
atmel,adc-vref = <3300>;
status = "okay";
};
watchdog@fc068640 {
status = "okay";
};
pinctrl@fc06a000 {
board {
pinctrl_mmc1_cd: mmc1_cd {
atmel,pins =
<AT91_PIOE 3 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_usba_vbus: usba_vbus {
atmel,pins =
<AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
};
pinctrl_key_gpio: key_gpio_0 {
atmel,pins =
<AT91_PIOE 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
};
};
};
usb0: gadget@00400000 {
atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usba_vbus>;
status = "okay";
};
usb1: ohci@00500000 {
num-ports = <3>;
atmel,vbus-gpio = <0
&pioE 11 GPIO_ACTIVE_HIGH
&pioE 14 GPIO_ACTIVE_HIGH
>;
status = "okay";
};
usb2: ehci@00600000 {
status = "okay";
};
nand0: nand@80000000 {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
atmel,has-pmecc;
status = "okay";
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x40000>;
};
bootloader@40000 {
label = "bootloader";
reg = <0x40000 0x80000>;
};
bootloaderenv@c0000 {
label = "bootloader env";
reg = <0xc0000 0xc0000>;
};
dtb@180000 {
label = "device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
rootfs@800000 {
label = "rootfs";
reg = <0x800000 0x0f800000>;
};
};
};
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio>;
pb_user1 {
label = "pb_user1";
gpios = <&pioE 8 GPIO_ACTIVE_HIGH>;
linux,code = <0x100>;
gpio-key,wakeup;
};
};
leds {
compatible = "gpio-leds";
status = "okay";
d8 {
label = "d8";
gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
d10 {
label = "d10";
gpios = <&pioE 15 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};
};

View File

@ -115,6 +115,10 @@ slot@1 {
};
};
ssc0: ssc@f8008000 {
status = "okay";
};
spi0: spi@f8010000 {
cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
status = "okay";
@ -127,6 +131,13 @@ m25p80@0 {
i2c0: i2c@f8014000 {
status = "okay";
wm8904: codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
clocks = <&pck2>;
clock-names = "mclk";
};
};
macb0: ethernet@f8020000 {
@ -171,6 +182,10 @@ pinctrl_mmc1_cd: mmc1_cd {
atmel,pins =
<AT91_PIOE 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_pck2_as_audio_mck: pck2_as_audio_mck {
atmel,pins =
<AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_usba_vbus: usba_vbus {
atmel,pins =
<AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
@ -244,8 +259,6 @@ rootfs@800000 {
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio>;
@ -257,4 +270,42 @@ pb_user1 {
gpio-key,wakeup;
};
};
leds {
compatible = "gpio-leds";
status = "okay";
d8 {
label = "d8";
/* PE28, conflicts with usart4 rts pin */
gpios = <&pioE 28 GPIO_ACTIVE_LOW>;
};
d9 {
label = "d9";
gpios = <&pioE 9 GPIO_ACTIVE_HIGH>;
};
d10 {
label = "d10";
gpios = <&pioE 8 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};
sound {
compatible = "atmel,asoc-wm8904";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pck2_as_audio_mck>;
atmel,model = "wm8904 @ SAMA5D4EK";
atmel,audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN1L", "Line In Jack",
"IN1R", "Line In Jack";
atmel,ssc-controller = <&ssc0>;
atmel,audio-codec = <&wm8904>;
};
};

View File

@ -494,12 +494,12 @@ pinctrl_usart3: usart3-0 {
pinctrl_usart3_rts: usart3_rts-0 {
atmel,pins =
<AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC8 periph B */
<AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_usart3_cts: usart3_cts-0 {
atmel,pins =
<AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC10 periph B */
<AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
@ -976,7 +976,6 @@ watchdog@fffffd40 {
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
atmel,idle-halt;
status = "disabled";
};

View File

@ -69,7 +69,7 @@ sram0: sram@00300000 {
sram1: sram@00500000 {
compatible = "mmio-sram";
reg = <0x00300000 0x4000>;
reg = <0x00500000 0x4000>;
};
ahb {
@ -905,7 +905,6 @@ watchdog@fffffd40 {
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
atmel,idle-halt;
status = "disabled";
};

View File

@ -7,6 +7,7 @@
*/
#include "at91sam9x5.dtsi"
#include "at91sam9x5_isi.dtsi"
#include "at91sam9x5_usart3.dtsi"
#include "at91sam9x5_macb0.dtsi"

View File

@ -16,10 +16,28 @@ / {
ahb {
apb {
spi0: spi@f0000000 {
status = "disabled";
};
mmc1: mmc@f000c000 {
status = "disabled";
};
i2c0: i2c@f8010000 {
ov2640: camera@0x30 {
status = "okay";
};
};
macb0: ethernet@f802c000 {
phy-mode = "rmii";
status = "okay";
};
isi: isi@f8048000 {
status = "okay";
};
};
};
};

View File

@ -1116,7 +1116,6 @@ watchdog@fffffd40 {
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
atmel,idle-halt;
status = "disabled";
};

View File

@ -894,7 +894,6 @@ watchdog@fffffe40 {
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
atmel,idle-halt;
status = "disabled";
};
@ -913,6 +912,15 @@ pwm0: pwm@f8034000 {
clocks = <&pwm_clk>;
status = "disabled";
};
usb1: gadget@f803c000 {
compatible = "atmel,at91sam9260-udc";
reg = <0xf803c000 0x4000>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&udphs_clk>, <&udpck>;
clock-names = "pclk", "hclk";
status = "disabled";
};
};
nand0: nand@40000000 {

View File

@ -108,6 +108,13 @@ pinctrl_pck0_as_audio_mck: pck0_as_audio_mck {
<AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
usb1 {
pinctrl_usb1_vbus_sense: usb1_vbus_sense {
atmel,pins =
<AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PB16 gpio usb vbus sense, no pull up and deglitch */
};
};
};
spi0: spi@f0000000 {
@ -120,6 +127,13 @@ m25p80@0 {
};
};
usb1: gadget@f803c000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_vbus_sense>;
atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
status = "okay";
};
watchdog@fffffe40 {
status = "okay";
};

View File

@ -1130,7 +1130,6 @@ watchdog@fffffe40 {
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
atmel,idle-halt;
status = "disabled";
};

View File

@ -13,6 +13,37 @@
/ {
ahb {
apb {
pinctrl@fffff400 {
isi {
pinctrl_isi_data_0_7: isi-0-data-0-7 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D0, conflicts with LCDDAT0 */
AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D1, conflicts with LCDDAT1 */
AT91_PIOC 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D2, conflicts with LCDDAT2 */
AT91_PIOC 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D3, conflicts with LCDDAT3 */
AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D4, conflicts with LCDDAT4 */
AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D5, conflicts with LCDDAT5 */
AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D6, conflicts with LCDDAT6 */
AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D7, conflicts with LCDDAT7 */
AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_PCK, conflicts with LCDDAT12 */
AT91_PIOC 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_HSYNC, conflicts with LCDDAT14 */
AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* ISI_VSYNC, conflicts with LCDDAT13 */
};
pinctrl_isi_data_8_9: isi-0-data-8-9 {
atmel,pins =
<AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D8, conflicts with LCDDAT8 */
AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* ISI_D9, conflicts with LCDDAT9 */
};
pinctrl_isi_data_10_11: isi-0-data-10-11 {
atmel,pins =
<AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D10, conflicts with LCDDAT10 */
AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* ISI_D11, conflicts with LCDDAT11 */
};
};
};
pmc: pmc@fffffc00 {
periphck {
isi_clk: isi_clk {
@ -21,6 +52,21 @@ isi_clk: isi_clk {
};
};
};
isi: isi@f8048000 {
compatible = "atmel,at91sam9g45-isi";
reg = <0xf8048000 0x4000>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_isi_data_0_7>;
clocks = <&isi_clk>;
clock-names = "isi_clk";
status = "disabled";
port {
#address-cells = <1>;
#size-cells = <0>;
};
};
};
};
};

View File

@ -59,6 +59,16 @@ usb2: gadget@f803c000 {
status = "okay";
};
isi: isi@f8048000 {
status = "disabled";
port {
isi_0: endpoint@0 {
remote-endpoint = <&ov2640_0>;
bus-width = <8>;
};
};
};
i2c0: i2c@f8010000 {
status = "okay";
@ -66,9 +76,47 @@ wm8731: wm8731@1a {
compatible = "wm8731";
reg = <0x1a>;
};
ov2640: camera@0x30 {
compatible = "ovti,ov2640";
reg = <0x30>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>;
clocks = <&pck0>;
clock-names = "xvclk";
assigned-clocks = <&pck0>;
assigned-clock-rates = <25000000>;
status = "disabled";
port {
ov2640_0: endpoint {
remote-endpoint = <&isi_0>;
bus-width = <8>;
};
};
};
};
pinctrl@fffff400 {
camera_sensor {
pinctrl_pck0_as_isi_mck: pck0_as_isi_mck-0 {
atmel,pins =
<AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_MCK */
};
pinctrl_sensor_power: sensor_power-0 {
atmel,pins =
<AT91_PIOA 13 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_sensor_reset: sensor_reset-0 {
atmel,pins =
<AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
mmc0 {
pinctrl_board_mmc0: mmc0-board {
atmel,pins =

View File

@ -1248,7 +1248,6 @@ watchdog@fffffe40 {
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
atmel,idle-halt;
status = "disabled";
};

View File

@ -44,8 +44,6 @@ macb1: ethernet@f802c000 {
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
pb_user1 {
label = "pb_user1";

View File

@ -1,5 +1,5 @@
/*
* at91sama5d3_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
* sama5d3_can.dtsi - Device Tree Include file for SAMA5D3 SoC with
* CAN support
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>

View File

@ -1,5 +1,5 @@
/*
* at91sama5d3_emac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
* sama5d3_emac.dtsi - Device Tree Include file for SAMA5D3 SoC with
* Ethernet.
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>

View File

@ -1,5 +1,5 @@
/*
* at91sama5d3_gmac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
* sama5d3_gmac.dtsi - Device Tree Include file for SAMA5D3 SoC with
* Gigabit Ethernet.
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>

View File

@ -1,5 +1,5 @@
/*
* at91sama5d3_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
* sama5d3_lcd.dtsi - Device Tree Include file for SAMA5D3 SoC with
* LCD support
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>

View File

@ -1,5 +1,5 @@
/*
* at91sama5d3_mci2.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
* sama5d3_mci2.dtsi - Device Tree Include file for SAMA5D3 SoC with
* 3 MMC ports
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>

View File

@ -1,5 +1,5 @@
/*
* at91sama5d3_tcb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
* sama5d3_tcb1.dtsi - Device Tree Include file for SAMA5D3 SoC with
* 2 TC blocks.
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>

View File

@ -1,5 +1,5 @@
/*
* at91sama5d3_uart.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
* sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with
* UART support
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>

View File

@ -64,8 +64,13 @@ aliases {
gpio2 = &pioC;
gpio3 = &pioD;
gpio4 = &pioE;
pwm0 = &pwm0;
ssc0 = &ssc0;
ssc1 = &ssc1;
tcb0 = &tcb0;
tcb1 = &tcb1;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
};
cpus {
@ -318,6 +323,21 @@ dma1: dma-controller@f0004000 {
clock-names = "dma_clk";
};
isi: isi@f0008000 {
compatible = "atmel,at91sam9g45-isi";
reg = <0xf0008000 0x4000>;
interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_isi_data_0_7>;
clocks = <&isi_clk>;
clock-names = "isi_clk";
status = "disabled";
port {
#address-cells = <1>;
#size-cells = <0>;
};
};
ramc0: ramc@f0010000 {
compatible = "atmel,sama5d3-ddramc";
reg = <0xf0010000 0x200>;
@ -799,6 +819,33 @@ mmc0: mmc@f8000000 {
clock-names = "mci_clk";
};
ssc0: ssc@f8008000 {
compatible = "atmel,at91sam9g45-ssc";
reg = <0xf8008000 0x4000>;
interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
dmas = <&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(26))>,
<&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(27))>;
dma-names = "tx", "rx";
clocks = <&ssc0_clk>;
clock-names = "pclk";
status = "disabled";
};
pwm0: pwm@f800c000 {
compatible = "atmel,sama5d3-pwm";
reg = <0xf800c000 0x300>;
interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
#pwm-cells = <3>;
clocks = <&pwm_clk>;
status = "disabled";
};
spi0: spi@f8010000 {
#address-cells = <1>;
#size-cells = <0>;
@ -838,6 +885,25 @@ i2c0: i2c@f8014000 {
status = "disabled";
};
i2c1: i2c@f8018000 {
compatible = "atmel,at91sam9x5-i2c";
reg = <0xf8018000 0x4000>;
interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
dmas = <&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
AT91_XDMAC_DT_PERID(4)>,
<&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
AT91_XDMAC_DT_PERID(5)>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&twi1_clk>;
status = "disabled";
};
tcb0: timer@f801c000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf801c000 0x100>;
@ -852,6 +918,8 @@ macb0: ethernet@f8020000 {
interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_rmii>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&macb0_clk>, <&macb0_clk>;
clock-names = "hclk", "pclk";
status = "disabled";
@ -952,6 +1020,24 @@ usart4: serial@fc010000 {
status = "disabled";
};
ssc1: ssc@fc014000 {
compatible = "atmel,at91sam9g45-ssc";
reg = <0xfc014000 0x4000>;
interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
dmas = <&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(28))>,
<&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(29))>;
dma-names = "tx", "rx";
clocks = <&ssc1_clk>;
clock-names = "pclk";
status = "disabled";
};
tcb1: timer@fc020000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xfc020000 0x100>;
@ -1007,6 +1093,46 @@ trigger@3 {
};
};
aes@fc044000 {
compatible = "atmel,at91sam9g46-aes";
reg = <0xfc044000 0x100>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
AT91_XDMAC_DT_PERID(41)>,
<&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
AT91_XDMAC_DT_PERID(40)>;
dma-names = "tx", "rx";
clocks = <&aes_clk>;
clock-names = "aes_clk";
status = "disabled";
};
tdes@fc04c000 {
compatible = "atmel,at91sam9g46-tdes";
reg = <0xfc04c000 0x100>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
AT91_XDMAC_DT_PERID(42)>,
<&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
AT91_XDMAC_DT_PERID(43)>;
dma-names = "tx", "rx";
clocks = <&tdes_clk>;
clock-names = "tdes_clk";
status = "disabled";
};
sha@fc050000 {
compatible = "atmel,at91sam9g46-sha";
reg = <0xfc050000 0x100>;
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
AT91_XDMAC_DT_PERID(44)>;
dma-names = "tx";
clocks = <&sha_clk>;
clock-names = "sha_clk";
status = "disabled";
};
rstc@fc068600 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfc068600 0x10>;
@ -1189,6 +1315,14 @@ pinctrl_i2c0: i2c0-0 {
};
};
i2c1 {
pinctrl_i2c1: i2c1-0 {
atmel,pins =
<AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */
AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
};
};
i2c2 {
pinctrl_i2c2: i2c2-0 {
atmel,pins =
@ -1197,6 +1331,33 @@ pinctrl_i2c2: i2c2-0 {
};
};
isi {
pinctrl_isi_data_0_7: isi-0-data-0-7 {
atmel,pins =
<AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D0 */
AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D1 */
AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D2 */
AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D3 */
AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D4 */
AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D5 */
AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D6 */
AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D7 */
AT91_PIOB 1 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_PCK, conflict with G0_RXCK */
AT91_PIOB 3 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_VSYNC */
AT91_PIOB 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */
};
pinctrl_isi_data_8_9: isi-0-data-8-9 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */
AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */
};
pinctrl_isi_data_10_11: isi-0-data-10-11 {
atmel,pins =
<AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */
AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */
};
};
macb0 {
pinctrl_macb0_rmii: macb0_rmii-0 {
atmel,pins =
@ -1280,6 +1441,38 @@ AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
};
};
ssc0 {
pinctrl_ssc0_tx: ssc0_tx {
atmel,pins =
<AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK0 */
AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF0 */
AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */
};
pinctrl_ssc0_rx: ssc0_rx {
atmel,pins =
<AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK0 */
AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF0 */
AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */
};
};
ssc1 {
pinctrl_ssc1_tx: ssc1_tx {
atmel,pins =
<AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK1 */
AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF1 */
AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */
};
pinctrl_ssc1_rx: ssc1_rx {
atmel,pins =
<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK1 */
AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF1 */
AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */
};
};
usart2 {
pinctrl_usart2: usart2-0 {
atmel,pins =

View File

@ -70,6 +70,7 @@ CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_ARM_AT91_ETHER=y
CONFIG_MACB=y
# CONFIG_NET_VENDOR_BROADCOM is not set
CONFIG_DM9000=y

View File

@ -3,8 +3,6 @@
CONFIG_SYSVIPC=y
CONFIG_IRQ_DOMAIN_DEBUG=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y

View File

@ -270,37 +270,35 @@ static void __init at91_pm_sram_init(void)
phys_addr_t sram_pbase;
unsigned long sram_base;
struct device_node *node;
struct platform_device *pdev;
struct platform_device *pdev = NULL;
node = of_find_compatible_node(NULL, NULL, "mmio-sram");
if (!node) {
pr_warn("%s: failed to find sram node!\n", __func__);
return;
for_each_compatible_node(node, NULL, "mmio-sram") {
pdev = of_find_device_by_node(node);
if (pdev) {
of_node_put(node);
break;
}
}
pdev = of_find_device_by_node(node);
if (!pdev) {
pr_warn("%s: failed to find sram device!\n", __func__);
goto put_node;
return;
}
sram_pool = dev_get_gen_pool(&pdev->dev);
if (!sram_pool) {
pr_warn("%s: sram pool unavailable!\n", __func__);
goto put_node;
return;
}
sram_base = gen_pool_alloc(sram_pool, at91_slow_clock_sz);
if (!sram_base) {
pr_warn("%s: unable to alloc ocram!\n", __func__);
goto put_node;
return;
}
sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false);
put_node:
of_node_put(node);
}
#endif

View File

@ -44,7 +44,7 @@ static inline void at91rm9200_standby(void)
" mcr p15, 0, %0, c7, c0, 4\n\t"
" str %5, [%1, %2]"
:
: "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR),
: "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),
"r" (1), "r" (AT91RM9200_SDRAMC_SRR),
"r" (lpr));
}

View File

@ -25,11 +25,6 @@
*/
#undef SLOWDOWN_MASTER_CLOCK
#define MCKRDY_TIMEOUT 1000
#define MOSCRDY_TIMEOUT 1000
#define PLLALOCK_TIMEOUT 1000
#define PLLBLOCK_TIMEOUT 1000
pmc .req r0
sdramc .req r1
ramc1 .req r2
@ -41,56 +36,36 @@ tmp2 .req r5
* Wait until master clock is ready (after switching master clock source)
*/
.macro wait_mckrdy
mov tmp2, #MCKRDY_TIMEOUT
1: sub tmp2, tmp2, #1
cmp tmp2, #0
beq 2f
ldr tmp1, [pmc, #AT91_PMC_SR]
1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_MCKRDY
beq 1b
2:
.endm
/*
* Wait until master oscillator has stabilized.
*/
.macro wait_moscrdy
mov tmp2, #MOSCRDY_TIMEOUT
1: sub tmp2, tmp2, #1
cmp tmp2, #0
beq 2f
ldr tmp1, [pmc, #AT91_PMC_SR]
1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_MOSCS
beq 1b
2:
.endm
/*
* Wait until PLLA has locked.
*/
.macro wait_pllalock
mov tmp2, #PLLALOCK_TIMEOUT
1: sub tmp2, tmp2, #1
cmp tmp2, #0
beq 2f
ldr tmp1, [pmc, #AT91_PMC_SR]
1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_LOCKA
beq 1b
2:
.endm
/*
* Wait until PLLB has locked.
*/
.macro wait_pllblock
mov tmp2, #PLLBLOCK_TIMEOUT
1: sub tmp2, tmp2, #1
cmp tmp2, #0
beq 2f
ldr tmp1, [pmc, #AT91_PMC_SR]
1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_LOCKB
beq 1b
2:
.endm
.text
@ -134,6 +109,16 @@ ddr_sr_enable:
cmp memctrl, #AT91_MEMCTRL_DDRSDR
bne sdr_sr_enable
/* LPDDR1 --> force DDR2 mode during self-refresh */
ldr tmp1, [sdramc, #AT91_DDRSDRC_MDR]
str tmp1, .saved_sam9_mdr
bic tmp1, tmp1, #~AT91_DDRSDRC_MD
cmp tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR
ldreq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
biceq tmp1, tmp1, #AT91_DDRSDRC_MD
orreq tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2
streq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
/* prepare for DDRAM self-refresh mode */
ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
str tmp1, .saved_sam9_lpr
@ -142,14 +127,26 @@ ddr_sr_enable:
/* figure out if we use the second ram controller */
cmp ramc1, #0
ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
strne tmp2, .saved_sam9_lpr1
bicne tmp2, #AT91_DDRSDRC_LPCB
orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
beq ddr_no_2nd_ctrl
ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
str tmp2, .saved_sam9_mdr1
bic tmp2, tmp2, #~AT91_DDRSDRC_MD
cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
biceq tmp2, tmp2, #AT91_DDRSDRC_MD
orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
str tmp2, .saved_sam9_lpr1
bic tmp2, #AT91_DDRSDRC_LPCB
orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
/* Enable DDRAM self-refresh mode */
str tmp2, [ramc1, #AT91_DDRSDRC_LPR]
ddr_no_2nd_ctrl:
str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
b sdr_sr_done
@ -280,12 +277,17 @@ sdr_sr_done:
*/
cmp memctrl, #AT91_MEMCTRL_DDRSDR
bne sdr_en_restore
/* Restore MDR in case of LPDDR1 */
ldr tmp1, .saved_sam9_mdr
str tmp1, [sdramc, #AT91_DDRSDRC_MDR]
/* Restore LPR on AT91 with DDRAM */
ldr tmp1, .saved_sam9_lpr
str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
/* if we use the second ram controller */
cmp ramc1, #0
ldrne tmp2, .saved_sam9_mdr1
strne tmp2, [ramc1, #AT91_DDRSDRC_MDR]
ldrne tmp2, .saved_sam9_lpr1
strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
@ -319,5 +321,11 @@ ram_restored:
.saved_sam9_lpr1:
.word 0
.saved_sam9_mdr:
.word 0
.saved_sam9_mdr1:
.word 0
ENTRY(at91_slow_clock_sz)
.word .-at91_slow_clock

View File

@ -92,7 +92,7 @@
#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
#define AT91_DDRSDRC_MD (7 << 0) /* Memory Device Type */
#define AT91_DDRSDRC_MD_SDR 0
#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3