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drm/i915: Remove I915_POSTING_READ_FW
Only a few call sites remain which have been converted to uncore mmio accessors and so the macro can be removed. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190611104548.30545-2-tvrtko.ursulin@linux.intel.com
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@ -2877,7 +2877,6 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
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*/
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*/
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#define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
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#define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
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#define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
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#define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
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#define POSTING_READ_FW(reg__) __I915_REG_OP(posting_read_fw, dev_priv, (reg__))
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/* "Broadcast RGB" property */
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/* "Broadcast RGB" property */
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#define INTEL_BROADCAST_RGB_AUTO 0
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#define INTEL_BROADCAST_RGB_AUTO 0
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@ -263,11 +263,12 @@ void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv)
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i915_gem_chipset_flush(dev_priv);
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i915_gem_chipset_flush(dev_priv);
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with_intel_runtime_pm(dev_priv, wakeref) {
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with_intel_runtime_pm(dev_priv, wakeref) {
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spin_lock_irq(&dev_priv->uncore.lock);
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struct intel_uncore *uncore = &dev_priv->uncore;
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POSTING_READ_FW(RING_HEAD(RENDER_RING_BASE));
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spin_lock_irq(&uncore->lock);
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intel_uncore_posting_read_fw(uncore,
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spin_unlock_irq(&dev_priv->uncore.lock);
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RING_HEAD(RENDER_RING_BASE));
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spin_unlock_irq(&uncore->lock);
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}
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}
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}
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}
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@ -387,7 +387,7 @@ static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
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void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask)
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void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask)
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{
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{
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ilk_update_gt_irq(dev_priv, mask, mask);
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ilk_update_gt_irq(dev_priv, mask, mask);
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POSTING_READ_FW(GTIMR);
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intel_uncore_posting_read_fw(&dev_priv->uncore, GTIMR);
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}
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}
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void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask)
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void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask)
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@ -557,10 +557,10 @@ static void guc_add_request(struct intel_guc *guc, struct i915_request *rq)
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*/
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*/
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static void flush_ggtt_writes(struct i915_vma *vma)
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static void flush_ggtt_writes(struct i915_vma *vma)
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{
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{
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struct drm_i915_private *dev_priv = vma->vm->i915;
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struct drm_i915_private *i915 = vma->vm->i915;
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if (i915_vma_is_map_and_fenceable(vma))
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if (i915_vma_is_map_and_fenceable(vma))
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POSTING_READ_FW(GUC_STATUS);
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intel_uncore_posting_read_fw(&i915->uncore, GUC_STATUS);
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}
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}
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static void inject_preempt_context(struct work_struct *work)
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static void inject_preempt_context(struct work_struct *work)
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@ -1949,6 +1949,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
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{
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_uncore *uncore = &dev_priv->uncore;
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const struct vlv_fifo_state *fifo_state =
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const struct vlv_fifo_state *fifo_state =
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&crtc_state->wm.vlv.fifo_state;
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&crtc_state->wm.vlv.fifo_state;
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int sprite0_start, sprite1_start, fifo_size;
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int sprite0_start, sprite1_start, fifo_size;
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@ -1974,13 +1975,13 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
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* intel_pipe_update_start() has already disabled interrupts
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* intel_pipe_update_start() has already disabled interrupts
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* for us, so a plain spin_lock() is sufficient here.
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* for us, so a plain spin_lock() is sufficient here.
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*/
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*/
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spin_lock(&dev_priv->uncore.lock);
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spin_lock(&uncore->lock);
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switch (crtc->pipe) {
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switch (crtc->pipe) {
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u32 dsparb, dsparb2, dsparb3;
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u32 dsparb, dsparb2, dsparb3;
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case PIPE_A:
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case PIPE_A:
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dsparb = I915_READ_FW(DSPARB);
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dsparb = intel_uncore_read_fw(uncore, DSPARB);
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dsparb2 = I915_READ_FW(DSPARB2);
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dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
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dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
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dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
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VLV_FIFO(SPRITEB, 0xff));
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VLV_FIFO(SPRITEB, 0xff));
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@ -1992,12 +1993,12 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
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dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
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dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
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VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
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VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
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I915_WRITE_FW(DSPARB, dsparb);
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intel_uncore_write_fw(uncore, DSPARB, dsparb);
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I915_WRITE_FW(DSPARB2, dsparb2);
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intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
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break;
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break;
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case PIPE_B:
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case PIPE_B:
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dsparb = I915_READ_FW(DSPARB);
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dsparb = intel_uncore_read_fw(uncore, DSPARB);
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dsparb2 = I915_READ_FW(DSPARB2);
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dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
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dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
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dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
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VLV_FIFO(SPRITED, 0xff));
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VLV_FIFO(SPRITED, 0xff));
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@ -2009,12 +2010,12 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
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dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
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dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
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VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
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VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
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I915_WRITE_FW(DSPARB, dsparb);
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intel_uncore_write_fw(uncore, DSPARB, dsparb);
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I915_WRITE_FW(DSPARB2, dsparb2);
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intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
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break;
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break;
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case PIPE_C:
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case PIPE_C:
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dsparb3 = I915_READ_FW(DSPARB3);
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dsparb3 = intel_uncore_read_fw(uncore, DSPARB3);
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dsparb2 = I915_READ_FW(DSPARB2);
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dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
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dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
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dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
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VLV_FIFO(SPRITEF, 0xff));
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VLV_FIFO(SPRITEF, 0xff));
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@ -2026,16 +2027,16 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
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dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
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dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
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VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
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VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
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I915_WRITE_FW(DSPARB3, dsparb3);
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intel_uncore_write_fw(uncore, DSPARB3, dsparb3);
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I915_WRITE_FW(DSPARB2, dsparb2);
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intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
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break;
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break;
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default:
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default:
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break;
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break;
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}
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}
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POSTING_READ_FW(DSPARB);
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intel_uncore_posting_read_fw(uncore, DSPARB);
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spin_unlock(&dev_priv->uncore.lock);
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spin_unlock(&uncore->lock);
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}
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}
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#undef VLV_FIFO
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#undef VLV_FIFO
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