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drm/i915: Remove I915_READ8
Only a few call sites remain which have been converted to uncore mmio accessors and so the macro can be removed. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190611104548.30545-1-tvrtko.ursulin@linux.intel.com
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@ -2838,8 +2838,6 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
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#define __I915_REG_OP(op__, dev_priv__, ...) \
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intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
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#define I915_READ8(reg__) __I915_REG_OP(read8, dev_priv, (reg__))
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#define I915_READ16(reg__) __I915_REG_OP(read16, dev_priv, (reg__))
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#define I915_WRITE16(reg__, val__) __I915_REG_OP(write16, dev_priv, (reg__), (val__))
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@ -643,6 +643,7 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
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{
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struct drm_device *dev = crt->base.base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_uncore *uncore = &dev_priv->uncore;
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u32 save_bclrpat;
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u32 save_vtotal;
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u32 vtotal, vactive;
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@ -663,9 +664,9 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
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pipeconf_reg = PIPECONF(pipe);
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pipe_dsl_reg = PIPEDSL(pipe);
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save_bclrpat = I915_READ(bclrpat_reg);
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save_vtotal = I915_READ(vtotal_reg);
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vblank = I915_READ(vblank_reg);
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save_bclrpat = intel_uncore_read(uncore, bclrpat_reg);
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save_vtotal = intel_uncore_read(uncore, vtotal_reg);
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vblank = intel_uncore_read(uncore, vblank_reg);
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vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
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vactive = (save_vtotal & 0x7ff) + 1;
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@ -674,21 +675,23 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
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vblank_end = ((vblank >> 16) & 0xfff) + 1;
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/* Set the border color to purple. */
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I915_WRITE(bclrpat_reg, 0x500050);
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intel_uncore_write(uncore, bclrpat_reg, 0x500050);
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if (!IS_GEN(dev_priv, 2)) {
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u32 pipeconf = I915_READ(pipeconf_reg);
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I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
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POSTING_READ(pipeconf_reg);
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u32 pipeconf = intel_uncore_read(uncore, pipeconf_reg);
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intel_uncore_write(uncore,
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pipeconf_reg,
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pipeconf | PIPECONF_FORCE_BORDER);
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intel_uncore_posting_read(uncore, pipeconf_reg);
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/* Wait for next Vblank to substitue
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* border color for Color info */
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intel_wait_for_vblank(dev_priv, pipe);
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st00 = I915_READ8(_VGA_MSR_WRITE);
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st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
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status = ((st00 & (1 << 4)) != 0) ?
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connector_status_connected :
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connector_status_disconnected;
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I915_WRITE(pipeconf_reg, pipeconf);
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intel_uncore_write(uncore, pipeconf_reg, pipeconf);
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} else {
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bool restore_vblank = false;
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int count, detect;
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@ -702,9 +705,10 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
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u32 vsync_start = (vsync & 0xffff) + 1;
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vblank_start = vsync_start;
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I915_WRITE(vblank_reg,
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(vblank_start - 1) |
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((vblank_end - 1) << 16));
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intel_uncore_write(uncore,
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vblank_reg,
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(vblank_start - 1) |
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((vblank_end - 1) << 16));
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restore_vblank = true;
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}
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/* sample in the vertical border, selecting the larger one */
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@ -716,9 +720,10 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
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/*
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* Wait for the border to be displayed
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*/
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while (I915_READ(pipe_dsl_reg) >= vactive)
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while (intel_uncore_read(uncore, pipe_dsl_reg) >= vactive)
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;
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while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
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while ((dsl = intel_uncore_read(uncore, pipe_dsl_reg)) <=
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vsample)
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;
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/*
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* Watch ST00 for an entire scanline
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@ -728,14 +733,14 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
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do {
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count++;
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/* Read the ST00 VGA status register */
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st00 = I915_READ8(_VGA_MSR_WRITE);
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st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
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if (st00 & (1 << 4))
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detect++;
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} while ((I915_READ(pipe_dsl_reg) == dsl));
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} while ((intel_uncore_read(uncore, pipe_dsl_reg) == dsl));
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/* restore vblank if necessary */
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if (restore_vblank)
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I915_WRITE(vblank_reg, vblank);
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intel_uncore_write(uncore, vblank_reg, vblank);
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/*
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* If more than 3/4 of the scanline detected a monitor,
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* then it is assumed to be present. This works even on i830,
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@ -748,7 +753,7 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
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}
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/* Restore previous settings */
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I915_WRITE(bclrpat_reg, save_bclrpat);
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intel_uncore_write(uncore, bclrpat_reg, save_bclrpat);
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return status;
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}
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@ -8160,15 +8160,15 @@ unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
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return val;
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}
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unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
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unsigned long i915_mch_val(struct drm_i915_private *i915)
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{
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unsigned long m, x, b;
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u32 tsfs;
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tsfs = I915_READ(TSFS);
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tsfs = intel_uncore_read(&i915->uncore, TSFS);
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m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
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x = I915_READ8(TR1);
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x = intel_uncore_read8(&i915->uncore, TR1);
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b = tsfs & TSFS_INTR_MASK;
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