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clk: bcm: rpi: Use CCF boundaries instead of rolling our own

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The raspberrypi firmware clock driver has a min_rate / max_rate clamping by
storing the info it needs in a private structure.

However, the CCF already provides such a facility, so we can switch to it
to remove the boilerplate.

Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/d4c53dab6de5d5f70743d9c139d0117589530e62.1592210452.git-series.maxime@cerno.tech
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Maxime Ripard 2020-06-15 10:40:52 +02:00 committed by Stephen Boyd
parent 9bd43a6184
commit df4b6a4c3b
1 changed files with 8 additions and 10 deletions
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18
drivers/clk/bcm/clk-raspberrypi.c
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@ -36,9 +36,6 @@ struct raspberrypi_clk {
struct rpi_firmware *firmware; struct rpi_firmware *firmware;
struct platform_device *cpufreq; struct platform_device *cpufreq;
unsigned long min_rate;
unsigned long max_rate;
struct clk_hw pllb; struct clk_hw pllb;
}; };
@ -142,13 +139,11 @@ static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
static int raspberrypi_pll_determine_rate(struct clk_hw *hw, static int raspberrypi_pll_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req) struct clk_rate_request *req)
{ {
struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
pllb);
u64 div, final_rate; u64 div, final_rate;
u32 ndiv, fdiv; u32 ndiv, fdiv;
/* We can't use req->rate directly as it would overflow */ /* We can't use req->rate directly as it would overflow */
final_rate = clamp(req->rate, rpi->min_rate, rpi->max_rate); final_rate = clamp(req->rate, req->min_rate, req->max_rate);
div = (u64)final_rate << A2W_PLL_FRAC_BITS; div = (u64)final_rate << A2W_PLL_FRAC_BITS;
do_div(div, req->best_parent_rate); do_div(div, req->best_parent_rate);
@ -215,12 +210,15 @@ static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
dev_info(rpi->dev, "CPU frequency range: min %u, max %u\n", dev_info(rpi->dev, "CPU frequency range: min %u, max %u\n",
min_rate, max_rate); min_rate, max_rate);
rpi->min_rate = min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
rpi->max_rate = max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
rpi->pllb.init = &init; rpi->pllb.init = &init;
return devm_clk_hw_register(rpi->dev, &rpi->pllb); ret = devm_clk_hw_register(rpi->dev, &rpi->pllb);
if (!ret)
clk_hw_set_rate_range(&rpi->pllb,
min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE,
max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE);
return ret;
} }
static struct clk_fixed_factor raspberrypi_clk_pllb_arm = { static struct clk_fixed_factor raspberrypi_clk_pllb_arm = {