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ARM: dts: DRA7: change address-cells and size-cells

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DRA7 SoC has the capability to support DDR memory upto 4GB. In order to
represent this in memory dt node, the address-cells and size cells
should be 2. So, changing the address-cells and size-cells to 2 and
updating the memory nodes accordingly.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Lokesh Vutla 2016-02-24 15:41:04 +05:30 committed by Tony Lindgren
parent 4d91e28548
commit dae320ec31
5 changed files with 14 additions and 14 deletions
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2
arch/arm/boot/dts/am57xx-beagle-x15.dts
View File

@ -24,7 +24,7 @@ aliases {
memory {
device_type = "memory";
reg = <0x80000000 0x80000000>;
reg = <0x0 0x80000000 0x0 0x80000000>;
};
vdd_3v3: fixedregulator-vdd_3v3 {

2
arch/arm/boot/dts/am57xx-cl-som-am57x.dts
View File

@ -21,7 +21,7 @@ / {
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB - minimal configuration */
reg = <0x0 0x80000000 0x0 0x20000000>; /* 512 MB - minimal configuration */
};
leds {

2
arch/arm/boot/dts/dra7-evm.dts
View File

@ -18,7 +18,7 @@ / {
memory {
device_type = "memory";
reg = <0x80000000 0x60000000>; /* 1536 MB */
reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
};
evm_3v3_sd: fixedregulator-sd {

20
arch/arm/boot/dts/dra7.dtsi
View File

@ -15,8 +15,8 @@
#define MAX_SOURCES 400
/ {
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
compatible = "ti,dra7xx";
interrupt-parent = <&crossbar_mpu>;
@ -57,10 +57,10 @@ gic: interrupt-controller@48211000 {
compatible = "arm,cortex-a15-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x48211000 0x1000>,
<0x48212000 0x1000>,
<0x48214000 0x2000>,
<0x48216000 0x2000>;
reg = <0x0 0x48211000 0x0 0x1000>,
<0x0 0x48212000 0x0 0x1000>,
<0x0 0x48214000 0x0 0x2000>,
<0x0 0x48216000 0x0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-parent = <&gic>;
};
@ -69,7 +69,7 @@ wakeupgen: interrupt-controller@48281000 {
compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x48281000 0x1000>;
reg = <0x0 0x48281000 0x0 0x1000>;
interrupt-parent = <&gic>;
};
@ -96,10 +96,10 @@ ocp {
compatible = "ti,dra7-l3-noc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ranges = <0x0 0x0 0x0 0xc0000000>;
ti,hwmods = "l3_main_1", "l3_main_2";
reg = <0x44000000 0x1000000>,
<0x45000000 0x1000>;
reg = <0x0 0x44000000 0x0 0x1000000>,
<0x0 0x45000000 0x0 0x1000>;
interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

2
arch/arm/boot/dts/dra72-evm.dts
View File

@ -17,7 +17,7 @@ / {
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1024 MB */
reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
};
aliases {