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arm64: dts: imx8qxp: Add DSP DT node
This includes DSP reserved memory, ADMA DSP device and DSP MU communication channels description. Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -230,3 +230,7 @@ IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
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>;
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};
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};
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&adma_dsp {
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status = "okay";
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};
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@ -113,6 +113,17 @@ gic: interrupt-controller@51a00000 {
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dsp_reserved: dsp@92400000 {
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reg = <0 0x92400000 0 0x2000000>;
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no-map;
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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@ -204,6 +215,27 @@ adma_lpcg: clock-controller@59000000 {
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#clock-cells = <1>;
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};
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adma_dsp: dsp@596e8000 {
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compatible = "fsl,imx8qxp-dsp";
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reg = <0x596e8000 0x88000>;
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clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
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<&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
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<&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
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clock-names = "ipg", "ocram", "core";
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power-domains = <&pd IMX_SC_R_MU_13A>,
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<&pd IMX_SC_R_MU_13B>,
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<&pd IMX_SC_R_DSP>,
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<&pd IMX_SC_R_DSP_RAM>;
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mbox-names = "txdb0", "txdb1",
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"rxdb0", "rxdb1";
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mboxes = <&lsio_mu13 2 0>,
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<&lsio_mu13 2 1>,
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<&lsio_mu13 3 0>,
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<&lsio_mu13 3 1>;
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memory-region = <&dsp_reserved>;
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status = "disabled";
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};
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adma_lpuart0: serial@5a060000 {
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compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
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reg = <0x5a060000 0x1000>;
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