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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 01:57:08 +07:00
iwlagn: add an API for TX stop
Tx stop moves to transport layer. Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -2310,7 +2310,7 @@ void iwlagn_stop_device(struct iwl_priv *priv)
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* already dead.
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*/
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if (test_bit(STATUS_DEVICE_ENABLED, &priv->status)) {
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iwlagn_txq_ctx_stop(priv);
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priv->trans.ops->tx_stop(priv);
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priv->trans.ops->rx_stop(priv);
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/* Power-down device's busmaster DMA clocks */
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@ -851,39 +851,6 @@ static inline void iwlagn_free_dma_ptr(struct iwl_priv *priv,
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memset(ptr, 0, sizeof(*ptr));
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}
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/**
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* iwlagn_txq_ctx_stop - Stop all Tx DMA channels
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*/
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void iwlagn_txq_ctx_stop(struct iwl_priv *priv)
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{
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int ch, txq_id;
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unsigned long flags;
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/* Turn off all Tx DMA fifos */
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spin_lock_irqsave(&priv->lock, flags);
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iwlagn_txq_set_sched(priv, 0);
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/* Stop each Tx DMA channel, and wait for it to be idle */
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for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
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iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
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if (iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
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FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
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1000))
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IWL_ERR(priv, "Failing on timeout while stopping"
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" DMA channel %d [0x%08x]", ch,
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iwl_read_direct32(priv, FH_TSSR_TX_STATUS_REG));
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}
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spin_unlock_irqrestore(&priv->lock, flags);
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if (!priv->txq)
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return;
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/* Unmap DMA from host system and free skb's */
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for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
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iwl_tx_queue_unmap(priv, txq_id);
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}
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/*
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* Find first available (lowest unused) Tx Queue, mark it "active".
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* Called only when finding queue for aggregation.
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@ -217,7 +217,6 @@ int iwlagn_txq_check_empty(struct iwl_priv *priv,
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void iwlagn_rx_reply_compressed_ba(struct iwl_priv *priv,
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struct iwl_rx_mem_buffer *rxb);
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int iwlagn_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index);
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void iwlagn_txq_ctx_stop(struct iwl_priv *priv);
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static inline u32 iwl_tx_status_to_mac80211(u32 status)
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{
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@ -384,7 +384,6 @@ void iwl_chswitch_done(struct iwl_priv *priv, bool is_success);
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void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq);
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int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
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int count, int slots_num, u32 id);
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void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id);
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void iwl_setup_watchdog(struct iwl_priv *priv);
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/*****************************************************
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* TX power
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@ -694,8 +694,6 @@ struct iwl_hw_params {
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****************************************************************************/
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extern void iwl_update_chain_flags(struct iwl_priv *priv);
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extern const u8 iwl_bcast_addr[ETH_ALEN];
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extern int iwl_rxq_stop(struct iwl_priv *priv);
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extern void iwl_txq_ctx_stop(struct iwl_priv *priv);
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extern int iwl_queue_space(const struct iwl_queue *q);
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static inline int iwl_queue_used(const struct iwl_queue *q, int i)
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{
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@ -1234,6 +1232,7 @@ struct iwl_trans;
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* @rx_stop: stop the rx
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* @rx_free: frees the rx memory
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* @tx_init:inits the tx memory, allocate if needed
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* @tx_stop: stop the tx
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* @tx_free: frees the tx memory
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*/
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struct iwl_trans_ops {
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@ -1242,6 +1241,7 @@ struct iwl_trans_ops {
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void (*rx_free)(struct iwl_priv *priv);
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int (*tx_init)(struct iwl_priv *priv);
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int (*tx_stop)(struct iwl_priv *priv);
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void (*tx_free)(struct iwl_priv *priv);
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};
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@ -327,6 +327,24 @@ static int iwl_trans_txq_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
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return 0;
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}
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/**
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* iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
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*/
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static void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id)
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{
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struct iwl_tx_queue *txq = &priv->txq[txq_id];
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struct iwl_queue *q = &txq->q;
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if (!q->n_bd)
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return;
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while (q->write_ptr != q->read_ptr) {
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/* The read_ptr needs to bound by q->n_window */
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iwlagn_txq_free_tfd(priv, txq, get_cmd_index(q, q->read_ptr));
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q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
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}
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}
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/**
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* iwl_tx_queue_free - Deallocate DMA queue.
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* @txq: Transmit queue to deallocate.
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@ -497,12 +515,50 @@ static int iwl_trans_tx_init(struct iwl_priv *priv)
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return ret;
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}
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/**
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* iwlagn_txq_ctx_stop - Stop all Tx DMA channels
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*/
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static int iwl_trans_tx_stop(struct iwl_priv *priv)
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{
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int ch, txq_id;
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unsigned long flags;
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/* Turn off all Tx DMA fifos */
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spin_lock_irqsave(&priv->lock, flags);
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iwlagn_txq_set_sched(priv, 0);
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/* Stop each Tx DMA channel, and wait for it to be idle */
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for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
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iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
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if (iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
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FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
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1000))
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IWL_ERR(priv, "Failing on timeout while stopping"
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" DMA channel %d [0x%08x]", ch,
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iwl_read_direct32(priv, FH_TSSR_TX_STATUS_REG));
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}
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spin_unlock_irqrestore(&priv->lock, flags);
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if (!priv->txq) {
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IWL_WARN(priv, "Stopping tx queues that aren't allocated...");
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return 0;
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}
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/* Unmap DMA from host system and free skb's */
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for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
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iwl_tx_queue_unmap(priv, txq_id);
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return 0;
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}
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static const struct iwl_trans_ops trans_ops = {
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.rx_init = iwl_trans_rx_init,
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.rx_stop = iwl_trans_rx_stop,
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.rx_free = iwl_trans_rx_free,
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.tx_init = iwl_trans_tx_init,
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.tx_stop = iwl_trans_tx_stop,
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.tx_free = iwl_trans_tx_free,
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};
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@ -221,23 +221,6 @@ int iwlagn_txq_attach_buf_to_tfd(struct iwl_priv *priv,
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return 0;
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}
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/**
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* iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
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*/
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void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id)
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{
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struct iwl_tx_queue *txq = &priv->txq[txq_id];
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struct iwl_queue *q = &txq->q;
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if (q->n_bd == 0)
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return;
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while (q->write_ptr != q->read_ptr) {
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iwlagn_txq_free_tfd(priv, txq, get_cmd_index(q, q->read_ptr));
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q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
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}
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}
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/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
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* DMA services
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*
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