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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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iwlagn: add an API for RX stop
Rx stop moves to transport layer. Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -905,17 +905,6 @@ void iwlagn_rx_replenish_now(struct iwl_priv *priv)
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iwlagn_rx_queue_restock(priv);
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}
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int iwlagn_rxq_stop(struct iwl_priv *priv)
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{
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/* stop Rx DMA */
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iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
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iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
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FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
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return 0;
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}
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int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
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{
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int idx = 0;
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@ -2321,13 +2310,14 @@ void iwlagn_stop_device(struct iwl_priv *priv)
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* already dead.
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*/
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if (test_bit(STATUS_DEVICE_ENABLED, &priv->status)) {
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iwlagn_txq_ctx_stop(priv);
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iwlagn_rxq_stop(priv);
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iwlagn_txq_ctx_stop(priv);
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priv->trans.ops->rx_stop(priv);
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/* Power-down device's busmaster DMA clocks */
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iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
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udelay(5);
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}
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/* Power-down device's busmaster DMA clocks */
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iwl_write_prph(priv, APMG_CLK_DIS_REG,
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APMG_CLK_VAL_DMA_CLK_RQT);
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udelay(5);
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}
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/* Make sure (redundant) we've released our request to stay awake */
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iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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@ -193,7 +193,6 @@ void iwlagn_rx_queue_restock(struct iwl_priv *priv);
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void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority);
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void iwlagn_rx_replenish(struct iwl_priv *priv);
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void iwlagn_rx_replenish_now(struct iwl_priv *priv);
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int iwlagn_rxq_stop(struct iwl_priv *priv);
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int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band);
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void iwl_setup_rx_handlers(struct iwl_priv *priv);
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@ -1231,12 +1231,14 @@ struct iwl_trans;
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* struct iwl_trans_ops - transport specific operations
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* @rx_init: inits the rx memory, allocate it if needed
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* @rx_stop: stop the rx
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* @rx_free: frees the rx memory
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* @tx_init:inits the tx memory, allocate if needed
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* @tx_free: frees the tx memory
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*/
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struct iwl_trans_ops {
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int (*rx_init)(struct iwl_priv *priv);
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int (*rx_stop)(struct iwl_priv *priv);
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void (*rx_free)(struct iwl_priv *priv);
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int (*tx_init)(struct iwl_priv *priv);
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@ -188,6 +188,15 @@ static void iwl_trans_rx_free(struct iwl_priv *priv)
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rxq->rb_stts = NULL;
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}
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static int iwl_trans_rx_stop(struct iwl_priv *priv)
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{
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/* stop Rx DMA */
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iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
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return iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
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FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
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}
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/* TODO:remove this code duplication */
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static inline int iwlagn_alloc_dma_ptr(struct iwl_priv *priv,
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struct iwl_dma_ptr *ptr, size_t size)
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@ -490,6 +499,7 @@ static int iwl_trans_tx_init(struct iwl_priv *priv)
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static const struct iwl_trans_ops trans_ops = {
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.rx_init = iwl_trans_rx_init,
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.rx_stop = iwl_trans_rx_stop,
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.rx_free = iwl_trans_rx_free,
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.tx_init = iwl_trans_tx_init,
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