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drm/amd/display: Use physical addressing for DMCUB on both dcn20/21

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[Why]
CW0 and CW1 need to use physical addressing mode for dcn20 and dcn21.

The current code for dcn20 is using virtual.

[How]
We already program the DMCUB like this on dcn21 so we should just use
the same sequence for both.

Copy the dcn21 sequences into the dmjub_dcn20.c file and rename them.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Kazlauskas 2019-11-20 10:37:19 -05:00 committed by Alex Deucher
parent 01c229d977
commit c09d1d3404
4 changed files with 45 additions and 126 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

61
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
View File

@ -54,6 +54,14 @@ const struct dmub_srv_common_regs dmub_srv_dcn20_regs = {
/* Shared functions. */ /* Shared functions. */
static inline void dmub_dcn20_translate_addr(const union dmub_addr *addr_in,
uint64_t fb_base,
uint64_t fb_offset,
union dmub_addr *addr_out)
{
addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
}
void dmub_dcn20_reset(struct dmub_srv *dmub) void dmub_dcn20_reset(struct dmub_srv *dmub)
{ {
REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 1); REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 1);
@ -71,19 +79,26 @@ void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,
const struct dmub_window *cw0, const struct dmub_window *cw0,
const struct dmub_window *cw1) const struct dmub_window *cw1)
{ {
REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); union dmub_addr offset;
REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x4, uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset;
DMCUB_MEM_WRITE_SPACE, 0x4);
REG_WRITE(DMCUB_REGION3_CW0_OFFSET, cw0->offset.u.low_part); REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, cw0->offset.u.high_part); REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3,
DMCUB_MEM_WRITE_SPACE, 0x3);
dmub_dcn20_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
DMCUB_REGION3_CW0_ENABLE, 1); DMCUB_REGION3_CW0_ENABLE, 1);
REG_WRITE(DMCUB_REGION3_CW1_OFFSET, cw1->offset.u.low_part); dmub_dcn20_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, cw1->offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
@ -100,37 +115,49 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
const struct dmub_window *cw5, const struct dmub_window *cw5,
const struct dmub_window *cw6) const struct dmub_window *cw6)
{ {
REG_WRITE(DMCUB_REGION3_CW2_OFFSET, cw2->offset.u.low_part); union dmub_addr offset;
REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, cw2->offset.u.high_part); uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset;
dmub_dcn20_translate_addr(&cw2->offset, fb_base, fb_offset, &offset);
REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part);
REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base); REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0, REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top, DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top,
DMCUB_REGION3_CW2_ENABLE, 1); DMCUB_REGION3_CW2_ENABLE, 1);
REG_WRITE(DMCUB_REGION3_CW3_OFFSET, cw3->offset.u.low_part); dmub_dcn20_translate_addr(&cw3->offset, fb_base, fb_offset, &offset);
REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, cw3->offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
DMCUB_REGION3_CW3_ENABLE, 1); DMCUB_REGION3_CW3_ENABLE, 1);
/* TODO: Move this to CW4. */ /* TODO: Move this to CW4. */
dmub_dcn20_translate_addr(&cw4->offset, fb_base, fb_offset, &offset);
REG_WRITE(DMCUB_REGION4_OFFSET, cw4->offset.u.low_part); REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, cw4->offset.u.high_part); REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, DMCUB_REGION4_TOP_ADDRESS, REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, DMCUB_REGION4_TOP_ADDRESS,
cw4->region.top - cw4->region.base - 1, DMCUB_REGION4_ENABLE, cw4->region.top - cw4->region.base - 1, DMCUB_REGION4_ENABLE,
1); 1);
REG_WRITE(DMCUB_REGION3_CW5_OFFSET, cw5->offset.u.low_part); dmub_dcn20_translate_addr(&cw5->offset, fb_base, fb_offset, &offset);
REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, cw5->offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
DMCUB_REGION3_CW5_ENABLE, 1); DMCUB_REGION3_CW5_ENABLE, 1);
REG_WRITE(DMCUB_REGION3_CW6_OFFSET, cw6->offset.u.low_part); dmub_dcn20_translate_addr(&cw6->offset, fb_base, fb_offset, &offset);
REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, cw6->offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,

97
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
View File

@ -51,102 +51,7 @@ const struct dmub_srv_common_regs dmub_srv_dcn21_regs = {
#undef DMUB_SF #undef DMUB_SF
}; };
static inline void dmub_dcn21_translate_addr(const union dmub_addr *addr_in, /* Shared functions. */
uint64_t fb_base,
uint64_t fb_offset,
union dmub_addr *addr_out)
{
addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
}
void dmub_dcn21_backdoor_load(struct dmub_srv *dmub,
const struct dmub_window *cw0,
const struct dmub_window *cw1)
{
union dmub_addr offset;
uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset;
REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3,
DMCUB_MEM_WRITE_SPACE, 0x3);
dmub_dcn21_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
DMCUB_REGION3_CW0_ENABLE, 1);
dmub_dcn21_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
DMCUB_REGION3_CW1_ENABLE, 1);
REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
0x20);
}
void dmub_dcn21_setup_windows(struct dmub_srv *dmub,
const struct dmub_window *cw2,
const struct dmub_window *cw3,
const struct dmub_window *cw4,
const struct dmub_window *cw5,
const struct dmub_window *cw6)
{
union dmub_addr offset;
uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset;
dmub_dcn21_translate_addr(&cw2->offset, fb_base, fb_offset, &offset);
REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part);
REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top,
DMCUB_REGION3_CW2_ENABLE, 1);
dmub_dcn21_translate_addr(&cw3->offset, fb_base, fb_offset, &offset);
REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
DMCUB_REGION3_CW3_ENABLE, 1);
/* TODO: Move this to CW4. */
dmub_dcn21_translate_addr(&cw4->offset, fb_base, fb_offset, &offset);
REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, DMCUB_REGION4_TOP_ADDRESS,
cw4->region.top - cw4->region.base - 1, DMCUB_REGION4_ENABLE,
1);
dmub_dcn21_translate_addr(&cw5->offset, fb_base, fb_offset, &offset);
REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
DMCUB_REGION3_CW5_ENABLE, 1);
dmub_dcn21_translate_addr(&cw6->offset, fb_base, fb_offset, &offset);
REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
DMCUB_REGION3_CW6_ENABLE, 1);
}
bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub) bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub)
{ {

11
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
View File

@ -34,17 +34,6 @@ extern const struct dmub_srv_common_regs dmub_srv_dcn21_regs;
/* Hardware functions. */ /* Hardware functions. */
void dmub_dcn21_backdoor_load(struct dmub_srv *dmub,
const struct dmub_window *cw0,
const struct dmub_window *cw1);
void dmub_dcn21_setup_windows(struct dmub_srv *dmub,
const struct dmub_window *cw2,
const struct dmub_window *cw3,
const struct dmub_window *cw4,
const struct dmub_window *cw5,
const struct dmub_window *cw6);
bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub); bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub);
bool dmub_dcn21_is_phy_init(struct dmub_srv *dmub); bool dmub_dcn21_is_phy_init(struct dmub_srv *dmub);

2
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
View File

@ -84,8 +84,6 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
if (asic == DMUB_ASIC_DCN21) { if (asic == DMUB_ASIC_DCN21) {
dmub->regs = &dmub_srv_dcn21_regs; dmub->regs = &dmub_srv_dcn21_regs;
funcs->backdoor_load = dmub_dcn21_backdoor_load;
funcs->setup_windows = dmub_dcn21_setup_windows;
funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done; funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done;
funcs->is_phy_init = dmub_dcn21_is_phy_init; funcs->is_phy_init = dmub_dcn21_is_phy_init;
} }