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drm/amd/display: Get DMUB registers from ASIC specific structs

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[Why]
These values can differ per ASIC and should follow the full DC style
register programming model.

[How]
Define a common list and fill in the common list separately for
dcn20 and dcn21.

Unlike DC we're not using designated initializers for better compiler
compatibility since this resides in the DMUB service.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Kazlauskas 2019-11-20 09:29:17 -05:00 committed by Alex Deucher
parent 6b5d7730d2
commit 01c229d977
7 changed files with 176 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
View File

@ -76,7 +76,7 @@ extern "C" {
/* Forward declarations */
struct dmub_srv;
struct dmub_cmd_header;
struct dmcu;
struct dmub_srv_common_regs;
/* enum dmub_status - return code for dmcub functions */
enum dmub_status {
@ -307,6 +307,8 @@ struct dmub_srv {
volatile const struct dmub_fw_state *fw_state;
/* private: internal use only */
const struct dmub_srv_common_regs *regs;
struct dmub_srv_base_funcs funcs;
struct dmub_srv_hw_funcs hw_funcs;
struct dmub_rb inbox1_rb;

25
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
View File

@ -25,6 +25,7 @@
#include "../inc/dmub_srv.h"
#include "dmub_reg.h"
#include "dmub_dcn20.h"
#include "dcn/dcn_2_0_0_offset.h"
#include "dcn/dcn_2_0_0_sh_mask.h"
@ -33,6 +34,25 @@
#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
#define CTX dmub
#define REGS dmub->regs
/* Registers. */
const struct dmub_srv_common_regs dmub_srv_dcn20_regs = {
#define DMUB_SR(reg) REG_OFFSET(reg),
{ DMUB_COMMON_REGS() },
#undef DMUB_SR
#define DMUB_SF(reg, field) FD_MASK(reg, field),
{ DMUB_COMMON_FIELDS() },
#undef DMUB_SF
#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
{ DMUB_COMMON_FIELDS() },
#undef DMUB_SF
};
/* Shared functions. */
void dmub_dcn20_reset(struct dmub_srv *dmub)
{
@ -47,8 +67,9 @@ void dmub_dcn20_reset_release(struct dmub_srv *dmub)
REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 0);
}
void dmub_dcn20_backdoor_load(struct dmub_srv *dmub, struct dmub_window *cw0,
struct dmub_window *cw1)
void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,
const struct dmub_window *cw0,
const struct dmub_window *cw1)
{
REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x4,

117
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
View File

@ -30,6 +30,123 @@
struct dmub_srv;
/* DCN20 register definitions. */
#define DMUB_COMMON_REGS() \
DMUB_SR(DMCUB_CNTL) \
DMUB_SR(DMCUB_MEM_CNTL) \
DMUB_SR(DMCUB_SEC_CNTL) \
DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
DMUB_SR(DMCUB_INBOX1_SIZE) \
DMUB_SR(DMCUB_INBOX1_RPTR) \
DMUB_SR(DMCUB_INBOX1_WPTR) \
DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \
DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \
DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \
DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \
DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \
DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \
DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \
DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \
DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \
DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \
DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \
DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \
DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \
DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \
DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \
DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \
DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \
DMUB_SR(DMCUB_REGION4_OFFSET) \
DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \
DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \
DMUB_SR(DMCUB_SCRATCH0) \
DMUB_SR(DMCUB_SCRATCH1) \
DMUB_SR(DMCUB_SCRATCH2) \
DMUB_SR(DMCUB_SCRATCH3) \
DMUB_SR(DMCUB_SCRATCH4) \
DMUB_SR(DMCUB_SCRATCH5) \
DMUB_SR(DMCUB_SCRATCH6) \
DMUB_SR(DMCUB_SCRATCH7) \
DMUB_SR(DMCUB_SCRATCH8) \
DMUB_SR(DMCUB_SCRATCH9) \
DMUB_SR(DMCUB_SCRATCH10) \
DMUB_SR(DMCUB_SCRATCH11) \
DMUB_SR(DMCUB_SCRATCH12) \
DMUB_SR(DMCUB_SCRATCH13) \
DMUB_SR(DMCUB_SCRATCH14) \
DMUB_SR(DMCUB_SCRATCH15) \
DMUB_SR(CC_DC_PIPE_DIS)
#define DMUB_COMMON_FIELDS() \
DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
DMUB_SF(DMCUB_CNTL, DMCUB_SOFT_RESET) \
DMUB_SF(DMCUB_CNTL, DMCUB_TRACEPORT_EN) \
DMUB_SF(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE) \
DMUB_SF(DMCUB_MEM_CNTL, DMCUB_MEM_WRITE_SPACE) \
DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \
DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \
DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \
DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_ENABLE) \
DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE) \
DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE) \
DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE) \
DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE) \
DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE) \
DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \
DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \
DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE)
struct dmub_srv_common_reg_offset {
#define DMUB_SR(reg) uint32_t reg;
DMUB_COMMON_REGS()
#undef DMUB_SR
};
struct dmub_srv_common_reg_shift {
#define DMUB_SF(reg, field) uint8_t reg##__##field;
DMUB_COMMON_FIELDS()
#undef DMUB_SF
};
struct dmub_srv_common_reg_mask {
#define DMUB_SF(reg, field) uint32_t reg##__##field;
DMUB_COMMON_FIELDS()
#undef DMUB_SF
};
struct dmub_srv_common_regs {
const struct dmub_srv_common_reg_offset offset;
const struct dmub_srv_common_reg_mask mask;
const struct dmub_srv_common_reg_shift shift;
};
extern const struct dmub_srv_common_regs dmub_srv_dcn20_regs;
/* Hardware functions. */
void dmub_dcn20_init(struct dmub_srv *dmub);

18
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
View File

@ -25,6 +25,7 @@
#include "../inc/dmub_srv.h"
#include "dmub_reg.h"
#include "dmub_dcn21.h"
#include "dcn/dcn_2_1_0_offset.h"
#include "dcn/dcn_2_1_0_sh_mask.h"
@ -32,6 +33,23 @@
#define BASE_INNER(seg) DMU_BASE__INST0_SEG##seg
#define CTX dmub
#define REGS dmub->regs
/* Registers. */
const struct dmub_srv_common_regs dmub_srv_dcn21_regs = {
#define DMUB_SR(reg) REG_OFFSET(reg),
{ DMUB_COMMON_REGS() },
#undef DMUB_SR
#define DMUB_SF(reg, field) FD_MASK(reg, field),
{ DMUB_COMMON_FIELDS() },
#undef DMUB_SF
#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
{ DMUB_COMMON_FIELDS() },
#undef DMUB_SF
};
static inline void dmub_dcn21_translate_addr(const union dmub_addr *addr_in,
uint64_t fb_base,

4
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
View File

@ -28,6 +28,10 @@
#include "dmub_dcn20.h"
/* Registers. */
extern const struct dmub_srv_common_regs dmub_srv_dcn21_regs;
/* Hardware functions. */
void dmub_dcn21_backdoor_load(struct dmub_srv *dmub,

10
drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h
View File

@ -34,11 +34,15 @@ struct dmub_srv;
#define BASE(seg) BASE_INNER(seg)
#define REG_OFFSET(base_index, addr) (BASE(base_index) + addr)
#define REG_OFFSET(reg_name) (BASE(mm##reg_name##_BASE_IDX) + mm##reg_name)
#define REG(reg_name) REG_OFFSET(mm ## reg_name ## _BASE_IDX, mm ## reg_name)
#define FD_SHIFT(reg_name, field) reg_name##__##field##__SHIFT
#define FD(reg_field) reg_field ## __SHIFT, reg_field ## _MASK
#define FD_MASK(reg_name, field) reg_name##__##field##_MASK
#define REG(reg) (REGS)->offset.reg
#define FD(reg_field) (REGS)->shift.reg_field, (REGS)->mask.reg_field
#define FN(reg_name, field) FD(reg_name##__##field)

4
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
View File

@ -69,6 +69,8 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
switch (asic) {
case DMUB_ASIC_DCN20:
case DMUB_ASIC_DCN21:
dmub->regs = &dmub_srv_dcn20_regs;
funcs->reset = dmub_dcn20_reset;
funcs->reset_release = dmub_dcn20_reset_release;
funcs->backdoor_load = dmub_dcn20_backdoor_load;
@ -80,6 +82,8 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
funcs->is_hw_init = dmub_dcn20_is_hw_init;
if (asic == DMUB_ASIC_DCN21) {
dmub->regs = &dmub_srv_dcn21_regs;
funcs->backdoor_load = dmub_dcn21_backdoor_load;
funcs->setup_windows = dmub_dcn21_setup_windows;
funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done;