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This pull request contains Broadcom ARM-based SoCs Device Tree changes

Browse Source 
for 5.7, please pull the following:
 
 - Stefan adds GPIO labels to the Raspberry Pi 4 Model B board DTS
 
 - Nicolas moves the eMMC2 controller into its separate node in order for
   platform firmware to perform the necessary "dma-ranges" property
   patching based on the chip revision since the eMMC controller has
   different addressing constraints.
 
 - Florian convers a whole bunch of Broadcom boards bindings from text to
   YAML.
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Merge tag 'arm-soc/for-5.7/devicetree' of https://github.com/Broadcom/stblinux into arm/dt

This pull request contains Broadcom ARM-based SoCs Device Tree changes
for 5.7, please pull the following:

- Stefan adds GPIO labels to the Raspberry Pi 4 Model B board DTS

- Nicolas moves the eMMC2 controller into its separate node in order for
  platform firmware to perform the necessary "dma-ranges" property
  patching based on the chip revision since the eMMC controller has
  different addressing constraints.

- Florian convers a whole bunch of Broadcom boards bindings from text to
  YAML.

* tag 'arm-soc/for-5.7/devicetree' of https://github.com/Broadcom/stblinux:
  dt-bindings: arm: Document Broadcom SoCs 'secondary-boot-reg'
  dt-bindings: arm: bcm: Convert Vulcan to YAML
  dt-bindings: arm: bcm: Convert BCM11351 to YAML
  dt-bindings: arm: bcm: Convert BCM4708 to YAML
  dt-bindings: arm: bcm: Convert BCM23550 to YAML
  dt-bindings: arm: bcm: Convert BCM21664 to YAML
  dt-bindings: arm: bcm: Convert Stingray to YAML
  dt-bindings: arm: bcm: Convert Northstar 2 to YAML
  dt-bindings: arm: bcm: Convert Northstar Plus to YAML
  dt-bindings: arm: bcm: Convert Hurricane 2 to YAML
  dt-bindings: arm: bcm: Convert Cygnus to YAML
  ARM: dts: bcm2711: Move emmc2 into its own bus
  ARM: dts: bcm2711-rpi-4-b: Add SoC GPIO labels

Link: https://lore.kernel.org/r/20200311212012.9418-2-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2020-03-25 21:41:31 +01:00
commit b0f9a3111d
26 changed files with 440 additions and 281 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt
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Broadcom Kona Family CPU Enable Method
--------------------------------------
This binding defines the enable method used for starting secondary
CPUs in the following Broadcom SoCs:
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664
The enable method is specified by defining the following required
properties in the "cpu" device tree node:
- enable-method = "brcm,bcm11351-cpu-method";
- secondary-boot-reg = <...>;
The secondary-boot-reg property is a u32 value that specifies the
physical address of the register used to request the ROM holding pen
code release a secondary CPU. The value written to the register is
formed by encoding the target CPU id into the low bits of the
physical start address it should jump to.
Example:
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
enable-method = "brcm,bcm11351-cpu-method";
secondary-boot-reg = <0x3500417c>;
};
};

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Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351.txt
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Broadcom BCM11351 device tree bindings
-------------------------------------------
Boards with the bcm281xx SoC family (which includes bcm11130, bcm11140,
bcm11351, bcm28145, bcm28155 SoCs) shall have the following properties:
Required root node property:
compatible = "brcm,bcm11351";
DEPRECATED: compatible = "bcm,bcm11351";

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm11351.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM11351 device tree bindings
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- brcm,bcm28155-ap
- const: brcm,bcm11351
...

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Documentation/devicetree/bindings/arm/bcm/brcm,bcm21664.txt
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Broadcom BCM21664 device tree bindings
--------------------------------------
This document describes the device tree bindings for boards with the BCM21664
SoC.
Required root node property:
- compatible: brcm,bcm21664
Example:
/ {
model = "BCM21664 SoC";
compatible = "brcm,bcm21664";
[...]
}

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm21664.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM21664 device tree bindings
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- brcm,bcm21664-garnet
- const: brcm,bcm21664
...

36
Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt
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Broadcom Kona Family CPU Enable Method
--------------------------------------
This binding defines the enable method used for starting secondary
CPUs in the following Broadcom SoCs:
BCM23550
The enable method is specified by defining the following required
properties in the "cpu" device tree node:
- enable-method = "brcm,bcm23550";
- secondary-boot-reg = <...>;
The secondary-boot-reg property is a u32 value that specifies the
physical address of the register used to request the ROM holding pen
code release a secondary CPU. The value written to the register is
formed by encoding the target CPU id into the low bits of the
physical start address it should jump to.
Example:
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
enable-method = "brcm,bcm23550";
secondary-boot-reg = <0x3500417c>;
};
};

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Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.txt
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@ -1,15 +0,0 @@
Broadcom BCM23550 device tree bindings
--------------------------------------
This document describes the device tree bindings for boards with the BCM23550
SoC.
Required root node property:
- compatible: brcm,bcm23550
Example:
/ {
model = "BCM23550 SoC";
compatible = "brcm,bcm23550";
[...]
}

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm23550.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM23550 device tree bindings
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- brcm,bcm23550-sparrow
- const: brcm,bcm23550
...

15
Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt
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Broadcom BCM4708 device tree bindings
-------------------------------------------
Boards with the BCM4708 SoC shall have the following properties:
Required root node property:
bcm4708
compatible = "brcm,bcm4708";
bcm4709
compatible = "brcm,bcm4709";
bcm53012
compatible = "brcm,bcm53012";

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm4708.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM4708 device tree bindings
description:
Broadcom BCM4708/47081/4709/47094/53012 Wi-Fi/network SoCs based
on the iProc architecture (Northstar).
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
- Hauke Mehrtens <hauke@hauke-m.de>
- Rafal Milecki <zajec5@gmail.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: BCM4708 based boards
items:
- enum:
- asus,rt-ac56u
- asus,rt-ac68u
- buffalo,wzr-1750dhp
- linksys,ea6300-v1
- linksys,ea6500-v2
- luxul,xap-1510v1
- luxul,xwc-1000
- netgear,r6250v1
- netgear,r6300v2
- smartrg,sr400ac
- brcm,bcm94708
- const: brcm,bcm4708
- description: BCM47081 based boards
items:
- enum:
- asus,rt-n18u
- buffalo,wzr-600dhp2
- buffalo,wzr-900dhp
- luxul,xap-1410v1
- luxul,xwr-1200v1
- tplink,archer-c5-v2
- const: brcm,bcm47081
- const: brcm,bcm4708
- description: BCM4709 based boards
items:
- enum:
- asus,rt-ac87u
- buffalo,wxr-1900dhp
- linksys,ea9200
- netgear,r7000
- netgear,r8000
- tplink,archer-c9-v1
- brcm,bcm94709
- const: brcm,bcm4709
- const: brcm,bcm4708
- description: BCM47094 based boards
items:
- enum:
- dlink,dir-885l
- linksys,panamera
- luxul,abr-4500-v1
- luxul,xap-1610-v1
- luxul,xbr-4500-v1
- luxul,xwc-2000-v1
- luxul,xwr-3100v1
- luxul,xwr-3150-v1
- netgear,r8500
- phicomm,k3
- const: brcm,bcm47094
- const: brcm,bcm4708
- description: BCM53012 based boards
items:
- enum:
- brcm,bcm953012er
- brcm,bcm953012hr
- brcm,bcm953012k
- const: brcm,brcm53012
- const: brcm,bcm4708
...

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Documentation/devicetree/bindings/arm/bcm/brcm,cygnus.txt
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Broadcom Cygnus device tree bindings
------------------------------------
Boards with Cygnus SoCs shall have the following properties:
Required root node property:
BCM11300
compatible = "brcm,bcm11300", "brcm,cygnus";
BCM11320
compatible = "brcm,bcm11320", "brcm,cygnus";
BCM11350
compatible = "brcm,bcm11350", "brcm,cygnus";
BCM11360
compatible = "brcm,bcm11360", "brcm,cygnus";
BCM58300
compatible = "brcm,bcm58300", "brcm,cygnus";
BCM58302
compatible = "brcm,bcm58302", "brcm,cygnus";
BCM58303
compatible = "brcm,bcm58303", "brcm,cygnus";
BCM58305
compatible = "brcm,bcm58305", "brcm,cygnus";

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@ -0,0 +1,29 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,cygnus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Cygnus device tree bindings
maintainers:
- Ray Jui <rjui@broadcom.com>
- Scott Branden <sbranden@broadcom.com>
properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- brcm,bcm11300
- brcm,bcm11320
- brcm,bcm11350
- brcm,bcm11360
- brcm,bcm58300
- brcm,bcm58302
- brcm,bcm58303
- brcm,bcm58305
- const: brcm,cygnus
...

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Documentation/devicetree/bindings/arm/bcm/brcm,hr2.txt
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Broadcom Hurricane 2 device tree bindings
---------------------------------------
Broadcom Hurricane 2 family of SoCs are used for switching control. These SoCs
are based on Broadcom's iProc SoC architecture and feature a single core Cortex
A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND
flash and a PCIe attached integrated switching engine.
Boards with Hurricane SoCs shall have the following properties:
Required root node property:
BCM53342
compatible = "brcm,bcm53342", "brcm,hr2";

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,hr2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Hurricane 2 device tree bindings
description:
Broadcom Hurricane 2 family of SoCs are used for switching control. These SoCs
are based on Broadcom's iProc SoC architecture and feature a single core Cortex
A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND
flash and a PCIe attached integrated switching engine.
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- ubnt,unifi-switch8
- const: brcm,bcm53342
- const: brcm,hr2
...

9
Documentation/devicetree/bindings/arm/bcm/brcm,ns2.txt
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Broadcom North Star 2 (NS2) device tree bindings
------------------------------------------------
Boards with NS2 shall have the following properties:
Required root node property:
NS2 SVK board
compatible = "brcm,ns2-svk", "brcm,ns2";

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,ns2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom North Star 2 (NS2) device tree bindings
maintainers:
- Ray Jui <rjui@broadcom.com>
- Scott Branden <sbranden@broadcom.com>
properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- brcm,ns2-svk
- brcm,ns2-xmc
- const: brcm,ns2
...

39
Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
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Broadcom Northstar Plus SoC CPU Enable Method
---------------------------------------------
This binding defines the enable method used for starting secondary
CPU in the following Broadcom SoCs:
BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
The enable method is specified by defining the following required
properties in the corresponding secondary "cpu" device tree node:
- enable-method = "brcm,bcm-nsp-smp";
- secondary-boot-reg = <...>;
The secondary-boot-reg property is a u32 value that specifies the
physical address of the register which should hold the common
entry point for a secondary CPU. This entry is cpu node specific
and should be added per cpu. E.g., in case of NSP (BCM58625) which
is a dual core CPU SoC, this entry should be added to cpu1 node.
Example:
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
enable-method = "brcm,bcm-nsp-smp";
secondary-boot-reg = <0xffff042c>;
reg = <1>;
};
};

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Broadcom Northstar Plus device tree bindings
--------------------------------------------
Broadcom Northstar Plus family of SoCs are used for switching control
and management applications as well as residential router/gateway
applications. The SoC features dual core Cortex A9 ARM CPUs, integrating
several peripheral interfaces including multiple Gigabit Ethernet PHYs,
DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
SATA and several other IO controllers.
Boards with Northstar Plus SoCs shall have the following properties:
Required root node property:
BCM58522
compatible = "brcm,bcm58522", "brcm,nsp";
BCM58525
compatible = "brcm,bcm58525", "brcm,nsp";
BCM58535
compatible = "brcm,bcm58535", "brcm,nsp";
BCM58622
compatible = "brcm,bcm58622", "brcm,nsp";
BCM58623
compatible = "brcm,bcm58623", "brcm,nsp";
BCM58625
compatible = "brcm,bcm58625", "brcm,nsp";
BCM88312
compatible = "brcm,bcm88312", "brcm,nsp";

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,nsp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Northstar Plus device tree bindings
description:
Broadcom Northstar Plus family of SoCs are used for switching control
and management applications as well as residential router/gateway
applications. The SoC features dual core Cortex A9 ARM CPUs, integrating
several peripheral interfaces including multiple Gigabit Ethernet PHYs,
DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
SATA and several other IO controllers.
maintainers:
- Ray Jui <rjui@broadcom.com>
- Scott Branden <sbranden@broadcom.com>
properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- brcm,bcm58522
- brcm,bcm58525
- brcm,bcm58535
- brcm,bcm58622
- brcm,bcm58623
- brcm,bcm58625
- brcm,bcm88312
- const: brcm,nsp
...

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Broadcom Stingray device tree bindings
------------------------------------------------
Boards with Stingray shall have the following properties:
Required root node property:
Stingray Combo SVK board
compatible = "brcm,bcm958742k", "brcm,stingray";
Stingray SST100 board
compatible = "brcm,bcm958742t", "brcm,stingray";

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,stingray.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Stingray device tree bindings
maintainers:
- Ray Jui <rjui@broadcom.com>
- Scott Branden <sbranden@broadcom.com>
properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- brcm,bcm958742k
- brcm,bcm958742t
- brcm,bcm958802a802x
- const: brcm,stingray
...

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Broadcom Vulcan device tree bindings
------------------------------------
Boards with Broadcom Vulcan shall have the following root property:
Broadcom Vulcan Evaluation Board:
compatible = "brcm,vulcan-eval", "brcm,vulcan-soc";
Generic Vulcan board:
compatible = "brcm,vulcan-soc";

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,vulcan-soc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Vulcan device tree bindings
maintainers:
- Robert Richter <rrichter@marvell.com>
properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- brcm,vulcan-eval
- cavium,thunderx2-cn9900
- const: brcm,vulcan-soc
...

33
Documentation/devicetree/bindings/arm/cpus.yaml
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@ -287,6 +287,39 @@ properties:
While optional, it is the preferred way to get access to
the cpu-core power-domains.
secondary-boot-reg:
$ref: '/schemas/types.yaml#/definitions/uint32'
description: |
Required for systems that have an "enable-method" property value of
"brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
This includes the following SoCs: |
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
The secondary-boot-reg property is a u32 value that specifies the
physical address of the register used to request the ROM holding pen
code release a secondary CPU. The value written to the register is
formed by encoding the target CPU id into the low bits of the
physical start address it should jump to.
if:
# If the enable-method property contains one of those values
properties:
enable-method:
contains:
enum:
- brcm,bcm11351-cpu-method
- brcm,bcm23550
- brcm,bcm-nsp-smp
# and if enable-method is present
required:
- enable-method
then:
required:
- secondary-boot-reg
required:
- device_type
- reg

74
arch/arm/boot/dts/bcm2711-rpi-4-b.dts
View File

@ -20,6 +20,7 @@ memory@0 {
};
aliases {
emmc2bus = &emmc2bus;
ethernet0 = &genet;
};
@ -71,6 +72,79 @@ expgpio: gpio {
};
};
&gpio {
/*
* Parts taken from rpi_SCH_4b_4p0_reduced.pdf and
* the official GPU firmware DT blob.
*
* Legend:
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "ID_SDA",
"ID_SCL",
"SDA1",
"SCL1",
"GPIO_GCLK",
"GPIO5",
"GPIO6",
"SPI_CE1_N",
"SPI_CE0_N",
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
"GPIO12",
"GPIO13",
/* Serial port */
"TXD1",
"RXD1",
"GPIO16",
"GPIO17",
"GPIO18",
"GPIO19",
"GPIO20",
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"GPIO26",
"GPIO27",
"RGMII_MDIO",
"RGMIO_MDC",
/* Used by BT module */
"CTS0",
"RTS0",
"TXD0",
"RXD0",
/* Used by Wifi */
"SD1_CLK",
"SD1_CMD",
"SD1_DATA0",
"SD1_DATA1",
"SD1_DATA2",
"SD1_DATA3",
/* Shared with SPI flash */
"PWM0_MISO",
"PWM1_MOSI",
"STATUS_LED_G_CLK",
"SPIFLASH_CE_N",
"SDA0",
"SCL0",
"RGMII_RXCLK",
"RGMII_RXCTL",
"RGMII_RXD0",
"RGMII_RXD1",
"RGMII_RXD2",
"RGMII_RXD3",
"RGMII_TXCLK",
"RGMII_TXCTL",
"RGMII_TXD0",
"RGMII_TXD1",
"RGMII_TXD2",
"RGMII_TXD3";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>;

25
arch/arm/boot/dts/bcm2711.dtsi
View File

@ -241,17 +241,32 @@ pwm1: pwm@7e20c800 {
status = "disabled";
};
hvs@7e400000 {
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
};
};
/*
* emmc2 has different DMA constraints based on SoC revisions. It was
* moved into its own bus, so as for RPi4's firmware to update them.
* The firmware will find whether the emmc2bus alias is defined, and if
* so, it'll edit the dma-ranges property below accordingly.
*/
emmc2bus: emmc2bus {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>;
dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
emmc2: emmc2@7e340000 {
compatible = "brcm,bcm2711-emmc2";
reg = <0x7e340000 0x100>;
reg = <0x0 0x7e340000 0x100>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clocks BCM2711_CLOCK_EMMC2>;
status = "disabled";
};
hvs@7e400000 {
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
};
};
arm-pmu {