ARM: dts: k2g-evm: Add DCAN dt nodes

The 66AK2G evm has support for dcan.
Add nodes and pinmuxes for dcan0 and dcan1.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
This commit is contained in:
Faiz Abbas 2018-05-04 23:11:49 -07:00 committed by Santosh Shilimkar
parent 60cc43fc88
commit 84cfd2c4f3

View File

@ -114,6 +114,20 @@ K2G_CORE_IOPAD(0x11ec) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart2
K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart2_txd.uart2_txd */
>;
};
dcan0_pins: pinmux_dcan0_pins {
pinctrl-single,pins = <
K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dcan0tx.dcan0tx */
K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* dcan0rx.dcan0rx */
>;
};
dcan1_pins: pinmux_dcan1_pins {
pinctrl-single,pins = <
K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* qspicsn2.dcan1tx */
K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE1) /* qspicsn3.dcan1rx */
>;
};
};
&uart0 {
@ -268,3 +282,15 @@ &uart2 {
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
&dcan0 {
pinctrl-names = "default";
pinctrl-0 = <&dcan0_pins>;
status = "okay";
};
&dcan1 {
pinctrl-names = "default";
pinctrl-0 = <&dcan1_pins>;
status = "okay";
};