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arm64: dts: qcom: qcs404: Add PSCI cpuidle low power states
Add device bindings for cpuidle states for cpu devices. Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> [amit: rename the idle-states to more generic names and fixups] Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
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@ -30,6 +30,7 @@ CPU0: cpu@100 {
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compatible = "arm,cortex-a53";
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reg = <0x100>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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next-level-cache = <&L2_0>;
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};
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@ -38,6 +39,7 @@ CPU1: cpu@101 {
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compatible = "arm,cortex-a53";
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reg = <0x101>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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next-level-cache = <&L2_0>;
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};
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@ -46,6 +48,7 @@ CPU2: cpu@102 {
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compatible = "arm,cortex-a53";
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reg = <0x102>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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next-level-cache = <&L2_0>;
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};
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@ -54,6 +57,7 @@ CPU3: cpu@103 {
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compatible = "arm,cortex-a53";
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reg = <0x103>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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next-level-cache = <&L2_0>;
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};
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@ -61,6 +65,20 @@ L2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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idle-states {
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entry-method = "psci";
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CPU_SLEEP_0: cpu-sleep-0 {
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compatible = "arm,idle-state";
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idle-state-name = "standalone-power-collapse";
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arm,psci-suspend-param = <0x40000003>;
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entry-latency-us = <125>;
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exit-latency-us = <180>;
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min-residency-us = <595>;
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local-timer-stop;
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};
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};
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};
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firmware {
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