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ath9k_hw: DDR_PLL and BB_PLL need correct setting.
Updates from the analog team for AR9485 chipsets to set DDR_PLL2 and DDR_PLL3. Also program the BB_PLL ki and kd value. Signed-off-by: Vivek Natarajan <vnatarajan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -681,13 +681,37 @@ unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
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}
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EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
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#define DPLL2_KD_VAL 0x3D
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#define DPLL2_KI_VAL 0x06
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#define DPLL3_PHASE_SHIFT_VAL 0x1
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static void ath9k_hw_init_pll(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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u32 pll;
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if (AR_SREV_9485(ah))
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if (AR_SREV_9485(ah)) {
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REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
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REG_WRITE(ah, AR_CH0_DDR_DPLL2, 0x19e82f01);
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REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
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AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
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REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
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udelay(100);
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REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
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REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
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AR_CH0_DPLL2_KD, DPLL2_KD_VAL);
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REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
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AR_CH0_DPLL2_KI, DPLL2_KI_VAL);
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REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
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AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
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REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x142c);
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udelay(110);
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}
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pll = ath9k_hw_compute_pll_control(ah, chan);
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@ -1083,6 +1083,17 @@ enum {
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#define AR_ENT_OTP 0x40d8
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#define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000
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#define AR_ENT_OTP_MPSD 0x00800000
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#define AR_CH0_BB_DPLL2 0x16184
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#define AR_CH0_BB_DPLL3 0x16188
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#define AR_CH0_DDR_DPLL2 0x16244
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#define AR_CH0_DDR_DPLL3 0x16248
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#define AR_CH0_DPLL2_KD 0x03F80000
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#define AR_CH0_DPLL2_KD_S 19
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#define AR_CH0_DPLL2_KI 0x3C000000
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#define AR_CH0_DPLL2_KI_S 26
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#define AR_CH0_DPLL3_PHASE_SHIFT 0x3F800000
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#define AR_CH0_DPLL3_PHASE_SHIFT_S 23
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#define AR_PHY_CCA_NOM_VAL_2GHZ -118
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#define AR_RTC_9300_PLL_DIV 0x000003ff
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#define AR_RTC_9300_PLL_DIV_S 0
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