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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 12:16:42 +07:00
ath9k: Fix a PLL hang issue observed with AR9485.
When this PLL hang issue is seen, both Rx and Tx fail to work. The sqsum_dvc needs to be below 2000 for a good chip. During this issue the sqsum_dvc value is beyond 80000 and only a full reset can solve this problem. Signed-off-by: Vivek Natarajan <vnatarajan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -641,6 +641,7 @@ struct ath_softc {
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#endif
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struct ath_beacon_config cur_beacon_conf;
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struct delayed_work tx_complete_work;
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struct delayed_work hw_pll_work;
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struct ath_btcoex btcoex;
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struct ath_descdma txsdma;
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@ -230,6 +230,7 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
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cancel_work_sync(&sc->paprd_work);
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cancel_work_sync(&sc->hw_check_work);
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cancel_delayed_work_sync(&sc->tx_complete_work);
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cancel_delayed_work_sync(&sc->hw_pll_work);
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ath9k_ps_wakeup(sc);
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@ -290,6 +291,7 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
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if (sc->sc_flags & SC_OP_BEACONS)
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ath_beacon_config(sc, NULL);
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ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
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ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
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ath_start_ani(common);
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}
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@ -1263,6 +1265,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
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cancel_delayed_work_sync(&sc->ath_led_blink_work);
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cancel_delayed_work_sync(&sc->tx_complete_work);
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cancel_delayed_work_sync(&sc->hw_pll_work);
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cancel_work_sync(&sc->paprd_work);
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cancel_work_sync(&sc->hw_check_work);
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@ -2091,6 +2091,28 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
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}
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}
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static void ath_hw_pll_work(struct work_struct *work)
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{
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struct ath_softc *sc = container_of(work, struct ath_softc,
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hw_pll_work.work);
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static int count;
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if (AR_SREV_9485(sc->sc_ah)) {
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if (ar9003_get_pll_sqsum_dvc(sc->sc_ah) >= 0x40000) {
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count++;
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if (count == 3) {
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/* Rx is hung for more than 500ms. Reset it */
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ath_reset(sc, true);
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count = 0;
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}
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} else
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count = 0;
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ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
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}
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}
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static void ath_tx_complete_poll_work(struct work_struct *work)
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{
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struct ath_softc *sc = container_of(work, struct ath_softc,
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@ -2312,6 +2334,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
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}
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INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
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INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
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if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
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error = ath_tx_edma_init(sc);
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