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drm/amd/display: add dcc programming for dual plane

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Add dual plane dcc programming support for
surfaces.

Removes unions from plane size and dcc params as they
serve no practical purpose only making our code
more convoluted. This results in easy dual plane
dcc and surface size programming.

Temporary diags_dm code is used to handle the interface
change without breaking functionality as a diags change
needs to be applied after this one.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin 2019-07-03 16:20:42 -04:00 committed by Alex Deucher
parent f7938bc0f0
commit 12e2b2d4c6
17 changed files with 136 additions and 138 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View File

@ -2672,7 +2672,7 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev,
const struct amdgpu_framebuffer *afb,
const enum surface_pixel_format format,
const enum dc_rotation_angle rotation,
const union plane_size *plane_size,
const struct plane_size *plane_size,
const union dc_tiling_info *tiling_info,
const uint64_t info,
struct dc_plane_dcc_param *dcc,
@ -2698,8 +2698,8 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev,
return -EINVAL;
input.format = format;
input.surface_size.width = plane_size->grph.surface_size.width;
input.surface_size.height = plane_size->grph.surface_size.height;
input.surface_size.width = plane_size->surface_size.width;
input.surface_size.height = plane_size->surface_size.height;
input.swizzle_mode = tiling_info->gfx9.swizzle;
if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
@ -2717,9 +2717,9 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev,
return -EINVAL;
dcc->enable = 1;
dcc->grph.meta_pitch =
dcc->meta_pitch =
AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
dcc->grph.independent_64b_blks = i64b;
dcc->independent_64b_blks = i64b;
dcc_address = get_dcc_address(afb->address, info);
address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
@ -2735,7 +2735,7 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
const enum dc_rotation_angle rotation,
const uint64_t tiling_flags,
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
struct plane_size *plane_size,
struct dc_plane_dcc_param *dcc,
struct dc_plane_address *address)
{
@ -2748,11 +2748,11 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
memset(address, 0, sizeof(*address));
if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
plane_size->grph.surface_size.x = 0;
plane_size->grph.surface_size.y = 0;
plane_size->grph.surface_size.width = fb->width;
plane_size->grph.surface_size.height = fb->height;
plane_size->grph.surface_pitch =
plane_size->surface_size.x = 0;
plane_size->surface_size.y = 0;
plane_size->surface_size.width = fb->width;
plane_size->surface_size.height = fb->height;
plane_size->surface_pitch =
fb->pitches[0] / fb->format->cpp[0];
address->type = PLN_ADDR_TYPE_GRAPHICS;
@ -2761,20 +2761,20 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
} else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
uint64_t chroma_addr = afb->address + fb->offsets[1];
plane_size->video.luma_size.x = 0;
plane_size->video.luma_size.y = 0;
plane_size->video.luma_size.width = fb->width;
plane_size->video.luma_size.height = fb->height;
plane_size->video.luma_pitch =
plane_size->surface_size.x = 0;
plane_size->surface_size.y = 0;
plane_size->surface_size.width = fb->width;
plane_size->surface_size.height = fb->height;
plane_size->surface_pitch =
fb->pitches[0] / fb->format->cpp[0];
plane_size->video.chroma_size.x = 0;
plane_size->video.chroma_size.y = 0;
plane_size->chroma_size.x = 0;
plane_size->chroma_size.y = 0;
/* TODO: set these based on surface format */
plane_size->video.chroma_size.width = fb->width / 2;
plane_size->video.chroma_size.height = fb->height / 2;
plane_size->chroma_size.width = fb->width / 2;
plane_size->chroma_size.height = fb->height / 2;
plane_size->video.chroma_pitch =
plane_size->chroma_pitch =
fb->pitches[1] / fb->format->cpp[1];
address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;

2
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
View File

@ -2852,7 +2852,7 @@ static void populate_initial_data(
data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.height);
data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.width);
data->pitch_in_pixels[num_displays * 2 + j] = bw_int_to_fixed(
pipe[i].bottom_pipe->plane_state->plane_size.grph.surface_pitch);
pipe[i].bottom_pipe->plane_state->plane_size.surface_pitch);
data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps);
data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.v_taps);
data->h_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed(

2
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
View File

@ -329,7 +329,7 @@ static void pipe_ctx_to_e2e_pipe_params (
dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0;
}
input->src.dcc_rate = 1;
input->src.meta_pitch = pipe->plane_state->dcc.grph.meta_pitch;
input->src.meta_pitch = pipe->plane_state->dcc.meta_pitch;
input->src.source_scan = dm_horz;
input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle;

10
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -1349,8 +1349,8 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa
}
if (u->plane_info->dcc.enable != u->surface->dcc.enable
|| u->plane_info->dcc.grph.independent_64b_blks != u->surface->dcc.grph.independent_64b_blks
|| u->plane_info->dcc.grph.meta_pitch != u->surface->dcc.grph.meta_pitch) {
|| u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
|| u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
update_flags->bits.dcc_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_MED);
}
@ -1364,9 +1364,9 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa
elevate_update_type(&update_type, UPDATE_TYPE_FULL);
}
if (u->plane_info->plane_size.grph.surface_pitch != u->surface->plane_size.grph.surface_pitch
|| u->plane_info->plane_size.video.luma_pitch != u->surface->plane_size.video.luma_pitch
|| u->plane_info->plane_size.video.chroma_pitch != u->surface->plane_size.video.chroma_pitch) {
if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
|| u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
|| u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
update_flags->bits.plane_size_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_MED);
}

40
drivers/gpu/drm/amd/display/dc/core/dc_debug.c
View File

@ -115,16 +115,16 @@ void pre_surface_trace(
plane_state->clip_rect.height);
SURFACE_TRACE(
"plane_state->plane_size.grph.surface_size.x = %d;\n"
"plane_state->plane_size.grph.surface_size.y = %d;\n"
"plane_state->plane_size.grph.surface_size.width = %d;\n"
"plane_state->plane_size.grph.surface_size.height = %d;\n"
"plane_state->plane_size.grph.surface_pitch = %d;\n",
plane_state->plane_size.grph.surface_size.x,
plane_state->plane_size.grph.surface_size.y,
plane_state->plane_size.grph.surface_size.width,
plane_state->plane_size.grph.surface_size.height,
plane_state->plane_size.grph.surface_pitch);
"plane_state->plane_size.surface_size.x = %d;\n"
"plane_state->plane_size.surface_size.y = %d;\n"
"plane_state->plane_size.surface_size.width = %d;\n"
"plane_state->plane_size.surface_size.height = %d;\n"
"plane_state->plane_size.surface_pitch = %d;\n",
plane_state->plane_size.surface_size.x,
plane_state->plane_size.surface_size.y,
plane_state->plane_size.surface_size.width,
plane_state->plane_size.surface_size.height,
plane_state->plane_size.surface_pitch);
SURFACE_TRACE(
@ -202,20 +202,20 @@ void update_surface_trace(
SURFACE_TRACE(
"plane_info->color_space = %d;\n"
"plane_info->format = %d;\n"
"plane_info->plane_size.grph.surface_pitch = %d;\n"
"plane_info->plane_size.grph.surface_size.height = %d;\n"
"plane_info->plane_size.grph.surface_size.width = %d;\n"
"plane_info->plane_size.grph.surface_size.x = %d;\n"
"plane_info->plane_size.grph.surface_size.y = %d;\n"
"plane_info->plane_size.surface_pitch = %d;\n"
"plane_info->plane_size.surface_size.height = %d;\n"
"plane_info->plane_size.surface_size.width = %d;\n"
"plane_info->plane_size.surface_size.x = %d;\n"
"plane_info->plane_size.surface_size.y = %d;\n"
"plane_info->rotation = %d;\n"
"plane_info->stereo_format = %d;\n",
update->plane_info->color_space,
update->plane_info->format,
update->plane_info->plane_size.grph.surface_pitch,
update->plane_info->plane_size.grph.surface_size.height,
update->plane_info->plane_size.grph.surface_size.width,
update->plane_info->plane_size.grph.surface_size.x,
update->plane_info->plane_size.grph.surface_size.y,
update->plane_info->plane_size.surface_pitch,
update->plane_info->plane_size.surface_size.height,
update->plane_info->plane_size.surface_size.width,
update->plane_info->plane_size.surface_size.x,
update->plane_info->plane_size.surface_size.y,
update->plane_info->rotation,
update->plane_info->stereo_format);

4
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -705,7 +705,7 @@ struct dc_plane_state {
struct rect dst_rect;
struct rect clip_rect;
union plane_size plane_size;
struct plane_size plane_size;
union dc_tiling_info tiling_info;
struct dc_plane_dcc_param dcc;
@ -754,7 +754,7 @@ struct dc_plane_state {
};
struct dc_plane_info {
union plane_size plane_size;
struct plane_size plane_size;
union dc_tiling_info tiling_info;
struct dc_plane_dcc_param dcc;
enum surface_pixel_format format;

54
drivers/gpu/drm/amd/display/dc/dc_hw_types.h
View File

@ -115,42 +115,40 @@ struct rect {
int height;
};
union plane_size {
/* Grph or Video will be selected
* based on format above:
* Use Video structure if
* format >= DalPixelFormat_VideoBegin
* else use Grph structure
struct plane_size {
/* Graphic surface pitch in pixels.
* In LINEAR_GENERAL mode, pitch
* is 32 pixel aligned.
*/
struct {
struct rect surface_size;
/* Graphic surface pitch in pixels.
* In LINEAR_GENERAL mode, pitch
* is 32 pixel aligned.
*/
int surface_pitch;
} grph;
int surface_pitch;
int chroma_pitch;
struct rect surface_size;
struct rect chroma_size;
struct {
struct rect luma_size;
/* Graphic surface pitch in pixels.
* In LINEAR_GENERAL mode, pitch is
* 32 pixel aligned.
*/
int luma_pitch;
union {
struct {
struct rect surface_size;
int surface_pitch;
} grph;
struct rect chroma_size;
/* Graphic surface pitch in pixels.
* In LINEAR_GENERAL mode, pitch is
* 32 pixel aligned.
*/
int chroma_pitch;
} video;
struct {
struct rect luma_size;
int luma_pitch;
struct rect chroma_size;
int chroma_pitch;
} video;
};
};
struct dc_plane_dcc_param {
bool enable;
int meta_pitch;
bool independent_64b_blks;
int meta_pitch_c;
bool independent_64b_blks_c;
union {
struct {
int meta_pitch;

10
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
View File

@ -391,10 +391,10 @@ static void program_tiling(
static void program_size_and_rotation(
struct dce_mem_input *dce_mi,
enum dc_rotation_angle rotation,
const union plane_size *plane_size)
const struct plane_size *plane_size)
{
const struct rect *in_rect = &plane_size->grph.surface_size;
struct rect hw_rect = plane_size->grph.surface_size;
const struct rect *in_rect = &plane_size->surface_size;
struct rect hw_rect = plane_size->surface_size;
const uint32_t rotation_angles[ROTATION_ANGLE_COUNT] = {
[ROTATION_ANGLE_0] = 0,
[ROTATION_ANGLE_90] = 1,
@ -423,7 +423,7 @@ static void program_size_and_rotation(
GRPH_Y_END, hw_rect.height);
REG_SET(GRPH_PITCH, 0,
GRPH_PITCH, plane_size->grph.surface_pitch);
GRPH_PITCH, plane_size->surface_pitch);
REG_SET(HW_ROTATION, 0,
GRPH_ROTATION_ANGLE, rotation_angles[rotation]);
@ -505,7 +505,7 @@ static void dce_mi_program_surface_config(
struct mem_input *mi,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
struct plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
bool horizontal_mirror)

42
drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
View File

@ -229,26 +229,26 @@ static void program_tiling(
static void program_size_and_rotation(
struct dce_mem_input *mem_input110,
enum dc_rotation_angle rotation,
const union plane_size *plane_size)
const struct plane_size *plane_size)
{
uint32_t value = 0;
union plane_size local_size = *plane_size;
struct plane_size local_size = *plane_size;
if (rotation == ROTATION_ANGLE_90 ||
rotation == ROTATION_ANGLE_270) {
swap(local_size.video.luma_size.x,
local_size.video.luma_size.y);
swap(local_size.video.luma_size.width,
local_size.video.luma_size.height);
swap(local_size.video.chroma_size.x,
local_size.video.chroma_size.y);
swap(local_size.video.chroma_size.width,
local_size.video.chroma_size.height);
swap(local_size.surface_size.x,
local_size.surface_size.y);
swap(local_size.surface_size.width,
local_size.surface_size.height);
swap(local_size.chroma_size.x,
local_size.chroma_size.y);
swap(local_size.chroma_size.width,
local_size.chroma_size.height);
}
value = 0;
set_reg_field_value(value, local_size.video.luma_pitch,
set_reg_field_value(value, local_size.surface_pitch,
UNP_GRPH_PITCH_L, GRPH_PITCH_L);
dm_write_reg(
@ -257,7 +257,7 @@ static void program_size_and_rotation(
value);
value = 0;
set_reg_field_value(value, local_size.video.chroma_pitch,
set_reg_field_value(value, local_size.chroma_pitch,
UNP_GRPH_PITCH_C, GRPH_PITCH_C);
dm_write_reg(
mem_input110->base.ctx,
@ -297,8 +297,8 @@ static void program_size_and_rotation(
value);
value = 0;
set_reg_field_value(value, local_size.video.luma_size.x +
local_size.video.luma_size.width,
set_reg_field_value(value, local_size.surface_size.x +
local_size.surface_size.width,
UNP_GRPH_X_END_L, GRPH_X_END_L);
dm_write_reg(
mem_input110->base.ctx,
@ -306,8 +306,8 @@ static void program_size_and_rotation(
value);
value = 0;
set_reg_field_value(value, local_size.video.chroma_size.x +
local_size.video.chroma_size.width,
set_reg_field_value(value, local_size.chroma_size.x +
local_size.chroma_size.width,
UNP_GRPH_X_END_C, GRPH_X_END_C);
dm_write_reg(
mem_input110->base.ctx,
@ -315,8 +315,8 @@ static void program_size_and_rotation(
value);
value = 0;
set_reg_field_value(value, local_size.video.luma_size.y +
local_size.video.luma_size.height,
set_reg_field_value(value, local_size.surface_size.y +
local_size.surface_size.height,
UNP_GRPH_Y_END_L, GRPH_Y_END_L);
dm_write_reg(
mem_input110->base.ctx,
@ -324,8 +324,8 @@ static void program_size_and_rotation(
value);
value = 0;
set_reg_field_value(value, local_size.video.chroma_size.y +
local_size.video.chroma_size.height,
set_reg_field_value(value, local_size.chroma_size.y +
local_size.chroma_size.height,
UNP_GRPH_Y_END_C, GRPH_Y_END_C);
dm_write_reg(
mem_input110->base.ctx,
@ -637,7 +637,7 @@ void dce_mem_input_v_program_surface_config(
struct mem_input *mem_input,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
struct plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
bool horizotal_mirror)

20
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
View File

@ -163,7 +163,7 @@ void hubp1_program_tiling(
void hubp1_program_size(
struct hubp *hubp,
enum surface_pixel_format format,
const union plane_size *plane_size,
const struct plane_size *plane_size,
struct dc_plane_dcc_param *dcc)
{
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
@ -173,16 +173,16 @@ void hubp1_program_size(
* 444 or 420 luma
*/
if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) {
ASSERT(plane_size->video.chroma_pitch != 0);
ASSERT(plane_size->chroma_pitch != 0);
/* Chroma pitch zero can cause system hang! */
pitch = plane_size->video.luma_pitch - 1;
meta_pitch = dcc->video.meta_pitch_l - 1;
pitch_c = plane_size->video.chroma_pitch - 1;
meta_pitch_c = dcc->video.meta_pitch_c - 1;
pitch = plane_size->surface_pitch - 1;
meta_pitch = dcc->meta_pitch - 1;
pitch_c = plane_size->chroma_pitch - 1;
meta_pitch_c = dcc->meta_pitch_c - 1;
} else {
pitch = plane_size->grph.surface_pitch - 1;
meta_pitch = dcc->grph.meta_pitch - 1;
pitch = plane_size->surface_pitch - 1;
meta_pitch = dcc->meta_pitch - 1;
pitch_c = 0;
meta_pitch_c = 0;
}
@ -526,13 +526,13 @@ void hubp1_program_surface_config(
struct hubp *hubp,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
struct plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
bool horizontal_mirror,
unsigned int compat_level)
{
hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks);
hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
hubp1_program_tiling(hubp, tiling_info, format);
hubp1_program_size(hubp, format, plane_size, dcc);
hubp1_program_rotation(hubp, rotation, horizontal_mirror);

4
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
View File

@ -685,7 +685,7 @@ void hubp1_program_surface_config(
struct hubp *hubp,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
struct plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
bool horizontal_mirror,
@ -707,7 +707,7 @@ void hubp1_program_pixel_format(
void hubp1_program_size(
struct hubp *hubp,
enum surface_pixel_format format,
const union plane_size *plane_size,
const struct plane_size *plane_size,
struct dc_plane_dcc_param *dcc);
void hubp1_program_rotation(

4
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@ -2132,7 +2132,7 @@ void update_dchubp_dpp(
struct hubp *hubp = pipe_ctx->plane_res.hubp;
struct dpp *dpp = pipe_ctx->plane_res.dpp;
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
union plane_size size = plane_state->plane_size;
struct plane_size size = plane_state->plane_size;
unsigned int compat_level = 0;
/* depends on DML calculation, DPP clock value may change dynamically */
@ -2178,7 +2178,7 @@ void update_dchubp_dpp(
&pipe_ctx->ttu_regs);
}
size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
if (plane_state->update_flags.bits.full_update ||
plane_state->update_flags.bits.bpp_change)

20
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
View File

@ -397,7 +397,7 @@ static void hubp2_program_tiling(
void hubp2_program_size(
struct hubp *hubp,
enum surface_pixel_format format,
const union plane_size *plane_size,
const struct plane_size *plane_size,
struct dc_plane_dcc_param *dcc)
{
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
@ -410,16 +410,16 @@ void hubp2_program_size(
use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
&& format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END;
if (use_pitch_c) {
ASSERT(plane_size->video.chroma_pitch != 0);
ASSERT(plane_size->chroma_pitch != 0);
/* Chroma pitch zero can cause system hang! */
pitch = plane_size->video.luma_pitch - 1;
meta_pitch = dcc->video.meta_pitch_l - 1;
pitch_c = plane_size->video.chroma_pitch - 1;
meta_pitch_c = dcc->video.meta_pitch_c - 1;
pitch = plane_size->surface_pitch - 1;
meta_pitch = dcc->meta_pitch - 1;
pitch_c = plane_size->chroma_pitch - 1;
meta_pitch_c = dcc->meta_pitch_c - 1;
} else {
pitch = plane_size->grph.surface_pitch - 1;
meta_pitch = dcc->grph.meta_pitch - 1;
pitch = plane_size->surface_pitch - 1;
meta_pitch = dcc->meta_pitch - 1;
pitch_c = 0;
meta_pitch_c = 0;
}
@ -592,7 +592,7 @@ void hubp2_program_surface_config(
struct hubp *hubp,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
struct plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
bool horizontal_mirror,
@ -600,7 +600,7 @@ void hubp2_program_surface_config(
{
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
hubp2_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks);
hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
hubp2_program_tiling(hubp2, tiling_info, format);
hubp2_program_size(hubp, format, plane_size, dcc);
hubp2_program_rotation(hubp, rotation, horizontal_mirror);

4
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
View File

@ -273,7 +273,7 @@ void hubp2_dcc_control(struct hubp *hubp, bool enable,
void hubp2_program_size(
struct hubp *hubp,
enum surface_pixel_format format,
const union plane_size *plane_size,
const struct plane_size *plane_size,
struct dc_plane_dcc_param *dcc);
void hubp2_program_rotation(
@ -289,7 +289,7 @@ void hubp2_program_surface_config(
struct hubp *hubp,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
struct plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
bool horizontal_mirror,

12
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
View File

@ -1822,13 +1822,13 @@ int dcn20_populate_dml_pipes_from_context(
pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.video.luma_pitch;
pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.video.chroma_pitch;
pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.video.meta_pitch_l;
pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.video.meta_pitch_c;
pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
} else {
pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.grph.surface_pitch;
pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.grph.meta_pitch;
pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
}
pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;

2
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
View File

@ -103,7 +103,7 @@ struct hubp_funcs {
struct hubp *hubp,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
struct plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
bool horizontal_mirror,

2
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
View File

@ -149,7 +149,7 @@ struct mem_input_funcs {
struct mem_input *mem_input,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
struct plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
bool horizontal_mirror);